CHAPTER 3: Epitaxy
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Surface Diffusion Driven by Surface Energy
Spring 2004 Evolving Small Structures Z. Suo Lecture 6 Surface Diffusion Driven by Surface Energy Examples Flattening a surface. Spherodizing. Rayleigh instability. Grain boundary grooving. Sintering Self-assembled quantum dots Atomic Flux and Surface Velocity Atoms can arrive to the surface in many ways. Atoms in the vapor can condense to the surface. Or conversely, atoms on the solid surface can evaporate. Atoms can diffuse in the volume of the solid. The body can also change shape by creep. In this lecture, we assume atoms can only move on the surface by diffusion, and all other modes of transport are negligibly slow. This situation happens for crystals at relatively low temperature, in a low vapor pressure environment. Define the atomic flux on a solid surface by numberof atoms J = ()length (time) Note that this flux is a vector tangent to the surface, and has a different dimension from that in the bulk. The flux is a vector field on the solid surface Consider a small element of the surface of the body. Let vn be the velocity of the solid surface, taken to be positive when the surface element gains atoms. The velocity is normal to the solid surface. The velocity is a scalar field on the solid surface. February 21, 2009 1 Spring 2004 Evolving Small Structures Z. Suo The surface element extends when it gains atoms, and recedes when it loses atoms. Let Ω be the volume per atom in the solid. Thus, vn / Ω is the number of atoms gained per unit area and per unit time. -
21St American Conference on Crystal Growth and Epitaxy (ACCGE-21)
Program Book 21st American Conference on Crystal Growth and Epitaxy (ACCGE-21) and 18th US Workshop on Organometallic Vapor Phase Epitaxy (OMVPE-18) and 3rd Symposium on 2D Electronic Materials and Symposium on Epitaxy of Complex Oxides July 30 – August 4 1 | P a g e Table of Contents Table of Contents ........................................................................................................... 2 Welcome to Santa Fe, New Mexico………………………………...………………………..3 Maps of Conference Area and Resort ............................................................................ 4 Conference Sponsors & Supporters ............................................................................... 7 Conference Exhibitors .................................................................................................... 7 Conference Organizers .................................................................................................. 8 OMVPE Workshop Committee………………………. ...................................................... 9 AACG Organization (2015-2017) ................................................................................. 10 ACCGE Symposia and Organizers .................................................... ………………….11 Plenary Speakers ............................................................................... ………………….13 Award Recipients ............................................................................... ………………….14 Scope and Purpose of the Conferences ...................................................................... -
Microchip Manufacturing
Si3N4 Deposition & the Virtual Chemical Vapor Deposition Lab Making a transistor, the general process A closer look at chemical vapor deposition and the virtual lab Images courtesy Silicon Run Educational Video, VCVD Lab Screenshot Why Si3N4 Deposition…Making Microprocessors http://www.sonyericsson.com/cws/products/mobilephones /overview/x1?cc=us&lc=en http://vista.pca.org/yos/Porsche-911-Turbo.jpg On a wafer, billions of transistors are housed on a single square chip. One malfunctioning transistor could cause a chip to short-circuit, ruining the chip. Thus, the process of creating each microscopic transistor must be very precise. Wafer image: http://upload.wikimedia.org/wikipedia/fr/thumb/2/2b/PICT0214.JPG/300px-PICT0214.JPG What size do you think an individual transistor being made today is? Size of Transistors One chip is made of millions or billions of transistors packed into a length and width of less than half an inch. Channel lengths in MOSFET transistors are less than a tenth of a micrometer. Human hair is approximately 100 micrometers in diameter. Scaling of successive generations of MOSFETs into the nanoscale regime (from Intel). Transistor: MOS We will illustrate the process sequence of creating a transistor with a Metal Oxide Semiconductor(MOS) transistor. Wafers – 12” Diameter ½” to ¾” Source Gate Drain conductor Insulator n-Si n-Si p-Si Image courtesy: Pro. Milo Koretsky Chemical Engineering Department at OSU IC Manufacturing Process IC Processing consists of selectively adding material (Conductor, insulator, semiconductor) to, removing it from or modifying it Wafers Deposition / Photo/ Ion Implant / Pattern Etching / CMP Oxidation Anneal Clean Clean Transfer Loop (Note that these steps are not all the steps to create a transistor. -
Three-Dimensional Integrated Circuit Design: EDA, Design And
Integrated Circuits and Systems Series Editor Anantha Chandrakasan, Massachusetts Institute of Technology Cambridge, Massachusetts For other titles published in this series, go to http://www.springer.com/series/7236 Yuan Xie · Jason Cong · Sachin Sapatnekar Editors Three-Dimensional Integrated Circuit Design EDA, Design and Microarchitectures 123 Editors Yuan Xie Jason Cong Department of Computer Science and Department of Computer Science Engineering University of California, Los Angeles Pennsylvania State University [email protected] [email protected] Sachin Sapatnekar Department of Electrical and Computer Engineering University of Minnesota [email protected] ISBN 978-1-4419-0783-7 e-ISBN 978-1-4419-0784-4 DOI 10.1007/978-1-4419-0784-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009939282 © Springer Science+Business Media, LLC 2010 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Foreword We live in a time of great change. -
Epitaxy and Characterization of Sigec Layers Grown by Reduced Pressure Chemical Vapor Deposition
Epitaxy and characterization of SiGeC layers grown by reduced pressure chemical vapor deposition Licentiate Thesis by Julius Hållstedt Stockholm, Sweden 2004 Laboratory of Semiconductor materials, Department of Microelectronics and Information Technology (IMIT), Royal Institute of Technology (KTH) Epitaxy and characterization of SiGeC layers grown by reduced pressure chemical vapor deposition A dissertation submitted to the Royal Institute of Technology, Stockholm, Sweden, in partial fulfillment of the requirements for the degree of Teknologie Licentiat. TRITA-HMA REPORT 2004:1 ISSN 1404-0379 ISRN KTH/HMA/FR-04/1-SE © Julius Hållstedt, March 2004 This thesis is available in electronic version at: http://media.lib.kth.se Printed by Universitetsservice US AB, Stockholm 2004 ii Julius Hållstedt Epitaxy and characterization of SiGeC layers grown by reduced pressure chemical vapor deposition Laboratory of Semiconductor Materials (HMA), Department of Microelectronics and Information Technology (IMIT), Royal Institute of Technology (KTH), Stockholm, Sweden TRITA-HMA Report 2004:1, ISSN 1404-0379, ISRN KTH/HMA/FR-04/1-SE Abstract Heteroepitaxial SiGeC layers have attracted immense attention as a material for high frequency devices during recent years. The unique properties of integrating carbon in SiGe are the additional freedom for strain and bandgap engineering as well as allowing more aggressive device design due to the potential for increased thermal budget during processing. This work presents different issues on epitaxial growth, defect density, dopant incorporation and electrical properties of SiGeC epitaxial layers, intended for various device applications. Non-selective and selective epitaxial growth of Si1-x-yGexCy (0≤x≤0.30, 0≤y≤0.02) layers have been optimized by using high-resolution x-ray reciprocal lattice mapping. -
Single Adatom Adsorption and Diffusion on Fe Surfaces
Journal of Modern Physics, 2011, 2, 1067-1072 1067 doi:10.4236/jmp.2011.29130 Published Online September 2011 (http://www.SciRP.org/journal/jmp) Single Adatom Adsorption and Diffusion on Fe Surfaces Changqing Wang1*, Dahu Chang2, Chunjuan Tang2, Jianfeng Su2, Yongsheng Zhang2, Yu Jia3 1Department of Civil Engineering, Luoyang Institute of Science and Technology, Luoyang, China 2Department of Mathematics and Physics, Luoyang Institute of Science and Technology, Luoyang, China 3School of Physics and Engineering, Key Laboratory of Material Physics of Ministry of Education, Zhengzhou University, Zhengzhou, China E-mail: *[email protected] Received December 25, 2010; revised March 22, 2011; accepted April 8, 2011 Abstract Using Embedded-atom-method (EAM) potential, we have performed in detail molecular dynamics studies on a Fe adatom adsorption and diffusion dynamics on three low miller index surfaces, Fe (110), Fe (001), and Fe (111). Our results present that adatom adsorption energies and diffusion barriers on these surfaces have similar monotonic trend: adsorption energies, Ea(110) < Ea(001) < Ea(111), diffusion barriers, Ed(110) < Ed(001) < Ed(111). On the Fe (110) surface, adatom simple jump is the main diffusion mechanism with relatively low energy barrier; nevertheless, adatoms exchange with surface atoms play a dominant role in surface diffusion on the Fe (001). Keywords: EAM Potential, Molecular Dynamics, Diffusion, Nudged Elastic Band (NEB) Method, Iron, Adsorption 1. Introduction and Monte Carlo (MC) [16,17], it has been investigated intensively [18]. Understanding the processes of nucleation and growth on Iron is a very common metal for application. Abun- a substrate surface is of importance for growing high- dant work has been done on atom diffusion on the Fe quality thin film materials. -
Single-Crystal Metal Growth on Amorphous Insulating Substrates
Single-crystal metal growth on amorphous insulating substrates Kai Zhanga,1, Xue Bai Pitnera,1, Rui Yanga, William D. Nixb,2, James D. Plummera, and Jonathan A. Fana,2 aDepartment of Electrical Engineering, Stanford University, Stanford, CA 94305; and bDepartment of Materials Science and Engineering, Stanford University, Stanford, CA 94305 Contributed by William D. Nix, December 1, 2017 (sent for review October 12, 2017; reviewed by Hanchen Huang, David J. Srolovitz, and Carl Thompson) Metal structures on insulators are essential components in advanced Our method is based on liquid phase epitaxy, in which the electronic and nanooptical systems. Their electronic and optical polycrystalline metal structures are encapsulated in an amor- properties are closely tied to their crystal quality, due to the strong phous insulating crucible, together with polycrystalline seed dependence of carrier transport and band structure on defects and structures of differing material, and heated to the liquid phase. grain boundaries. Here we report a method for creating patterned As the system cools, the metal solidifies into single crystals. single-crystal metal microstructures on amorphous insulating sub- Liquid phase epitaxy has been previously studied in the context of strates, using liquid phase epitaxy. In this process, the patterned semiconductor-on-oxide growth (24–26), but has not been ex- metal microstructures are encapsulated in an insulating crucible, plored for metal growth. We will examine gold as a model system together with a small seed of a differing material. The system is in this study. Gold is an essential material in electronics and heated to temperatures above the metal melting point, followed by plasmonics because of its high conductivity and chemical inertness. -
Heterogeneous Electrocatalysis in Porous Cathodes of Solid Oxide Fuel Cells
Electrochimica Acta 159 (2015) 71–80 Contents lists available at ScienceDirect Electrochimica Acta journa l homepage: www.elsevier.com/locate/electacta Heterogeneous electrocatalysis in porous cathodes of solid oxide fuel cells a b a,c b b b a,d, Y. Fu , S. Poizeau , A. Bertei , C. Qi , A. Mohanram , J.D. Pietras , M.Z. Bazant * a Department of Chemical Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA b Saint-Gobain Ceramics and Plastics, Northboro Research and Development Center, Northboro, MA, USA c Department of Civil and Industrial Engineering, University of Pisa, Italy d Department of Mathematics, Massachusetts Institute of Technology, Cambridge, MA, USA A R T I C L E I N F O A B S T R A C T Article history: A general physics-based model is developed for heterogeneous electrocatalysis in porous electrodes and Received 3 December 2014 used to predict and interpret the impedance of solid oxide fuel cells. This model describes the coupled Received in revised form 19 January 2015 processes of oxygen gas dissociative adsorption and surface diffusion of the oxygen intermediate to the Accepted 22 January 2015 triple phase boundary, where charge transfer occurs. The model accurately captures the Gerischer-like Available online 24 January 2015 frequency dependence and the oxygen partial pressure dependence of the impedance of symmetric cathode cells. Digital image analysis of the microstructure of the cathode functional layer in four different Keywords: cells directly confirms the predicted connection between geometrical properties and the impedance electrochemical impedance spectroscopy response. As in classical catalysis, the electrocatalytic activity is controlled by an effective Thiele (EIS) modulus, which is the ratio of the surface diffusion length (mean distance from an adsorption site to the Gerischer element porous electrode triple phase boundary) to the surface boundary layer length (square root of surface diffusivity divided by oxygen reduction reaction (ORR) the adsorption rate constant). -
A Study of Surface Diffusion with the Scanning Tunneling Microscope from Fluctuations of the Tunneling Current Manuel Leonardo Pasetes Lozano Iowa State University
Iowa State University Capstones, Theses and Retrospective Theses and Dissertations Dissertations 1995 A study of surface diffusion with the scanning tunneling microscope from fluctuations of the tunneling current Manuel Leonardo Pasetes Lozano Iowa State University Follow this and additional works at: https://lib.dr.iastate.edu/rtd Part of the Condensed Matter Physics Commons Recommended Citation Pasetes Lozano, Manuel Leonardo, "A study of surface diffusion with the scanning tunneling microscope from fluctuations of the tunneling current " (1995). Retrospective Theses and Dissertations. 10959. https://lib.dr.iastate.edu/rtd/10959 This Dissertation is brought to you for free and open access by the Iowa State University Capstones, Theses and Dissertations at Iowa State University Digital Repository. It has been accepted for inclusion in Retrospective Theses and Dissertations by an authorized administrator of Iowa State University Digital Repository. For more information, please contact [email protected]. INFORMATION TO USERS This manuscr^t has been reproduced from the nuarofilm master. UMI films tiie text directfy from the original or copy submitted. Hius, some thesis and dissertation copies are in typewriter face, while others may be £rom aiQr type of conq)uter printer. The qnality of this Feprodnction is dependent upon the qoali^ of the copy submitted. Broken or indistinct print, colored or poor quality illustrations and photographs, print bleedthrough, substandard margirnt^ and is^oper alignment can adverse^ affect reproduction. In the unlikely event that the author did not send UMI a complete manuscript and there are missing pages, these will be noted. Also, if unauthorized copyright material had to be removed, a note wiQ indicate the deletion. -
Thin-Film Silicon Solar Cells
SOLAR CELLS Chapter 7. Thin-Film Silicon Solar Cells Chapter 7. THIN-FILM SILICON SOLAR CELLS 7.1 Introduction The simplest semiconductor junction that is used in solar cells for separating photo- generated charge carriers is the p-n junction, an interface between the p-type region and n- type region of one semiconductor. Therefore, the basic semiconductor property of a material, the possibility to vary its conductivity by doping, has to be demonstrated first before the material can be considered as a suitable candidate for solar cells. This was the case for amorphous silicon. The first amorphous silicon layers were reported in 1965 as films of "silicon from silane" deposited in a radio frequency glow discharge1. Nevertheless, it took more ten years until Spear and LeComber, scientists from Dundee University, demonstrated that amorphous silicon had semiconducting properties by showing that amorphous silicon could be doped n- type and p-type by adding phosphine or diborane to the glow discharge gas mixture, respectively2. This was a far-reaching discovery since until that time it had been generally thought that amorphous silicon could not be doped. At that time it was not recognised immediately that hydrogen played an important role in the newly made amorphous silicon doped films. In fact, amorphous silicon suitable for electronic applications, where doping is required, is an alloy of silicon and hydrogen. The electronic-grade amorphous silicon is therefore called hydrogenated amorphous silicon (a-Si:H). 1 H.F. Sterling and R.C.G. Swann, Solid-State Electron. 8 (1965) p. 653-654. 2 W. Spear and P. -
6Th International Workshop on Crystal Growth Technology
GERMANY, JUNE 15 - 19 BERLIN 2014 6th International Workshop on Crystal Growth Technology THE FUTURE OF Advances in bulk crystal growth of semiconductor & photovoltaic materials CRYSTAL GROWTH Optical and laser crystals TECHNOLOGY – Scintillators, piezo- and magnetoelectrics BRINGING NEW Substrates for wide band-gap and oxide semiconductors TECHNOLOGIES TO Growth control, quality assurance, and management of resources INDUSTRIAL GROWTH Crystal shaping and layer transfer technologies APPLICATION Frontiers in crystal growth technology Leibniz Institute for International Organization Crystal Growth (IKZ) for Crystal Growth The Organizing Committee would like to acknowledge support provided by CrysTec GmbH Köpenicker Str. 325 D-12555 Berlin, Germany http://www.crystec.de Deutsche Forschungsgemeinschaft e.V. Kennedyallee 40 53175 Bonn, Germany http://www.dfg.de EFG GmbH Beeskowdamm 6 D-14167 Berlin, Germany http://www.efg-berlin.de Leibniz Institute for Crystal Growth Max-Born-Str. 2 D-12489 Berlin, Germany http://www.ikz-berlin.de PVA TePla AG Im Westpark 10 - 12 35435 Wettenberg, Germany http://www.pvatepla.com STR Group, Inc. Engels av. 27, P.O. Box 89, 194156 St. Petersburg, Russia http://www.str-soft.com Systec Johann-Schöner-Str. 73 D-97753 Karlstadt http://www.systec-sa.de Takatori Corporation European Representative JTA Equipment Technology 34 St Peters Wharf Newcastle upon Tyne, NE6 1TW, UK http://www.jta-ltd.com Umicore Electro-Optic Materials Watertorenstraat 33 B-2250, Olen, Belgium http://eom.umicore.com/en/eom/ IWCGT-6 6th International Workshop on Crystal Growth Technology Berlin, Germany June 15 - 19, 2014 Systec Johann-Schöner-Str. 73 D-97753 Karlstadt http://www.systec-sa.de IWCGT-6 2014 3 4 IWCGT-6 2014 Welcome message Dear participants of the IWCGT-6, a warm welcome to you, and sincere thanks that you take part in this exciting event, the 6th International Workshop on Crystal Growth Technology (IWCGT-6) held at June 15-19, 2014 at the Novotel Am Tiergarten, Berlin, Germany. -
Semiconductor Industry
Semiconductor industry Heat transfer solutions for the semiconductor manufacturing industry In the microelectronics industry a the cleanroom, an area where the The following applications are all semiconductor fabrication plant environment is controlled to manufactured in a semicon fab: (commonly called a fab) is a factory eliminate all dust – even a single where devices such as integrated speck can ruin a microcircuit, which Microchips: Manufacturing of chips circuits are manufactured. A business has features much smaller than with integrated circuits. that operates a semiconductor fab for dust. The cleanroom must also be LED lighting: Manufacturing of LED the purpose of fabricating the designs dampened against vibration and lamps for lighting purposes. of other companies, such as fabless kept within narrow bands of PV industry: Manufacturing of solar semiconductor companies, is known temperature and humidity. cells, based on Si wafer technology or as a foundry. If a foundry does not also thin film technology. produce its own designs, it is known Controlling temperature and Flat panel displays: Manufacturing of as a pure-play semiconductor foundry. humidity is critical for minimizing flat panels for everything from mobile static electricity. phones and other handheld devices, Fabs require many expensive devices up to large size TV monitors. to function. The central part of a fab is Electronics: Manufacturing of printed circuit boards (PCB), computer and electronic components. Semiconductor plant Waste treatment The cleanroom Processing equipment Preparation of acids and chemicals Utility equipment Wafer preparation Water treatment PCW Water treatment UPW The principal layout and functions of would be the least complex, requiring capacities. Unique materials combined the fab are similar in all the industries.