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MOS Theory Fabrication Layout MOS Transistor Theory • So far, we have viewed a MOS transistor as an ideal switch (digital operation) – Reality: less than ideal 1 Introduction • So far, we have treated transistors as ideal switches • An ON transistor passes a finite amount of current – Depends on terminal voltages – Derive current-voltage (I-V) relationships • Transistor gate, source, drain all have capacitance – I = C (V/t) -> t = (C/I) V – Capacitance and current determine speed 2 1 MOS Capacitor • Gate and body form MOS capacitor • Operating modes – Accumulation – Depletion – Inversion 3 MOS Transistor Theory • Study conducting channel between source and drain • Modulated by voltage applied to the gate (voltage- controlled device) • nMOS transistor: majority carriers are electrons (greater mobility), p-substrate doped (positively doped) • pMOS transistor: majority carriers are holes (less mobility), n-substrate (negatively doped) 4 2 Gate Biasing Gate Source SiO2 Drain + + n Channel n • Vgs=0: no current flows from + - source to drain (insulated by two reverse biased pn E junctions p-substrate • Vgs>0: electric field created across substrate VSS (Gnd) • Electrons accumulate under gate: region changes from p-type to n-type • Conduction path between source and drain 5 nMOS Device Behavior Inversion p-substrate Polysilicon gate Oxide insulator Region (n-type) Depletion region Depletion region Vgs << Vt Vgs = Vt Vgs > Vt Accumulation Depletion mode Inversion mode mode • Enhancement-mode transistor: Conducts when gate bias Vgs > Vt • Depletion-mode transistor: Conducts when gate bias is zero 6 3 Transistor Operating Regions • Cut-off region: accumulation mode, zero current flow • Linear region: Vds <= Vgs-Vt, weak inversion layer, drain current depends on Vgs and Vds • Saturated region: Vds > Vgs-Vt, strong inversion layer, drain current independent of Vds EE 261 Krish Chakrabarty 7 Terminal Voltages • Mode of operation depends on Vg, Vd, Vs – Vgs = Vg – Vs – Vgd = Vg – Vd – Vds = Vd – Vs = Vgs - Vgd • Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage – Hence Vds 0 • nMOS body is grounded. First assume source is 0 too. • Three regions of operation – Cutoff – Linear – Saturation 8 4 nMOS Cutoff • No channel • Ids 0 9 nMOS Linear • Channel forms • Current flows from d to s – e- from s to d • Ids increases with Vds • Similar to linear resistor 10 5 nMOS Saturation • Channel pinches off • Ids independent of Vds • We say current saturates • Similar to current source 11 Threshold Voltage: Concept EE 261 Krish Chakrabarty 12 6 Current-Voltage Relations EE 261 Krish Chakrabarty 13 Current-Voltage Relations EE 261 Krish Chakrabarty 14 7 Current-Voltage Relations k n: transconductance of transistor W : width-to-length ratio L • As W increases, more carriers available to conduct current • As L increases, Vds diminishes in effect (more voltage drop). Takes longer to push carriers across the transistor, reducing current flow EE 261 Krish Chakrabarty 15 Typical Parameter Values k Vt n-type 24 microA/V2 0.8V p-type 9 microA/V2 -0.8V Why is k higher for n-type transistors? EE 261 Krish Chakrabarty 16 8 Transistor in Saturation Channel is pinched off EE 261 Krish Chakrabarty 17 nMOS I-V Summary • Shockley 1st order transistor models 3: CMOS Transistor 18 Theory 9 pMOS I-V • All dopings and voltages are inverted for pMOS – Source is the more positive terminal • Mobility μp is determined by holes – Typically 2-3x lower than that of electrons μn – 120 cm2/V•s in AMI 0.6 μm process • Thus pMOS must be wider to provide same current 19 Capacitance • Any two conductors separated by an insulator have capacitance • Gate to channel capacitor is very important – Creates channel charge necessary for operation • Source and drain have capacitance to body – Across reverse-biased diodes – Called diffusion capacitance because it is associated with source/drain diffusion 20 10 Gate Capacitance • Approximate channel as connected to source • Cgs = oxWL/tox = CoxWL = CpermicronW • Cpermicron is typically about 2 fF/μm 21 The Gate Capacitance EE 261 Krish Chakrabarty 22 11 Diffusion Capacitance • Csb, Cdb • Undesirable, called parasitic capacitance • Capacitance depends on area and perimeter – Use small diffusion nodes – Comparable to Cg for contacted diff – Cg for uncontacted – Varies with process 23 Diffusion Capacitance 24 12 Parasitic Resistances Polysilicongate Drain contact G LD VGS,eff S D W RS RD Drain RS = (LS/W)R + RC RC: contact resistance RD = (LD/W)R + RC R : sheet resistance per square of drain-source diffusion 25 Body Effect • Many MOS devices on a common substrate – Substrate voltage of all devices are normally equal • But several devices may be connected in series – Increase in source-to-substrate voltage as we proceed vertically along the chain g2 d2 s2 • Net effect: slight increase g1 d1 Vsb2 = 0 in threshold voltage Vt, V12 s1 Vsb1 = 0 Vt2>Vt1 V11 26 13 Making Chips Masks Processed Chemicals Processing wafer Chips Wafers 27 CMOS Fabrication • CMOS transistors are fabricated on silicon wafer • Lithography process similar to printing press • On each step, different materials are deposited or etched • Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process 28 14 Fabrication Steps • Features are patterned on a wafer by a photolithographic process – Photo-light lithography, n. process of printing from a plane surface on which image to be printed is ink-receptive and the blank area is ink-repellant • Cover the wafer with a light-sensitive, organic material called photoresist • Expose to light with the proper pattern (mask) • Patterns left by photoresist can be used to control where oxide is grown or materials are placed on surface of wafer 29 Basic Processing Steps • N-diffusion created by doping regions of the substrate • Poly and metal are laid over the substrate, with oxide to insulate them from substrate and each other • Wires are added in layers, alternating with oxide • Vias are cut in the oxide 30 15 Basic Fabrication Steps • Layout contains information on what patterns have to made on the wafer • Masks are created using the layout information provided by the designer • Procedure involves selective removal of the oxide – Coat the oxide with photoresist, polymerized by UV light (applied through mask) – Polymerized photoresist dissolves in acid – Photoresist itself is acid-resistant 31 Basic Processing Steps • Start with wafer at current step • Add photoresist • Pattern photoresist with mask • Step-specific etch, implant, etc. • Wash off resist 32 16 Inverter Cross-section • Typically use p-type substrate for nMOS transistors • Requires n-well for body of pMOS transistors Well and Substrate Taps • Substrate must be tied to GND and n-well to VDD • Metal to lightly-doped semiconductor forms poor connection called Shottky Diode • Use heavily doped well and substrate contacts / taps 34 17 Inverter Mask Set • Transistors and wires are defined by masks • Cross-section taken along dashed line Detailed Mask Views • Six masks – n-well – Polysilicon – n+ diffusion – p+ diffusion – Contact – Metal 18 Fabrication • Chips are built in huge factories called fabs • Contain clean rooms as large as football fields Courtesy of International Business Machines Corporation. Unauthorized use not permitted. Fabrication Steps • Start with blank wafer • Build inverter from the bottom up • First step will be to form the n-well – Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer – Strip off SiO2 19 Oxidation • Grow SiO2 on top of Si wafer – 900 – 1200 C with H2O or O2 in oxidation furnace Photoresist • Spin on photoresist – Photoresist is a light-sensitive organic polymer – Softens where exposed to light 20 Lithography • Expose photoresist through n-well mask • Strip off exposed photoresist Etch • Etch oxide with hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!! • Only attacks oxide where resist has been exposed 21 Strip Photoresist • Strip off remaining photoresist – Use mixture of acids called piranah etch • Necessary so resist doesn’t melt in next step n-well • n-well is formed with diffusion or ion implantation • Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si • Ion Implanatation – Blast wafer with beam of As ions – Ions blocked by SiO2, only enter exposed Si 22 Strip Oxide • Strip off the remaining oxide using HF • Back to bare wafer with n-well • Subsequent steps involve similar series of steps Polysilicon • Deposit very thin layer of gate oxide – < 20 Å (6-7 atomic layers) • Chemical Vapor Deposition (CVD) of silicon layer – Place wafer in furnace with Silane gas (SiH4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor 23 Polysilicon Patterning • Use same lithography process to pattern polysilicon Self-Aligned Process • Use oxide and masking to expose where n+ dopants should be diffused or implanted • N-diffusion forms nMOS source, drain, and n-well contact 24 N-diffusion • Pattern oxide and form n+ regions • Self-aligned process where gate blocks diffusion • Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing N-diffusion cont. • Historically dopants were diffused • Usually ion implantation today • But regions are still called diffusion 25 N-diffusion cont. • Strip off oxide to complete patterning step P-Diffusion • Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact 52 26 Contacts • Now we need to wire together the devices • Cover chip with thick field oxide • Etch oxide where contact cuts are needed 53 Metallization • Sputter on aluminum over whole wafer • Pattern to remove excess metal, leaving wires 54 27 Layout • Chips are specified with set of masks • Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) • Feature size f = distance between source and drain – Set by minimum width of polysilicon • Feature size improves 30% every 3 years or so • Normalize for feature size when describing design rules • Express rules in terms of = f/2 – E.g.
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