MOS Transistor Theory

•
So far, we have viewed a MOS transistor as an ideal switch (digital operation)
–
Reality: less than ideal

1

Introduction
•
So far, we have treated transistors as ideal switches
•
An ON transistor passes a finite amount of current
–
Depends on terminal voltages
–
Derive current-voltage (I-V) relationships
•
Transistor gate, source, drain all have capacitance
–
I = C (
V/
t) ->
t = (C/I)
V
–
Capacitance and current determine speed

2

1
MOS Capacitor

•
Gate and body form MOS capacitor
•
Operating modes
–
Accumulation
–
Depletion
–
Inversion

3

MOS Transistor Theory

•
Study conducting channel between source and drain
•
Modulated by voltage applied to the gate (voltage- controlled device)
•
nMOS transistor: majority carriers are electrons (greater mobility), p-substrate doped (positively doped)
•
pMOS transistor: majority carriers are holes (less mobility), n-substrate (negatively doped)

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2
Gate Biasing
Gate
Source
SiO2
Drain

+ + n
Channel
n
•
Vgs=0: no current flows from
+
-
source to drain (insulated by
two reverse biased pn
E
junctions
p-substrate
•
Vgs>0: electric field created
across substrate
VSS (Gnd)
•
Electrons accumulate under gate: region changes from p-type
to n-type
•
Conduction path between source and drain

5

nMOS Device Behavior
Inversion
p-substrate
Polysilicon gate
Oxide insulator
Region
(n-type)

Depletion region
Depletion region

Vgs << Vt
Vgs = Vt
Vgs > Vt
Accumulation
Depletion mode
Inversion mode
mode
•
Enhancement-mode transistor: Conducts when gate bias

Vgs > Vt
•
Depletion-mode transistor: Conducts when gate bias is zero

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3
Transistor Operating Regions

•
Cut-off region: accumulation mode, zero current flow

•
Linear region: Vds <= Vgs-Vt, weak inversion layer, drain current depends on Vgs and Vds

•
Saturated region: Vds > Vgs-Vt, strong inversion layer, drain current independent of Vds

EE 261
Krish Chakrabarty
7

Terminal Voltages

•
Mode of operation depends on Vg, Vd, Vs

–
Vgs = Vg – Vs

–
Vgd = Vg – Vd

–
Vds = Vd – Vs = Vgs - Vgd
•
Source and drain are symmetric diffusion terminals
–
By convention, source is terminal at lower voltage

–
Hence Vds
0
•
nMOS body is grounded. First assume source is 0 too.
•
Three regions of operation
–
Cutoff
–
Linear
–
Saturation

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4
nMOS Cutoff

•
No channel

•
Ids  0

9

nMOS Linear

•
Channel forms
•
Current flows from d to s
–
e- from s to d

•
Ids increases with Vds
•
Similar to linear resistor

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5
nMOS Saturation
•
Channel pinches off

•
Ids independent of Vds
•
We say current saturates
•
Similar to current source

11

Threshold Voltage: Concept

EE 261
Krish Chakrabarty
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Current-Voltage Relations

EE 261
Krish Chakrabarty
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Current-Voltage Relations

EE 261
Krish Chakrabarty
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7
Current-Voltage Relations

k n: transconductance of transistor
W : width-to-length ratio
L

•
As W increases, more carriers available to conduct current

•
As L increases, Vds diminishes in effect (more voltage drop). Takes longer to push carriers across the transistor, reducing current flow

EE 261
Krish Chakrabarty
15

Typical Parameter Values

k Vt
n-type 24 microA/V2 0.8V
p-type 9 microA/V2 -0.8V

Why is k higher for n-type transistors?

EE 261
Krish Chakrabarty
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8
Transistor in Saturation

Channel is pinched off

EE 261
Krish Chakrabarty
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nMOS I-V Summary

•
Shockley 1st order transistor models

3: CMOS Transistor 18
Theory

9
pMOS I-V

•
All dopings and voltages are inverted for pMOS
–
Source is the more positive terminal

•
Mobility μp is determined by holes

–
Typically 2-3x lower than that of electrons μn
–
120 cm2/V•s in AMI 0.6 μm process
•
Thus pMOS must be wider to

provide same current

19

Capacitance

•
Any two conductors separated by an insulator have capacitance
•
Gate to channel capacitor is very important
–
Creates channel charge necessary for operation
•
Source and drain have capacitance to body
–
Across reverse-biased diodes
–
Called diffusion capacitance because it is associated with source/drain diffusion

20

10
Gate Capacitance
•
Approximate channel as connected to source

•
Cgs =
oxWL/tox = CoxWL = CpermicronW

•
Cpermicron is typically about 2 fF/μm

21

The Gate Capacitance

EE 261
Krish Chakrabarty
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11
Diffusion Capacitance

•
Csb, Cdb
•
Undesirable, called parasitic capacitance
•
Capacitance depends on area and perimeter
–
Use small diffusion nodes

–
Comparable to Cg

for contacted diff

–
 Cg for uncontacted
–
Varies with process

23

Diffusion Capacitance

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12
Parasitic Resistances
P
o
ly
s
i
l
i
c

o
n
ga

te

D
r
a
in

contact G







LD

V
GS

,
ef

f
S
D
W
R
S
R
D

D
r
a
in

RS = (LS/W)R + RC
RC: contact resistance
RD = (LD/W)R + RC
R : sheet resistance per square
of drain-source diffusion

25

Body Effect

•
Many MOS devices on a common substrate
–
Substrate voltage of all devices are normally equal
•
But several devices may be connected in series
–
Increase in source-to-substrate voltage as we proceed vertically along the chain

g2
d2
s2
•
Net effect: slight increase
g1
d1
Vsb2 = 0
in threshold voltage Vt,
V12
s1
Vsb1 = 0
Vt2>Vt1
V11

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13
Making Chips

Masks

Processed
Chemicals
Processing
wafer
Chips

Wafers

27

CMOS Fabrication

•
CMOS transistors are fabricated on silicon wafer
•
Lithography process similar to printing press
•
On each step, different materials are deposited or etched
•
Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

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14
Fabrication Steps

•
Features are patterned on a wafer by a photolithographic process
–
Photo-light lithography, n. process of printing from a plane surface on which image to be printed is ink-receptive and the blank area is ink-repellant
•
Cover the wafer with a light-sensitive, organic material called photoresist
•
Expose to light with the proper pattern (mask)
•
Patterns left by photoresist can be used to control where oxide is grown or materials are placed on surface of wafer

29

Basic Processing Steps

•
N-diffusion created by doping regions of the substrate
•
Poly and metal are laid over the substrate, with oxide to insulate them from substrate and each other
•
Wires are added in layers, alternating with oxide
•
Vias are cut in the oxide

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15
Basic Fabrication Steps
•
Layout contains information on what patterns have to made on the wafer
•
Masks are created using the layout information provided by the designer
•
Procedure involves selective removal of the oxide
–
Coat the oxide with photoresist, polymerized by UV light (applied through mask)
–
Polymerized photoresist dissolves in acid
–
Photoresist itself is acid-resistant

31

Basic Processing Steps

•
Start with wafer at current step
•
Add photoresist
•
Pattern photoresist with mask
•
Step-specific etch, implant, etc.
•
Wash off resist

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16
Inverter Cross-section
•
Typically use p-type substrate for nMOS transistors
•
Requires n-well for body of pMOS transistors

Well and Substrate Taps

•
Substrate must be tied to GND and n-well to VDD
•
Metal to lightly-doped semiconductor forms poor connection called Shottky Diode
•
Use heavily doped well and substrate contacts / taps

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17
Inverter Mask Set

•
Transistors and wires are defined by masks
•
Cross-section taken along dashed line

Detailed Mask Views

•
Six masks
–
n-well
–
Polysilicon
–
n+ diffusion
–
p+ diffusion
–
Contact
–
Metal

18
Fabrication
•
Chips are built in huge factories called fabs
•
Contain clean rooms as large as football fields

Courtesy of International Business Machines Corporation. Unauthorized use not permitted.

Fabrication Steps

•
Start with blank wafer
•
Build inverter from the bottom up
•
First step will be to form the n-well

–
Cover wafer with protective layer of SiO2 (oxide)
–
Remove layer where n-well should be built
–
Implant or diffuse n dopants into exposed wafer

–
Strip off SiO2

19
Oxidation

•
Grow SiO2 on top of Si wafer

–
900 – 1200 C with H2O or O2 in oxidation furnace

Photoresist

•
Spin on photoresist
–
Photoresist is a light-sensitive organic polymer
–
Softens where exposed to light

20
Lithography

•
Expose photoresist through n-well mask
•
Strip off exposed photoresist

Etch

•
Etch oxide with hydrofluoric acid (HF)
–
Seeps through skin and eats bone; nasty stuff!!!
•
Only attacks oxide where resist has been exposed

21
Strip Photoresist

•
Strip off remaining photoresist
–
Use mixture of acids called piranah etch
•
Necessary so resist doesn’t melt in next step

n-well

•
n-well is formed with diffusion or ion implantation
•
Diffusion
–
Place wafer in furnace with arsenic gas
–
Heat until As atoms diffuse into exposed Si
•
Ion Implanatation
–
Blast wafer with beam of As ions

–
Ions blocked by SiO2, only enter exposed Si

22
Strip Oxide

•
Strip off the remaining oxide using HF
•
Back to bare wafer with n-well
•
Subsequent steps involve similar series of steps

Polysilicon

•
Deposit very thin layer of gate oxide
–
< 20 Å (6-7 atomic layers)
•
Chemical Vapor Deposition (CVD) of silicon layer

–
Place wafer in furnace with Silane gas (SiH4)
–
Forms many small crystals called polysilicon
–
Heavily doped to be good conductor

23
Polysilicon Patterning

•
Use same lithography process to pattern polysilicon

Self-Aligned Process

•
Use oxide and masking to expose where n+ dopants should be diffused or implanted
•
N-diffusion forms nMOS source, drain, and n-well contact

24
N-diffusion
•
Pattern oxide and form n+ regions
•
Self-aligned process where gate blocks diffusion
•
Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

N-diffusion cont.

•
Historically dopants were diffused
•
Usually ion implantation today
•
But regions are still called diffusion

25
N-diffusion cont.

•
Strip off oxide to complete patterning step

P-Diffusion

•
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

52

26
Contacts

•
Now we need to wire together the devices
•
Cover chip with thick field oxide
•
Etch oxide where contact cuts are needed

53

Metallization
•
Sputter on aluminum over whole wafer
•
Pattern to remove excess metal, leaving wires

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27
Layout
•
Chips are specified with set of masks
•
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
•
Feature size f = distance between source and drain
–
Set by minimum width of polysilicon
•
Feature size improves 30% every 3 years or so
•
Normalize for feature size when describing design rules
•
Express rules in terms of
= f/2
–
E.g.
= 0.3 μm in 0.6 μm process

55

Design Rules
•
Design rules govern the layout of individual components: transistors, wires, contacts, vias
–
How small can the gates be, and how small can the wires be made?
•
Conflicting Demands:
–
component packing: more functionality, higher speed
–
Chip yield: smaller sizes can reduce yield (fraction of good chips)
•
Conservative vs aggressive design rules

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Geometric Design Rules

•
Resolution
–
Width and spacing of lines on one layer
•
Alignment
–
make sure interacting layers overlap (or don’t)
–
Contact surround
–
Poly overlap of diffusion
–
Well surround of diffusion

57

SCMOS Design Rules
•
Scalable CMOS design rules
•
Feature size

= half the drawn gate length
(poly width)
•
Mentor Graphics IC tool has built-in design
rule checker (DRC)
Example design rules:

Layer Minimum Width Separation
Metal 1 3

3


Metal 2 3

4


Poly 2

poly-poly: 2


poly-diff: 1

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Foundry Interface

Layout
(mask set)

Designer
Foundry

Design Rules
Process Parameters

59

Simplified Design Rules

•
Conservative rules to get you started

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30
Tub Ties and Latchup

•
Substrate must be connected to power supply

•
p-tub for nMOS to VSS (Gnd)
•
n-tub for pMOS to VDD
•
Connections made by special vias called tub ties
•
Conservative design rule: place tub ties for every one or two transistors
•
Why not place one tie in each tub that has 50 transistors?

61

Latchup
•
Too few ties: high resistance between tub and power supply, leads to parasitic bipolar transistors inhibiting normal chip operation
•
Parasitic silicon-controlled rectifier (SCR)
•
When both bipolar transistors are off, SCR conducts no current

•
SCR turns on: high current short-circuit between VDD and Gnd.

62

31
Stick Diagrams
•
Designing complete layout in terms of rectangles can be overwhelming
•
Stick diagram: abstraction between transistor schematic and layout
–
Cartoon of a chip layout
•
Replace rectangles by lines

VDD (blue)
p-type diffusion
transistor
VDD (yellow)

a Metal 1 (blue)
a a Poly (red)
n-type
diffusion
Gnd (green)
VSS (Gnd)

63

Stick Diagram

VDD Metal 1
VDD

a b p-diffusion
a z b a

b Poly
Gnd n-diffusion

Metal 1
Gnd

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32
Cell Minimization
•
Chip area (cell size) must be minimized carefully
Impact of die size/chip area on cost (unpackaged dies)
Nominal
1% increase
15% increase
Pentium die
in die size
in die size
Wafer cost $1,460 $1,460 $1,460
Die size 160.2 mm2 161.8 mm2 184.2 mm2
Die cost $84.06 $85.33 $102.55
Chips
fabricated
per week 498.1 K 482.9 K 337.5 K
Added
annual cost $63.5 M $961 M

65

Minimize number of diffusion strips
•
How do we order the gate inputs (poly)?
•
More diffusion strips
more spacing, more area
V
DD Try a, b, c, d, e:

VDD
e
x
x
x
x
x
a
d

b
c
F
F

a
x
x
x
x
x
x
x
b
a
b
c
d
e
d
e
c
Gnd
Two n-diff gaps, zero p-diff gaps

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33
e
b
VDD
a
a

e
d
c
a
d
e
d
b
c

b
c
pMOS graph
nMOS graph

a
b
d
e
c

Gnd

67

•
Euler path: Visit every edge exactly
once
•
Find all Euler paths for nMOS and
pMOS graphs
•
Find p- and n-path that have identical
labeling

•
For example: d, e, a, b, c
•
If no such path exists, then break diffusion into strips

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34
V
e
b
DD pMOS graph
a
a

e
d
a
d
e
c
d
b
c

b
c
nMOS graph

VDD
x
x
x
a
F
x
x
b
c
e
F
d
Gnd

Ordering: d, e, a, b, c:
x
x
x
x
x
Zero n-diff gaps, zero p-diff gaps
Gnd
d
e
a
b
c

69

Some Layout Hints
•
Plan the global structure •
Wiring on orthogonal (“big picture”), then metal layers
design cells
–
Assign preferred –
Floorplan
directions to M1 and –
Wiring strategy
M2
–
Power and ground –
Use diffusion only for distribution
devices, not for interconnect
–
Systematic placement
–
Use poly only for very –
Keep all pMOS/nMOS local interconnect
together
–
Place transistors in rows: share source/drain diffusion

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Inverter Layout

•
Transistor dimensions specified as Width / Length
–
Minimum size is 4
/ 2
, sometimes called 1 unit
–
In f = 0.6 μm process, this is 1.2 μm wide, 0.6 μm long

71

Summary

•
MOS transistors are stacks of gate, oxide, silicon
•
Act as electrically controlled switches
•
Build logic gates out of switches
•
Draw masks to specify layout of transistors

•
Now you know everything necessary to start designing schematics and layout for a simple chip!

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