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Process Steps for High Quality Si-Based Epitaxial Growth at Low Temperature Via RPCVD

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Process Steps for High Quality Si-Based Epitaxial Growth at Low Temperature Via RPCVD materials Article Process Steps for High Quality Si-Based Epitaxial Growth at Low Temperature via RPCVD Jongwan Jung 1,2,*,† , Baegmo Son 3,†, Byungmin Kam 3,†, Yong Sang Joh 3, Woonyoung Jeong 2, Seongjae Cho 4 , Won-Jun Lee 2 and Sangjoon Park 3 1 Hybrid Materials Center (HMC), Sejong University, Seoul 05006, Korea 2 Department of Nano and Advanced Materials Science, Sejong University, Seoul 05006, Korea; [email protected] (W.J.); [email protected] (W.-J.L.) 3 Wonik IPS, Pyeongtaek 17709, Korea; [email protected] (B.S.); [email protected] (B.K.); [email protected] (Y.S.J.); [email protected] (S.P.) 4 Department of Electronics Engineering, The Graduate School of IT Convergence Engineering, Gachon University, Seongnam 13120, Korea; [email protected] * Correspondence: [email protected] † These authors contributed equally. Abstract: The key process steps for growing high-quality Si-based epitaxial films via reduced pressure chemical vapor deposition (RPCVD) are investigated herein. The quality of the epitaxial films is largely affected by the following steps in the epitaxy process: ex-situ cleaning, in-situ bake, and loading conditions such as the temperature and gaseous environment. With respect to ex-situ cleaning, dry cleaning is found to be more effective than wet cleaning in 1:200 dilute hydrofluoric acid (DHF), while wet cleaning in 1:30 DHF is the least effective. However, the best results of all are obtained via a combination of wet and dry cleaning. With respect to in-situ hydrogen bake in the presence of H2 gas, the level of impurities is gradually decreased as the temperature increases from Citation: Jung, J.; Son, B.; Kam, B.; 700 ◦C to a maximum of 850 ◦C, at which no peaks of O and F are observed. Further, the addition Joh, Y.S.; Jeong, W.; Cho, S.; Lee, W.-J.; of a hydrogen chloride (HCl) bake step after the H2 bake results in effective in-situ bake even at Park, S. Process Steps for High temperatures as low as 700 ◦C. In addition, the effects of temperature and environment (vacuum or Quality Si-Based Epitaxial Growth at gas) at the time of loading the wafers into the process chamber are compared. Better quality epitaxial Low Temperature via RPCVD. films are obtained when the samples are loaded into the process chamber at low temperature in a Materials 2021, 14, 3733. https:// doi.org/10.3390/ma14133733 gaseous environment. These results indicate that the epitaxial conditions must be carefully tuned and controlled in order to achieve high-quality epitaxial growth. Academic Editor: Matthieu Petit Keywords: epitaxy; RPCVD; low temperature; Si; SiGe; impurity; in-situ cleaning; pre-cleaning; Received: 5 June 2021 surface treatment Accepted: 30 June 2021 Published: 3 July 2021 Publisher’s Note: MDPI stays neutral 1. Introduction with regard to jurisdictional claims in The epitaxial growth of silicon, silicon-germanium (SiGe) layers on a silicon substrate published maps and institutional affil- is a well-established technology for semiconductor fabrication, and has long been applied iations. to the production of high-performance image sensors [1] and power devices [2]. Moreover, the addition of phosphorus or boron precursors along with the Si precursor enables the growth of Si:P or Si:B alloys with much higher P or B doping concentrations than can be obtained via ion implantation [3–6]. In addition to Si, Group 4 elements such as Ge, C, Copyright: © 2021 by the authors. etc. can be applied to stress engineering [7–10]. This enables a source/drain (S/D) strain Licensee MDPI, Basel, Switzerland. engineering in which SiC epitaxy is used to increase electron mobility by providing tensile This article is an open access article strain, while SiGe epitaxy is used to increase hole mobility by providing compressive distributed under the terms and strain. Further, relaxed epitaxy technology can be used to grow Ge as a relaxed-Ge channel conditions of the Creative Commons with very high hole mobility [11]. Currently, epitaxy technology is a key process for the Attribution (CC BY) license (https:// continued scaling and increased functionality of integrated circuits. With respect to scaling, creativecommons.org/licenses/by/ the currently used FIN field-effect transistor (FINFET) technology has been extended down 4.0/). Materials 2021, 14, 3733. https://doi.org/10.3390/ma14133733 https://www.mdpi.com/journal/materials Materials 2021, 14, x FOR PEER REVIEW 2 of 11 scaling, the currently used FIN field-effect transistor (FINFET) technology has been ex- tended down to 5 nm, but the most suitable structure for the 3 to 2 nm scale downwards is probably the gate-all-around FET (GAAFET) [12,13]. A key process for implementing the GAAFET is the stacked epitaxial growth of Si and SiGe to construct multi-layers of nanosheets. The chemical vapor deposition (CVD) processes used for epitaxial growth includes ultra-high vacuum CVD (UHVCVD) [14], reduced pressure CVD (RPCVD) [15,16], and atmospheric-pressure CVD (APCVD) [17]. Among these, RPCVD has the advantage of combining a high throughput with high quality epitaxy. While several papers have re- ported the growth of crystalline Si or SiGe [18–24], there are a few reports on key process steps in low-temperature epitaxial growth via RPCVD. In addition, many reports using dichlorosilane (DCS) as Si source have been performed at high temperature above 700 °C Materials 2021, 14, 3733 [18–23] due to poor chlorine (Cl) desorption of DCS at low temperature. Even2 of 11 though high order silane precursors can be used at lower temperature [24–27], a cyclic deposition and etch routine are needed for selective epitaxial growth (SEG), making DCS the most com- monto 5 nm, Si butprecursor the most for suitable SEG structureof Si and for SiGe. the 3 to Epitaxial 2 nm scale growth downwards is performed is probably via the several se- quentialgate-all-around steps. FET The (GAAFET) first step [12 is,13 pre]. A-treatment key process of for the implementing wafers, which the GAAFET usually is involves an initialthe stacked ex-situ epitaxial wet cleaning growth of step, Si and after SiGe which to construct the wafers multi-layers are loaded of nanosheets. into a load lock chamber of theThe RPCVD chemical system. vapor depositionFrom there, (CVD) the wafers processes are used moved for epitaxial via a transfer growth chamber includes into either ultra-high vacuum CVD (UHVCVD) [14], reduced pressure CVD (RPCVD) [15,16], and anatmospheric-pressure additional in-situ CVD cleaning (APCVD) chamber [17]. Among or directly these, RPCVD into the has proc the advantageess chamber, of com- where a final prebining-cleaning a high throughput step such withas H high2 bake quality takes epitaxy. place. While Finally, several the papersepitaxial have growth reported occurs in the processthe growth chamber of crystalline (Figure Si or 1). SiGe Each [18– 24of], these there areprocess a few reportssteps onneed key to process be well steps tuned in to grow highlow-temperature-quality epitaxial epitaxial films. growth In via particular, RPCVD. In the addition, most manyrepresentative reports using interface dichlorosi- impurities in ◦ Silane and (DCS) SiGe as epitaxy Si source are have oxygen been performed (O), carbon at high (C), temperatureand fluorine above (F). 700The C[presence18–23] of O at the interfacedue to poor of chlorine Si and (Cl)epitaxial desorption layer of leads DCS at to low staking temperature. faults Evenin the though Si film high [28], order while C leads silane precursors can be used at lower temperature [24–27], a cyclic deposition and etch toroutine the precipitation are needed for selectiveof silicon epitaxial carbide growth and (SEG),causes making dislocation DCS the or most staking common faults in the Si lattice.Si precursor Meanwhile, for SEGof surface Si and- SiGe.adsorbed Epitaxial F is growthunstable, is performed such that via Si– severalF bonds sequen- are easily trans- formedtial steps. into The Si first–H step–O bonds is pre-treatment during the of the extended wafers, whichqueue usually time under involves ambient an initial atmosphere, thusex-situ promoting wet cleaning re- step,oxidation after which after thethe wafers surface are cleaning loaded into [20 a,29 load]. lock chamber of the RPCVDTherefore, system. the From use there,of RPCVD the wafers equipment are moved and via processes a transfer chamberthat are free into eitherfrom impurities, an additional in-situ cleaning chamber or directly into the process chamber, where a final or at least suppress impurities as much as possible, are essential. In the present paper, pre-cleaning step such as H2 bake takes place. Finally, the epitaxial growth occurs in the severalprocess chamberkey process (Figure steps1 ). Eachare examined of these process using steps a 300 need mm to cluster be well RPCVD tuned to system grow at a tem- peraturehigh-quality as epitaxiallow as 700 films. °C Inwith particular, DCS precursor the most representative. First, for the interface application impurities of ex- insitu cleaning, wetSi and cleaning SiGe epitaxy with are dilute oxygen hydrofluoric (O), carbon (C),acid and (DHF), fluorine dry (F). cleaning, The presence and a of combination O at the of wet andinterface dry ofcleaning Si and epitaxial are compared. layer leads Then to staking the faultseffects in of the in Si-situ film [bake28], while with C H leads2 at tovarious tem- the precipitation of silicon carbide and causes dislocation or staking faults in the Si lattice. peratures, and the effects of two-step baking with H2 followed by HCl, are investigated. Meanwhile, surface-adsorbed F is unstable, such that Si–F bonds are easily transformed Finally, the effects of the temperature and environment of the process chamber at the time into Si–H–O bonds during the extended queue time under ambient atmosphere, thus ofpromoting loading re-oxidation the wafers after are theexamined.
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