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Process Development for Fabrication of Silicon Semiconductor Devices in a Low Gravity, High Vacuum, Space Environment

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Process Development for Fabrication of Silicon Semiconductor Devices in a Low Gravity, High Vacuum, Space Environment by Nicholas Pfeiffer B.A.Sc. University of British Columbia, 1988 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE IN THE SCHOOL OF ENGINEERING SCIENCE O Nicholas Pfeiffer 2000 SIMON FRASER UNIVERSITY December 2000 All rights reserved. This work may not be reproduced in whole or in part, by photocopy or other means, without permission of the author. Approval I Name: Nicholas Pfeiffer Degree: Master of Applied Scien Title of thesis: Process Development for Fabrication of Silicon Semiconductor Devices in a Low Gravity, High Vacuum, Space Environment Examining Committee: Dr. Shahram Payandeh, Chairperson Dr. Glenn Chapman, sen& Supervisor Dr. John Jones, supemsor 1 Dr. Ash Parameswaran, Examiner Date Approved: PARTIAL COPYRIGHT LICENSE I hereby grant to Simon Fraser University the right to lend my thesis, project or extended essay (the title of which is shown below) to users of the Simon Fraser University Library, and to make partial or single copies only for such users or in response to a request from the library of any other university, or other educational institution, on its own behalf or for one of its users. I further agree that permission for multiple copying of this work for scholarly purposes may be granted by me or the Dean of Graduate Studies. It is understood that copying or publication of this work for financial gain shall not be allowed without my written permission. Title of Thesis/Project/Extended Essay 66ProcesssDevelopment for Fabrication Of Silicon Semiconductor Devices In A Low Gravity, High Vaccum, Space Environment" Author: (signature) Nicholas Pfeiffer (name) December, 2000 (date) Abstract Semiconductor microchips are high value per mass products whose fabrication requires many of the resources available in low-Earth orbit. It is hypothesized that orbital fabrication of silicon microchip devices may be more economically attractive than traditional Earth-based fabrication based upon the inherent advantages of the space environment: vacuum, cleanliness, and microgravity. This thesis examines the feasibility of fabricating semiconductor devices in near-Earth orbit through the use of process and economic models. The semiconductor fabrication processes are represented in a detailed, step-by-step, numerical model which uses mass flow, thermodynamics and other operational calculations to create models of important process operational parameters. Wherever possible, these calculations are verified either with measurements or published literature data on existing systems. Advantages of this approach are the ability to easily add new processes and to determine energy, consumable, time, and equipment requirements for each process step. As a confirmation of accuracy, the process flow for a standard 12 level CMOS device is modeled and the generated results are comparable to published literature values. Handling of 37 gram, 200 rnrn diameter by 0.5 mrn thick silicon wafers cannot be accomplished in a high vacuum environment with the vacuum suction method used on Earth. A system for the transport and fixturing of wafers in the orbital environment, in which non-contact forces are exerted on the wafer in six degrees of freedom through magnetic levitation, is modeled in this thesis. It is found that by developing new, dry processes that are vacuum compatible, fabricating semiconductor devices in orbit is both technically and economically feasible. The outcome is a synergistic, orbital-based methodology for micro- I fabrication capable of building and delivering commercially marketable microfabricated structures. The base case modeled, production of 5,000 ASIC wafers per month, indicates that orbital fabrication is 103% more expensive than existing commercial facilities. However, optimization of process parameters and consumable requirements is shown to decrease the cost of orbital fabrication dramatically. Modeling indicates that the cost of orbital fabrication can be decreased to 58% that of an advanced, fbture Earth-based facility when trends of increasing process equipment costs and decreasing orbital transport costs are considered. Acknowledgements The author would like to thank Dr. Glenn Chapman of Simon Fraser University for his encouragement and support during this project and Jeff Johnson of Boeing Advanced Space & Communications for the reviews by him and his associates of many of the concepts developed in this project. This work was supported in part by the Natural Sciences and Engineering Research Council of Canada and Simon Fraser University. Table of Contents .. Approval ................................................................................................. 11 ... Abstract ................................................................................................. nl Acknowledgements.. ............................................................................... .v Table of Contents .................................................................................... vi List of Figures.. ..................................................................................... .xv List of Tables ....................................................................................... .xxi List of Symbols................................................................................... xxvi Foreword .......................................................................................... xxxvi Chapter 1 - Introduction ..........................................................................1 1.1 General .....................................................................................................1 1.2 Background.. ..............................................................................................1 1.3 Thesis Scope ..............................................................................................6 1.4 Thesis Outline ............................................................................................6 Chapter 2 - Semiconductor Processing .................................................... 9 2.1 Introduction ................................................................................................ 9 2.2 Background............................................................................................... .9 2.3 Processes.................................................................................................. 11 2.3.1 Material Deposition.. ............................................................................ 12 2.3.2 Patterning ............................................................................................. 15 2.3.3 Material Removal ................................................................................. 17 vii 1 Doping ................................................................................................. 19 Thermal Processes ................................................................................ 20 Wafer Transport ...................................................................................21 Cleaning ...............................................................................................22 Testing/Inspection ................................................................................ 24 Typical Process Flow Description ........................................................ 24 2.4 Processing Methodologies ........................................................................ 25 2.4.2 Single Wafer Processing ....................................................................... 26 2.4.3 Cluster Tools ........................................................................................ 27 . 2.4.4 Mini Environments............................................................................... 27 2.5 Devices .................................................................................................... 28 2.5.1 MPU .................................................................................................... 29 2.5.2 DRAM ................................................................................................. 29 2.5.3 ASIC .................................................................................................... 29 2.5.4 Wafer Size ............................................................................................30 2.6 Facilities and Equipment ..........................................................................31 2.7 Conclusions .............................................................................................. 33 Chapter 3 - Space-Based Processing ...................................................... 34 3.1 Introduction .............................................................................................. 34 3.2 Background .............................................................................................. 34 3.3 Advantages of Orbital Manufacturing....................................................... 35 3.3.1 Free Vacuum ........................................................................................36 3.3.2 Clean Environment............................................................................... 37 ... Vlll t 3.3.3 Atomic Oxygen .................................................................................... 38 3.3.4 Microgravity .......................................................................................
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