EE/MSEN/MECH 6322 Semiconductor Processing Technology Fall 2009 Walter Hu

Lecture 1: Overview <1> Course Overview • Goals of the class – Understand full process flow of IC fabrication – Design a device fabrication process – Understand basic device physics and materials – Understand and analyze concepts in lithography and photomask technology – Understand and analyze concepts in oxidation process – Understand and analyze concepts in diffusion process – Understand and analyze concepts in implantation process – Understand and analyze concepts in film deposition methods – Understand vacuum systems and equipments for IC fab – Understand and analyze concepts in etching process – Understand and analyze concepts in back-end technology – Ability to understand key considerations for CMOS/BJT process integration

Lecture 1: Overview <2> Syllabus

Lecture 1: Overview <3> Why Learn IC Fab?

Most important technology In the last 40 years? Integrated Circuits Most important technology In the coming decade? Nano; Bio Internet IEEE Spectrum 2004 November Wireless

Integrated circuits were an essential breakthrough in electronics -- allowing a large amount of circuitry to be mass-produced in reusable components with high levels of functionality.

Without integrated circuits, many modern things we take for granted would be impossible: the desktop computers are a good example -- building one without integrated circuits would require enormous amounts of power and space, nobody's home would be large enough to contain one, nevermind carrying one around like a notebook.

Lecture 1: Overview <4> Before IC is invented

ENIAC or Electronic Numerical Integrator And Computer, 1946

…Besides its speed, the most remarkable thing about ENIAC was its size and complexity. ENIAC contained 17,468 vacuum tubes, 7,200 crystal diodes, 1,500 relays, 70,000 resistors, 10,000 capacitors and around 5 million hand-soldered joints. It weighed 30 short tons (27 t), was roughly 8.5 feet by 3 feet by 80 feet (2.6 m by 0.9 m by 26 m), took up 680 square feet (63 m²), and consumed 150 kW of power. …

Lecture 1: Overview <5> First Transistor

1st commercially successful TR 1947 Raytheon CK722, 1953 Ge-based pnp low 1st transistor power TR AT&T Bell Lab

3 inventors (John 1st Si transistor Bardeen, Walter made by Gordon Brattain, and Teal at TI in William Shockley) share 1954 Nobel prize

Sources: http://roiconnect.com/transistor.htm Source: http://www.lucent.com/minds/transistor/ http://www.pbs.org/transistor/science/events/silicont1.html

Lecture 1: Overview <6> Integrated Circuit Inventors

Integrated Circuit (IC): a large number of individual components (transistors, resistors, capacitors, etc.) fabricated side by side on a common substrate and wired together to perform a particular circuit function.

1958, Jack Kilby, Texas Instrument In 1962, Steven Hofstein and Fredric Heiman at the RCA research laboratory in Princeton, New Jersey, invented a new family of devices called metal-oxide semiconductor field-effect transistors Andy Grove, (MOS FETs for short). Although these transistors Robert Noyce, were somewhat slower than bipolar transistors, and Gordon they were cheaper, smaller and used less power. Moore with Also of interest was the fact that modified metal- Intel 8080 layout. oxide semiconductor structures could be made to act as capacitors or resistors.

Sources: http://www.ti.com/corp/docs/kilbyctr/jackbuilt.shtml; http://www.maxmon.com/1926ad.htm; Intel

Lecture 1: Overview <7> Moore’s Law

The number of transistors per square inch on integrated circuits doubles every year, later every 1.5 year.

Source: Intel, Gordon Moore, presentation at ISSC 2003

Lecture 1: Overview <8> IC Manufacturing Cost

100 nano$ per transistor!

Source: Intel, Gordon Moore, presentation at ISSC 2003

Lecture 1: Overview <9> IC Market

Source: Intel, Gordon Moore, presentation at ISSC 2003

Lecture 1: Overview <10> IC Technology Market

MOS Memories MPU BJT ASICs Compound Misc.

CMOS TTL Digital MOS Analog BJT NMOS Analog MOS GaAs ECL BiCMOS

Lecture 1: Overview <11> Planar Fabrication Process

Lecture 1: Overview <12> Periodic Table-Semiconductors

Source: http://www.pmel.org/HandBook/PeriodicTable/periodic.htm

Lecture 1: Overview <13> Properties of Semiconductors

From Appendix III, Streetman and Banerjee Lattice a Density Bandgap Eg n p [Å] [g/cm^3] style [eV] [cm^2/V-s] [cm^2/V-s] Si Diamond 5.43 2.33 indirect 1.11 1350 480 Ge Diamond 5.65 5.32 indirect 0.67 3900 1900 GaAs Zincblende 5.65 5.31 direct 1.43 8500 400 InP Zincblende 5.87 4.79 direct 1.35 4000 100 GaN Z,W 4.5 6.1 direct 3.4 380 CdS Z,W 4.137 4.82 direct 2.42 250 15 InSb Zincblende 6.48 5.78 direct 0.18 10^5 1700

Si crystal

Lecture 1: Overview <14> Bonds and Carriers

Near absolute zero, all Si bonds are complete. Each Si atom contributes one electron to each of the four bond pairs.

Increasing temperature adds energy to the system and breaks bonds in the lattice, generating electron-hole pairs. Intrinsic conductivity: 1010 cm-3 at 23˚C

Intrinsic Si

Donor Impurities in Silicon

Acceptor Impurities in Silicon

Lecture 1: Overview <15> Intrinsic Carrier Concentration

• The density of carriers in a semiconductor as a function of temperature and material properties is:

2 3  EG  -6 ni  BT exp   cm  kT 

• EG = semiconductor bandgap energy in eV (electron volts) • k = Boltzmann’s constant, 8.62 x 10-5 eV/K • T = absolute temperature, K • B = material-dependent parameter, 1.08 x 1031 K-3 cm-6 for Si • Bandgap energy is the minimum energy needed to free an electron by breaking a covalent bond in the semiconductor crystal.

Lecture 1: Overview <16> Intrinsic Carrier Concentration

• Electron density is n (electrons/cm3) and ni for intrinsic material n = ni. • Intrinsic refers to properties of pure materials. 10 -3 • ni ≈ 10 cm for Si

Also see Fig. 1-16, p16 in textbook

Lecture 1: Overview <17> Electron-Hole Concentrations

• A vacancy is left when a covalent bond is broken. • The vacancy is called a hole. • A hole moves when the vacancy is filled by an electron from a nearby broken bond (hole current). • Hole density is represented by p.

• For intrinsic silicon, n = ni = p. • The product of electron and hole concentrations 2 is pn = ni . • The pn product above holds when a semiconductor is in thermal equilibrium (not with an external voltage applied).

Lecture 1: Overview <18> Drift Current

• Electrical resistivity  and its reciprocal, conductivity , characterize current flow in a material when an electric field is applied. • Charged particles move or drift under the influence of the applied field. • The resulting current is called drift current. • Drift current density is j = Qv (C/cm3)(cm/s) = A/cm2 j = current density, (Coulomb charge moving through a unit area) Q = charge density, (Charge in a unit volume) v = velocity of charge in an electric field.

Note that “density” may mean area or volumetric density, depending on the context.

Lecture 1: Overview <19> Mobility

• At low fields, carrier drift velocity v (cm/s) is proportional to electric field E (V/cm). The constant of proportionality is the mobility, :

• vn = - nE and vp = pE , where

• vn and vp = electron and hole velocity (cm/s), 2 • n and p = electron and hole mobility (cm /Vs)

• Hole mobility is less than electron since hole current is the result of multiple covalent bond disruptions, while electrons can move freely about the crystal.

Lecture 1: Overview <20> Velocity Saturation

At high fields, carrier velocity saturates and places upper limits on the speed of solid-state devices.

Lecture 1: Overview <21> Intrinsic Silicon Resistivity

• Given drift current and mobility, we can calculate resistivity: drift 2 jn = Qnvn = (-qn)(- nE) = + qn nE A/cm drift 2 jp = Qpvp = ( qp)( pE) = + qp pE A/cm

drift = jT jn + jp = q(n n + p p)E = E

Defines electrical conductivity: -1  = q(n n + p p) (cm)

Resistivity  is the reciprocal of conductivity:  = 1/ (cm)

Lecture 1: Overview <22> Ex1: Resistivity of Silicon

Lecture 1: Overview <23> Acceptor Impurities in Silicon

Hole is propagating through the silicon.

Lecture 1: Overview <24> Carrier Concentrations

• If n > p, the material is n-type. If p > n, the material is p-type. • The carrier with the largest concentration is the majority carrier, the smaller is the minority carrier. 3 • ND = donor impurity concentration atoms/cm 3 NA = acceptor impurity concentration atoms/cm • Charge neutrality requires q(ND + p - NA - n) = 0 2 • It can also be shown that pn = ni , even for doped semiconductors in thermal equilibrium.

Lecture 1: Overview <25> n-Type Material

2 • Substituting p = ni /n into q(ND + p - NA - n) = 2 2 0 yields n - (ND - NA)n - ni = 0. • Solving for n

(N  N ) (N  N )2  4n2 n2 n  D A D A i and p  i 2 n

• For (ND - NA) >> 2ni, n  (ND - NA)

P-type Materials:

For (NA - ND) >> 2ni, p  (NA - ND).

Lecture 1: Overview <26> Practical Doping Levels

• Majority carrier concentrations are established at manufacturing time and are independent of temperature (over practical temp. ranges). • However, minority carrier concentrations are 2 proportional to ni , a highly temperature dependent term.

• For practical doping levels, n  (ND - NA) for n-type and p  (NA - ND) for p-type material. • Typical doping ranges are 1014/cm3 to 1021/cm3.

Lecture 1: Overview <27> Mobility and Resistivity

Mobility is a function of Doping in Semiconductors

Impurities Disrupt the Periodic Lattice Structure

Lecture 1: Overview <28> Diffusion Current

• Second Mechanism to Produce Current in Semiconductors • In practical semiconductors, it is quite useful to create carrier concentration gradients by varying the dopant concentration and/or the dopant type across a region of semiconductor. • This gives rise to a diffusion current resulting from the natural tendency of carriers to move from high concentration regions to low concentration regions. • Diffusion current is analogous to a gas moving across a room to evenly distribute itself across the volume.

Lecture 1: Overview <29> Diffusion Current (cont.)

• Carriers move toward regions of lower concentration, so diffusion current densities are proportional to the negative of the carrier gradient.

diff   p   p 2 jp  ( q)Dp     qDp A/cm   x   x

diff   p   n 2 jn  ( q)Dn    qDn A/cm Diffusion currents in the   x   x   presence of a concentration gradient. Diffusion current density equations

Lecture 1: Overview <30> Total Current in Semiconductor

• Total current is the sum of drift and diffusion current:

 n j T  q nE  qD n n n  x  p j T  q pE  qD p p p  x

Lecture 1: Overview <31> Why Si in IC?

• Germanium was used as the original semiconductor material. Later, silicon became the material of choice for ICs. • Why Si? – Band gap (>> operating temperature) • Si (1.12 eV), Ge (0.66 eV) • Si can be operated up to ~ 150 °C while Ge can be operated up to ~ 100 °C. – Ease of fabrication of passivation layer

• GeO2 – Difficult to form, water soluble, dissociates at 800 °C.

• SiO2 – Easy to form, chemically stable – Cost • Si – Abundant, cheap (~ 10 times cheaper than Ge) • Si: facts – From Latin word “silex” or “silicis” that means “flint” – Si is the 2nd most abundant (25.7% by weight) on earth’s crust (1st: oxygen)

Lecture 1: Overview <32> Why Compound Semiconductors?

• Uniqueness of compound semiconductors – Band gap engineering • Heterostructure devices

• Hg1-xCdxTe : -0.25 ~ 1.6 eV

• AlxGa1-xAs : – AlAs : 2.16 eV, indirect – GaAs : 1.43 eV, direct – Larger electron and/or hole mobility • Good for high speed (high frequency) devices – Direct band gap materials • Optoelectronic devices (lasers, LED’s) • Compound semiconductor processing – Cost • Compound material growth is not cheap. – Difficulty of fabrication (example: GaAs) • Doping – Some dopants are amphoteric. (Donor in the Ga site and acceptor in the As site). • Oxidation

– Ge2O3 and As2O3 : oxidation rates are different.

Lecture 1: Overview <33> Band Gap and Fermi Level

3/2  me * kT  n  2  exp[(EF  Ec ) / kT]  2 2 

3/2  mh * kT  p  2  exp[(Ev  EF ) / kT ]  2 2 

UTD | Fall 2007|EE/MSEN 6322 Semiconductor Processing Technology -Dr. W. Hu Lecture 1: Overview <34> Ex2: Fermi level, n, p, for doped Si

P28 in textbook

UTD | Fall 2007|EE/MSEN 6322 Semiconductor Processing Technology -Dr. W. Hu Lecture 1: Overview <35> Semiconductor Devices

PN Diodes MOSFET Bipolar Junction Transistor CMOS (BJT) n-type p-type silicon silicon cathode anode pn Junction

Al Al p-type Si n-type Si

http://jas.eng.buffalo. Collector edu/education/pn/bi asedPN/index.html Base

http://jas.eng.buffalo. Isolation Emitter Isolation edu/education/mos/ mosfet/mosfet.html Lecture 1: Overview <36> CMOS Inverter

Lecture 1: Overview <37> CMOS Fab Example: Inverter • Typically use p-type substrate for nMOS transistor – Requires n-well for body of pMOS transistors – Several alternatives: SOI, twin-tub, etc.

A GND V DD SiO Y 2 n+ diffusion

p+ diffusion n+ n+ p+ p+ polysilicon n well p substrate metal1

nMOS transistor pMOS transistor

Lecture 1: Overview <38> Well and Substrate Taps

• Substrate must be tied to GND and n-well to VDD • Metal to lightly-doped semiconductor forms poor connection called Shottky Diode • Use heavily doped well and substrate contacts / taps

A GND V Y DD

p+ n+ n+ p+ p+ n+

n well p substrate

substrate tap well tap

Lecture 1: Overview <39> Inverter Mask Set

• Transistors and wires are defined by masks • Cross-section taken along dashed line

A

Y

GND VDD nMOS transistor pMOS transistor substrate tap well tap

Fabrication and Layout Lecture 1: Overview <40> Detailed Mask Views • Six masks – n-well n well – Polysilicon

Polysilicon – n+ diffusion

– p+ diffusion n+ Diffusion

– Contact p+ Diffusion – Metal Contact

Metal

Fabrication and Layout Lecture 1: Overview <41> Fabrication Steps • Start with blank wafer • Build inverter from the bottom up • First step will be to form the n-well

– Cover wafer with protective layer of SiO2 (oxide) – Remove layer where n-well should be built – Implant or diffuse n dopants into exposed wafer

– Strip off SiO2

p substrate

Fabrication and Layout Lecture 1: Overview <42> Oxidation

• Grow SiO2 on top of Si wafer

– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Fabrication and Layout Lecture 1: Overview <43> Photoresist • Spin on photoresist – Photoresist is a light-sensitive organic polymer – Softens where exposed to light

Photoresist

SiO2

p substrate

Fabrication and Layout Lecture 1: Overview <44> Lithography • Expose photoresist through n-well mask • Strip off exposed photoresist

Photoresist

SiO2

p substrate

Fabrication and Layout Lecture 1: Overview <45> Etch • Etch oxide with hydrofluoric acid (HF) – Seeps through skin and eats bone; nasty stuff!!! • Only attacks oxide where resist has been exposed

Photoresist

SiO2

p substrate

Fabrication and Layout Lecture 1: Overview <46> Strip Photoresist • Strip off remaining photoresist – Use mixture of acids called piranah etch • Necessary so resist doesn’t melt in next step

SiO2

p substrate

Fabrication and Layout Lecture 1: Overview <47> n-well

• n-well is formed with diffusion or ion implantation • Diffusion – Place wafer in furnace with arsenic gas – Heat until As atoms diffuse into exposed Si • Ion Implanatation – Blast wafer with beam of As ions

– Ions blocked by SiO2, only enter exposed Si

SiO2

n well

Fabrication and Layout Lecture 1: Overview <48> Strip Oxide • Strip off the remaining oxide using HF • Back to bare wafer with n-well • Subsequent steps involve similar series of steps

n well p substrate

Fabrication and Layout Lecture 1: Overview <49> Polysilicon • Deposit very thin layer of gate oxide – < 20 Å (6-7 atomic layers) • Chemical Vapor Deposition (CVD) of silicon layer

– Place wafer in furnace with Silane gas (SiH4) – Forms many small crystals called polysilicon – Heavily doped to be good conductor

Polysilicon Thin gate oxide

n well p substrate

Fabrication and Layout Lecture 1: Overview <50> Polysilicon Patterning • Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon Thin gate oxide

n well p substrate

Fabrication and Layout Lecture 1: Overview <51> Self-Aligned Process • Use oxide and masking to expose where n+ dopants should be diffused or implanted • N-diffusion forms nMOS source, drain, and n-well contact

n well p substrate

Fabrication and Layout Lecture 1: Overview <52> N-diffusion

• Pattern oxide and form n+ regions • Self-aligned process where gate blocks diffusion • Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

n+ Diffusion

n well p substrate

Fabrication and Layout Lecture 1: Overview <53> N-diffusion • Historically dopants were diffused • Usually ion implantation today • But regions are still called diffusion

n+ n+ n+

n well p substrate

Fabrication and Layout Lecture 1: Overview <54> N-diffusion • Strip off oxide to complete patterning step

n+ n+ n+ n well p substrate

Fabrication and Layout Lecture 1: Overview <55> P-Diffusion • Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+ n well p substrate

Fabrication and Layout Lecture 1: Overview <56> Contacts • Now we need to wire together the devices • Cover chip with thick field oxide • Etch oxide where contact cuts are needed

Contact

Thick field oxide p+ n+ n+ p+ p+ n+

n well p substrate

Fabrication and Layout Lecture 1: Overview <57> Metallization

• Sputter on aluminum over whole wafer • Pattern to remove excess metal, leaving wires

Metal

Metal Thick field oxide p+ n+ n+ p+ p+ n+

n well p substrate

Fabrication and Layout Lecture 1: Overview <58> CMOS Fabrication Process • http://jas.eng.buffalo.edu/education/f ab/invFab/index.html# • Movie: Silicon Run 1 v2. • Homework – Read Chapter 1 & 2 – Read Kilby lecture, write 100 words about what you learned from it. – 1.2, 1.4, 1.9.

Lecture 1: Overview <59>