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Assessing Device Rds(On) at Wafer Level

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Assessing Device Rds(On) at Wafer Level WATER CHARACTERIZATION AND TEST WATER CHARACTERIZATION AND TEST Power MOSFET engineers are con- The ability to sort devices based on development engineers, dramatically fronted with the conflicting demands drain-source resistance, or even the improving process yield. of providing ever-increasing efficiency capability to measure the through resis- Assessing Device Rds(on) and power ratings, while using ever- tance of the device early in the manu- The basic steps for performing and shrinking process geometries. The facturing process, is important. This is verifying the key power measurements solution has traditionally been to drive because these capabilities can enable of a field-effect power semiconduc- device RDS(ON) values to lower and lower power-device engineers using leading- tor device are essentially the same for levels. In general, lowering the on-state edge process technology to design bet- both on-wafer testing and in-package resistances of power devices improves ter, more stable fabrication processes testing. R of the device is derived at Wafer Level DS(ON) their performance. Therefore, RDS(ON) is a for their devices. Processes with these by dividing the drain-source voltage by key parameter for power-device manu- capabilities can also be controlled, the drain-source current. The maximum facturers, and can be used as a basis modeled, characterized and optimized current rating of the device for a given New measurement capability for power for KGD sorting. more effectively by fabrication-process power rating that might be assigned for a given package type can then be device engineers determined by sorting based on the key parameter of RDS(ON). YES Reducing the electrical and thermal resistance of the wafer-chuck interface enables full characterization Both voltage and current can usually of wafer-level power devices. be measured directly and accurately from the parameter analyzer’s source By Terry Burcham, Technical Support Manager, Cascade Microtech monitoring units (SMUs) for low-power, on-wafer testing. This is accomplished nown-good-die (KGD) sorting is by using the proper Kelvin connections a commonly used technique in (shown in Figure 1). However in the case Ksemiconductor processing that of high drain-source currents in a power allows IC-device engineers to bypass MOSFET the resistance of the device the packaging of defective semiconduc- under (DUT) test may be much lower tor devices while they are still on the than the resistance of the SMU test wafer, saving time and money. Due to leads, causing significant voltage drops inadequate probes and probe stations, that easily distort the voltage measure- power-device engineers have not been ments. able to take advantage of this powerful To avoid test-lead voltage drop technique for the parameter of RDS(ON) in power devices, a key characteristic, Fig 2. This graph of RDS(ON) measurements for a MOSFET using a standard errors for large currents, all param- and have had to resort to a lengthy and parametric-analyzer-SMU approach produces an inaccurate reading caused eter analyzer SMUs offer “force-and- costly packaging process prior to char- by probe-contact voltage drops being sensed by the voltage probes (compare sense” connections, enabling true acterization. with Fig. 3). Kelvin test conditions. As the drain- source current increases, it causes a However, using a recently devel- proportionally higher voltage drop, or oped probe technology, the capability “force”, in the test leads. The “sense” connection measures this voltage now exists to perform these RDS(ON) measurements directly on the wafer drop, which is then supplied to the over a broad temperature range. This SMU for calculating the actual drain- provides power-device designers with source voltage. Fig 1. All parameter analyzer SMUs offer “force-and-sense” connections, such the capability to obtain a wafer map as those shown here on an VDMOS device, enabling true Kelvin test conditions. Most engineers try to make the key of device RDS(ON) values for each die on the wafer. With this capability, they RDS(ON) measurement directly from a can determine known good die (KGD) design-cycle times and development Without KGD data, the cause of the parametric analyzer’s Kelvin-connected much earlier in the manufacturing costs for power devices. failure cannot be known. SMUs. However, even when the param- process, reducing both development eter analyzer SMUs are connected in times and manufacturing costs for the Key Power Measurements By testing on wafer, the painful pro- a true Kelvin measurement, significant device. In the engineering design and devel- cess of finding the root cause of failure errors in the derived value for RDS(ON) opment process, it is vital to verify as in a packaged device is precluded: if a have been observed. These errors are As a general rule of thumb, every many parameters of a manufactured device fails the wafer testing, it will not mostly due to the voltage accuracy or manufacturing step in the design-and- device as possible, and also to do so as be packaged. Conversely, if a packaged resolution of the SMU itself. Illustrated development process increases total early in the manufacturing process as device fails, either the packaging design in Fig. 2 is an attempt to measure RDS(ON) project cost by a factor of ten. The possible. The worst thing that can hap- or the packaging process is the most of a medium-power MOSFET device. Fig 3. R measurements for the same MOSFET measured in Fig. 2, but using elimination of unnecessary packaging pen is to get to the end of the process likely cause, because the device would DS(ON) The RDS(ON) values were derived using the superior VMU approach, improve accuracy by compensating for high-current the voltage read from the current-source enabled by on-wafer RDS(ON) measure- and discover that a package failure may have tested good prior to being pack- ments can therefore substantially reduce have rendered a device un-testable. aged. voltage drops developed across the contact resistance of the wafer probes. SMU, yielding 40 mΩ. 24 Power Systems Design Europe November 2007 www.powersystemsdesign.com 25 WATER CHARACTERIZATION AND TEST WATER CHARACTERIZATION AND TEST Fig. 3 shows the same device mea- chuck and the backside of the wafer. wafer-level probing for power devices. sorting. This level of testing is especially sured with a voltage monitoring unit This occurs because the thickness important for military/aerospace appli- (VMU) added to accurately measure the Vacuum Technology Minimizes of power-device wafers are typically cations. source voltage used in the RDS(ON) calcu- Contact Resistance reduced for improved die performance, lation, yielding 12 mΩ. If very-high-pow- As a designer or consumer of a reducing their lateral thermal conduc- With the dramatic improvement in the er devices are to be fully characterized manufacturer’s devices, it is important tivity. VacuChannel technology signifi- heatsinking properties of the VacuChan- directly from the parametric analyzer, to know that there has been a paradigm cantly reduces the thermal resistance nel chuck technology, testing on-wafer it requires a VMU to be applied to the shift in RDS(ON) measurement methodol- of the contact between the backside of over a wide temperature range is pos- source probe (or in some cases both the ogy. Until recently, there were no wafer- the wafer and chuck, providing supe- sible. Thermal conditions once restricted source and drain probes) in order to get chuck technologies that allowed an on- rior hold-down capability of the power to the testing of packaged devices can accurate measurements at high cur- wafer RDS(ON) measurement to correlate device wafer. now be created for the testing of wafer- rents. wafer-level measurements with in- level devices. package measurements. Using this technology, a true paramet- RDS(ON) Die Sorting ric measurement of a particular die for On average, the thermal resistance of In the packaging process, the die is Cascade Microtech’s VacuChannelÔ multiple gate-source voltages can be a normal chuck is 1ºC/W, and a typical bonded to the package; therefore, there technology provides the solution to the performed at the wafer level, as shown wafer chuck can exhibit a 50°C temper- is no significant resistance between on-wafer, RDS(ON) measurement chal- in Fig. 4. This figure contains data for ature rise. This has effectively prevented the package and the die. Measuring lenge. The unique chuck distributes the three different metals used for the top on-wafer thermal testing. Specifically, RDS(ON) in a packaged device is benefi- vacuum more evenly to the wafer than surface contact of the chuck. The criti- thermal runaway can render electrical cial because it accurately simulates the standard holes or ring technologies. cal RDS(ON) measurement can be made measurements useless and can even behavior of the die in the situation where The evenly-distributed vacuum, coupled for each device much earlier in the cause electrical shorts in the measure- it is going to be used. The drawback is with a highly polished gold top surface, engineering-development manufactur- ment path. the time and cost required to package ensures 10 to 100 times lower contact ing process. This eliminates the need to the die. resistances between the wafer and dice, package, test, and then finally sort VacuChannel technology provides a chuck than what is offered by standard faulty power devices that might have Fig 5. This wafer map illustrates how individual die can be binned on a wafer heat-sinking capability that is an order Wafer-level measurements are con- chuck technologies. passed conventional low-power func- according to RDS(ON) , allowing for the identification of faulty devices before of magnitude greater than that of venient and provide a time and cost tional testing.
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