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Making of a Chip” Illustrations “Making of a Chip” Illustrations 22nm 3D/Trigate Transistors – Version January 2012 Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 1 The illustrations on the following foils are low resolution images that visually support the explanations of the individual steps. For publishing purposes there are high resolution JPEG files posted to the Intel website: www.intel.com/pressroom/kits/chipmaking Optionally same resolution (uncompressed) images are available as well. Please request them from [email protected] Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 2 Sand / Ingot Melted Silicon – Monocrystalline Silicon Ingot – Sand scale: wafer level (~300mm / 12 inch) scale: wafer level (~300mm / 12 inch) Silicon is the second most abundant element in the earth's crust. Common In order to be used for computer chips, The ingot has a diameter of 300mm and sand has a high percentage of silicon. silicon must be purified so there is less weighs about 100 kg. Silicon – the starting material for than one alien atom per billion. It is pulled computer chips – is a semiconductor, from a melted state to form a solid which meaning that it can be readily turned is a single, continuous and unbroken into an excellent conductor or an crystal lattice in the shape of a cylinder, insulator of electricity, by the known as an ingot. introduction of minor amounts of impurities. Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 3 Ingot / Wafer Wafer – scale: wafer level (~300mm / 12 inch) The wafers are polished until they have flawless, Ingot Slicing – mirror-smooth surfaces. Intel buys manufacturing- scale: wafer level (~300mm / 12 inch) ready wafers from its suppliers. Wafer sizes have The ingot is cut into individual silicon discs increased over time, resulting in decreased costs per called wafers. Each wafer has a diameter of chip. when Intel began making chips, wafers were only 300mm and is about 1 mm thick. 50mm in diameter. Today they are 300mm, and the industry has a plan to advance to 450mm. Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 4 Fabrication of chips on a wafer consists of hundreds of precisely controlled steps which result in a series of patterned layers of various materials one on top of another. What follows is a sample of the most important steps in this complex process. Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 5 Photolithography Applying Photoresist – Exposure – scale: wafer level (~300mm / 12 inch) scale: wafer level (~300mm / 12 inch) Resist Development– Photolithography is the process by which The photoresist is hardened, and portions of it are scale: wafer level (~300mm / 12 inch) a specific pattern is imprinted on the exposed to ultraviolet (UV) light, making it soluble. The soluble photoresist is removed by a wafer. It starts with the application of a The exposure is done using masks that act like chemical process, leaving a photoresist liquid known as photoresist, which is stencils, so only a specific pattern of photoresist pattern determined by what was on the evenly poured onto the wafer while it becomes soluble. The mask has an image of the mask. spins. It gets its name from the fact that pattern that needs to go on the wafer; it is optically it is sensitive to certain frequencies of reduced by a lens, and the exposure tool steps and light (“photo”) and is resistant to certain repeats across the wafer to form the same image a chemicals that will be used later to large number of times. remove portions of a layer of material (“resist”). Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 6 Ion Implantation Ion Implantation– scale: wafer level (~300mm / 12 inch) Removing Photoresist– The wafer with patterned photoresist is Begin Transistor Formation– scale: wafer level (~300mm / 12 inch) bombarded with a beam of ions (positively or scale: transistor level (~50-200nm) After ion implantation, the photoresist is negatively charged atoms) which become Here we zoom into a tiny part of the removed and the resulting wafer has a embedded beneath the surface in the regions not wafer, where a single transistor will be pattern of doped regions in which covered by photoresist. This process is called formed. The green region represents transistors will be formed. doping, because impurities are introduced into doped silicon. Today’s wafers can have the silicon. This alters the conductive properties hundreds of billions of such regions of the silicon (making it conductive or insulating, which will house transistors. depending on the type of ion used) in selected locations. Here we show the creation of wells, which are regions within which transistors will be formed. Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 7 Etching Etch– scale: transistor level (~50-200nm) In order to create a fin for a tri-gate Removing Photoresist – transistor, a pattern of material called scale: transistor level (~50-200nm) a hard mask (blue) is applied using the The hard mask is chemically removed, leaving a tall, photolithography process just thin silicon fin which will contain the channel of a described. Then a chemical is applied transistor. to etch away unwanted silicon, leaving behind a fin with a layer of hard mask on top. Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 8 Temporary Gate Formation Silicon Dioxide Gate Dielectric– scale: transistor level (~50-200nm) Polysilicon Gate Electrode– Insulator– Using a photolithography step, scale: transistor level (~50-200nm) portions of the transistor are covered scale: transistor level (~50-200nm) with photoresist and a thin silicon Again using a photolithography step, a In another oxidation step, a silicon dioxide dioxide layer (red) is created by temporary layer of polycrystalline silicon layer is created over the entire wafer inserting the wafer in an oxygen-filled (yellow) is created. This becomes a (red/transparent layer) to insulate this tube-furnace. This becomes a temporary gate electrode. transistor from other elements. temporary gate dielectric. Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 9 Intel uses a “gate last” (also known as “replacement metal gate”) technique for creating transistor metal gates. This is done in order to avoid transistor stability problems which otherwise might arise as a result of some subsequent high temperature process steps. Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 10 “Gate-Last” High-k/Metal Gate Formation Removal of Sacrificial Gate– Applying High-k Dielectric – Metal Gate– scale: transistor level (~50-200nm) scale: transistor level (~50-200nm) scale: transistor level (~50-200nm) Using a masking step, the temporary Individual molecular layers are applied to the A metal gate electrode (blue) is formed (sacrificial) gate electrode and gate surface of the wafer in a process called “atomic over the wafer and, using a lithography dielectric are etched away. The actual layer deposition”. The yellow layers shown step, removed from regions other than gate will now be formed; because the here represent two of these. Using a where the gate electrode is desired. The first gate was removed, this procedure photolithography step, the high-k material is combination of this and the high-k material is known as “gate last”. etched away from the undesired areas such as (thin yellow layer) gives the transistor above the transparent silicon dioxide. much better performance and reduced leakage than would be possible with a traditional silicon dioxide/polysilicon gate. Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 11 Metal Deposition Electroplating – Ready Transistor – scale: transistor level (~50-200nm) After Electroplating – scale: transistor level (~50-200nm) The wafers are put into a copper sulphate scale: transistor level (~50-200nm) This transistor is close to being finished. solution at this stage. The copper ions are On the wafer surface the copper ions Three holes have been etched into the deposited onto the transistor thru a settle as a thin layer of copper. insulation layer (red color) above the process called electroplating. The copper transistor. These three holes will be ions travel from the positive terminal filled with copper or other material (anode) to the negative terminal (cathode) which will make up the connections to which is represented by the wafer. other transistors. Copyright © 2012, Intel Corporation. All rights reserved. Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries. 12 Metal Layers Metal Layers – scale: transistor level (six transistors combined ~500nm) Multiple metal layers are created to interconnect (think: wires) all the transistors on Polishing – the chip in a specific configuration. How these connections have to be “wired” is scale: transistor level (~50-200nm) determined by the architecture and design teams that develop the functionality of The excess material is mechanically the respective processor (e.g.
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