ECE473 Computer Organization and Architecture

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ECE473 Computer Architecture and Organization

Technology Trends

Lecturer: Prof. Yifeng Zhu

Fall, 2014

Portions of these slides are derived from: ECE473 Lec 1.1 Dave Patterson © UCB Couse Website

http://arch.eece.maine.edu/ece473

ECE473 Lec 1.2 Author of the Text Book

Communications of the ACM, Volume 49, No. 4, April 2006, Page 31

ECE473 Lec 1.3 Author of the Text Book

ECE473 Lec 1.4 Outline

• Technology Trends • Introduction to Computer Architecture

ECE473 Lec 1.5 What If Your Salary? • Parameters – $16 base – 59% growth/year – 40 years

• Initially $16  buy book • 3rd year’s $64  buy computer game • 16th year’s $27,000  buy car • 22nd year’s $430,000  buy house • 40th year’s > billion dollars  buy a lot

You have to find fundamental new ways to spend money!

ECE473 Lec 1.6 Birth of the Revolution -- The Intel 4004

First Microprocessor in 1971

• Intel 4004 • 2300 transistors • Barely a processor • Could access 300 bytes of memory

@intel Introduced November 15, 1971 108 KHz, 50 KIPs, 2300 10m transistors

ECE473 Lec 1.7 2002 – Pentium® 4 Processor

November 14, 2002

@3.06 GHz, 533 MT/s bus

1099 SPECint_base2000* 1077 SPECfp_base2000*

55 Million 130 nm process

@intel

ECE473 Lec 1.8 Source: http://www.specbench.org/cpu2000/results/ 2002 - Intel Itanium 2 Processor for Servers

• 64-bit processors Branch Unit Floating Point Unit • .18mm bulk, 6 layer Al process IA32 Pipeline Control L1I • 8 stage, fully stalled in- cache ALAT Integer Multi- Int order pipeline L1D Medi Datapath RF a • Symmetric six integer- cache unit CLK issue design HPW DTLB • IA32 execution engine

integrated mm 21.6 L2D Array and Control L3 Tag • 3 levels of cache on-die totaling 3.3MB • 221 Million transistors Bus Logic • 130W @1GHz, 1.5V • 421 mm2 die • 142 mm2 CPU core L3 Cache

19.5mm ECE473 @intelLec 1.9 2006 - Intel Core Duo Processors for Desktop

PERFORMANCE 40%

POWER 40% …relative to Intel® Pentium® D 960

When compared to the Intel® Pentium® D processor 960. Performance measured using SPECint* rate base2000. Actual performance may vary. Energy efficiency based on Thermal Design Power (TDP) measurement. See http://www.intel.com/performance for more information.

ECE473 Lec 1.10 2008-2014 - Intel Core i7 64-bit x86-64

a 5-stage pipelined processor (group project, two members)

• Successor to the Intel Core 2 family • Scales up number of threads • 32 nm CMOS process supported • Adding GPU into the processor • 4 SMT cores, each supporting 4 • Intel Core i7 uses simultaneous multi- threads appears as 16 core ECE473 threading (SMT) Lec 1.11

Intel 4th Generation Core Processor: “Haswell”

• More than 90% of processors shipping today include a GPU on die • Low energy use is a key design goal

4-core GT2 Desktop: 35 W package 2-core GT2 Ultrabook: 11.5 W package

ECE473 Lec 1.12 Integrating GPU into CPU Chip: AMD Fusion

notebook computers

ECE473 Lec 1.13 Integrating GPU into CPU Chip: AMD Fusion, 2011

ECE473 Lec 1.14 Integrating GPU into CPU Chip: AMD Trinity, May 2012

ECE473 Lec 1.15 Embedded Processors: Intel Atom

ECE473 Lec 1.16 Technology constantly on the move! • Num of transistors not limiting factor – Currently ~ 1 billion transistors/chip – Problems: » Too much Power, Heat, Latency » Not enough Parallelism • 3-dimensional chip technology? – Sandwiches of silicon – “Through-Vias” for communication • On-chip optical connections? – Power savings for large packets Nehalem • The Intel® Core™ i7 microprocessor (“Nehalem”) – 4 cores/chip – 32 nm, Hafnium hi-k dielectric – 731M Transistors – Shared L3 Cache - 8MB – L2 Cache - 1MB (256K x 4) ECE473 Lec 1.17 Amazing Underlying Technology Change

• In 1965, Gordon Moore (co- founder of Intel) sketched out his prediction of the pace of silicon technology.

• Moore's Law: The number of transistors incorporated in a chip will approximately double every 24 months.

• Decades later, Moore's Law From Intel remains true.

ECE473 Lec 1.18 Technology Trends: Moore’s Law

• Gordon Moore (Founder of Intel) observed in 1965 that the number of transistors on a chip doubles about every 24 months. • In fact, the number of transistors on a chip doubles about every 18 months.

From intel ECE473 Lec 1.19 How did we do so far ?

Moore´s Law applied to the travel industry • A flight from New York to Paris

ECE473 Lec 1.20 IBM Power4 Dual Processor on a Chip

Two cores (~30M transistors each)

Large Shared L2: Multi-ported: 3 independent L3 & Mem slices Controller: L3 tags Chip-to-Chip & on-die for MCM-to-MCM full-speed Fabric: coherency Glueless SMP checks

@IBM

ECE473 *Other names and brands may be claimed as the property of others Lec 1.21 AMD64 Dual Core Processor

• Two AMD Opteron™ CPU cores on one single die, each with 1MB L2 cache Core 0 • 90nm, ~205 million 1-MB L2 transistors* – Approximately same die size as 130nm single-core AMD Opteron processor* • 95 watt power envelope Northbridge fits into 90nm power infrastructure • Dual-core processors for client market are expected to follow 1-MB L2 Core 1

*Based on current revisions of the design ECE473 Lec 1.22 Niagara: Multithreaded SPARC Processor

ECE473 Lec 1.23 Niagara Architecture

ECE473 Lec 1.24 Cell Overview Cell Prototype Die (Pham et al, ISSCC 2005)