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Unit I

80386DX Architecture

Session 1

History of 8086

Microprocessor –

Microprocessor is a single silicon chip used for performs the operations. It act as a brain of . History of 8086 microprocessor –

A microprocessor is a sequential digital circuit which provides the flexibility to perform different tasks upon execution of corresponding instruction sequence.

The world’s first microprocessor, the 4004, was a 4-bit microprocessor.

Intel 4004

1971: Intel launches the world's first microprocessor, the 4-bit 4004, designed by .

The

The 2,000- chip is made for a Japanese , but a farsighted Intel ad calls it "a micro-programmable computer on a chip."

Year of introduction 1971

• 4-bit microprocessor

• 4 KB main memory

• 45 instructions

• PMOS

• It was first programmable device which was used in

Intel 8008

1972: Intel announces the 8-bit 8008 processor. Teenagers and Paul Allen try to develop a programming language for the chip, but it is not powerful enough. In 1972, Intel launched the 8008, the first 8-bit microprocessor. It implemented an instruction set designed by Data point corporation with programmable CRT terminals in mind, which also proved to be fairly general purpose. The device needed several additional ICs to produce a functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address (Intel was primarily a DRAM manufacturer at the time).

Year of introduction 1972

• 8-bit version of 4004

• 16 KB main memory

• 48 instructions

• PMOS technology

• Slow

Intel 8080

1974: Intel introduces the 8-bit 8080 processor, with 4,500 and 10 times the performance of its predecessor.

1975: The 8080 chip finds its first PC application in the , launching the PC revolution. Gates and Allen succeed in developing the Altair Basic language, which will later become Basic, for the 8080.

Two years later, Intel launched the 8080, employing the new 40-pin DIL packages originally developed for calculator ICs to enable a separate address bus. It had an extended instruction set that was source (not binary) compatible with the 8008 and also included some 16-bit instructions to make programming easier. The 8080 device, often described as "the first truly useful microprocessor”, was eventually replaced by the depletion-load based 8085 (1977) which sufficed with a single +5 V power supply instead of the three different operating voltages of earlier chips. Other well known 8-bit that emerged during these years were (1974), General Instrument PIC16X (1975), MOS Technology 6502 (1975), Z80 (1976), and (1978).

Year of introduction 1973

• 8-bit microprocessor

• 64 KB main memory

• z microseconds clock cycle time • 500,000 instructions/sec

• ioX faster than 8008

• NMOS technology

• Drawback was that it needed three power supplies.

• Small () were designed in mid 1970's using 8080 as CPU.

Intel 8085

• Year of introduction 1975

• 8-bit microprocessor-upgraded version of 8o8o

• 64 KB main memory

• 1.3 microseconds clock cycle time

• 246 instructions

• Intel sold l00 million copies of this 8-bit microprocessor

• uses only one +5v power supply.

Intel 8086/8088

1978: Intel introduces the 16-bit 8086 microprocessor. It will become an industry standard.

Year of introduction 1978 for 8o86 and 1979 for 8o88

• 16-bit microprocessors

• Data bus width of 8o86 is 16 bit and 8 bit for 8o88

• 1 MB main memory

• 400 nanoseconds clock cycle time

• 6 instruction cache for 8o86 and 4 byte for 8o88

• Other improvements included more registers and additional instructions

• In 1981 IBM decided to use 8o88 in its

Features of 8086 Processor –

was launched in 1978.  It was the first 16-bit microprocessor.  This microprocessor had major improvement over the execution speed of 8085.  It is available as 40-pin Dual-Inline-Package (DIP).  It is available in three versions: o 8086 (5 MHz) o 8086-2 (8 MHz) o 8086-1 (10 MHz)  It consists of 29,000 transistors.  - A data width of 2 byte is attained by the de multiplexing of AD0 to AF15 pins.

- The instruction queue is of 6 .

- From the memory the fetching of a program is performed only once there are 2 byte empty in queue.

- The BIU of 8086 is not as same as in the 8088 but the EU is similar.

Block Diagram of Intel 8086

The 8086 CPU is divided into two independent functional units:

 Bus Interface Unit (BIU)  Execution Unit (EU)

Fig. 1: Block Diagram of Intel 8086

Bus Interface Unit (BIU)

The function of BIU is to:

 Fetch the instruction or data from memory.  Write the data to memory.  Write the data to the port.  Read data from the port.

Instruction Queue

1. To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory. 2. All six bytes are then held in first in first out 6 byte register called instruction queue. 3. Then all bytes have to be given to EU one by one. 4. This pre fetching operation of BIU may be in parallel with execution operation of EU, which improves the speed execution of the instruction.

Execution Unit (EU)

The functions of execution unit are:

 To tell BIU where to fetch the instructions or data from.  To decode the instructions.  To execute the instructions. The EU contains the control circuitry to perform various internal operations. A decoder in EU decodes the instruction fetched memory to generate different internal or external control signals required to perform the operation. EU has 16-bit ALU, which can perform arithmetic and logical operations on 8-bit as well as 16-bit.

Conclusion The session is concluded with some questions

1. Explain the various evolution phases of different processor.

2. Demonstrate the architecture of 8086 processor.

Session 2

Concept of segmentation in 8086

Concept of segmentation in 8086

Two types of memory organizations are commonly used. These are linear addressing and segmented addressing.

In segmented addressing, the available memory space is divided into chunks called segments, such a memory is known as Segmented memory.

MEMORY SEGMENTATION

Paragraphs:

The Space (MAS) is divided into 65,536 (i.e., 10,000H ) paragraphs.

Each paragraph is 16 (i.e., 10H) consecutive bytes.

Thus each paragraph starts at a whose rightmost hexadecimal digit is zero:

FFFFFH 

10H bytes Paragraph FFFFH

FFFF0H 

FFFEFH

00030H

0002FH 

10H bytes Paragraph 2H

00020H 

0001FH 

10H bytes Paragraph 1H

00010H 

0000FH 

10H bytes Paragraph 0H

00000H 

Physical Memory Segments:

The address bus of the 8086/8088 is 20-bits.

Hence the microprocessor uses 20-bit memory addresses; but its registers are 16 bits.

The concept of memory segmentation is used to solve this problem of using 20-bit addresses in a 16-bit microprocessor.

The 8086/8088 partitions its memory into 65,536 physical memory segments. A physical memory segment is a block of 216 (i.e., 64K or 10,000H) consecutive bytes starting at a paragraph boundary.

The segments overlap but they all begin at different paragraph boundaries.

All segments from the one starting at F0000h to the one starting at FFFF0h wrap around and end at lower memory addresses.

Since each segment starts at a physical address whose leftmost hexadecimal digit is zero, this digit need not be stored, hence a 16-bit segment register can be used to store the remaining four digits of the 20-bit address.

Within a segment, a memory location is specified by giving an offset. This is the number of bytes from the beginning of the segment. Since a segment is 10,000H bytes, the first byte in a segment has offset 0000h and the last byte has offset FFFFh (Note: Offsets are unsigned numbers).

Thus a memory location may be specified by providing the 16-bit segment base address, and a 16-bit offset, written in the form segment:offset; this is known as a for the memory location.

For example, the logical address A4FB:4872h means offset 4872h within segment A4FBh, that is, the segment starting at physical address A4FB0h. To obtain the corresponding 20-bit physical (i.e., absolute) address, the 8086/8088 microprocessor first shifts the segment base address 4 bits to the left (this is equivalent to multiplying by 10H), and then adds the offset. Thus the physical address for A4FB:4872h is:

A4FB0h

+ 4872h

A9822h (20-bit physical address) Because segments may overlap, the segment:offset form of an address is not unique for a particular memory location as is the case for the physical address of that memory location. For example consider the following:

Example: For the memory location whose physical address is 1256Ah, give the address in segment:offset form for segments 1256h and 1240h.

Solution: Let X be the offset in segment 1256h and Y the offset in segment 1240h. We have:

(a) 1256Ah = 12560h + X  X = 000Ah hence 1256Ah = 1256:000Ah (1)

(b) 1256Ah = 12400h + Y  Y = 016Ah hence 1256Ah = 1240:016Ah (2)

(1) & (2)  1256:000AH = 1240:016AH

 

000Ah

016Ah   1256h

  1240h

Example: A memory location has physical address 80FD2h. In what segment does it have offset BFD2h ?

Solution:

physical address = segment * 10h + offset

 segment * 10h = physical address - offset

Hence:

physical address = 80FD2h - offset = BFD2h

75000h

Thus the segment is 7500h

Program (or Logical) segments

A logical segment is part of a program that is loaded into memory beginning on a paragraph boundary (thus the base address of a logical segment has a rightmost hexadecimal digit of zero).

A logical segment is contained within a particular physical segment. Since the size of a physical segment is 64K, the maximum size of a logical segment is 64K.

Logical segments may or may not overlap.

There are four types of logical segments: , , Extra segment, and Stack segment.

The Code segment contains the instructions of a program. The Data segment provides a read/write memory in which the data of a program can be stored. The Extra segment is usually used for . Some string operations use the Extra segment to handle memory addressing. The Stack segment is used for temporary storage of addresses and data. It is in this segment that the values of the IP register, the Flags register, and other registers are stored whenever an Interrupt or call occurs.

Every 8086/8088 program must contain an explicitly defined Code segment. An 8086/8088 assembly language program which generates an file with extension .EXE must have an explicitly defined Stack segment. Such a program may or may not contain the Data or the Extra segment. An 8086/8088 assembly language program which generates an executable file with extension .COM has only one explicitly defined segment: the Code segment. The Stack segment for such a program is implicit. Thus the maximum size for an 8086/8088 COM format Assembly language program is 64K.

An EXE format 8086/8088 Assembly language program may contain multiple segments of a certain type; however only four logical segments can be active at a time.

To keep track of the various logical segments, the 8086/8088 uses each of its four segment registers to hold a 16-bit portion (called a segment number) of the 20-bit starting address of a logical segment. The remaining four rightmost bits of the address are implied 0000 because a logical segment starts at a paragraph boundary. The CS, DS, SS, and ES registers contain the code, data, stack, and extra segment numbers, respectively. The segment registers provide the segment base address part of a logical memory address (i.e., segment:offset address):

CS:IP is the segment:offset address of the next instruction to be executed.

DS:offset is the segment:offset address of the byte with the given offset in the data segment.

SS:SP is the segment:offset address of the top of the stack.

SS:BP is the segment:offset address of the byte, in the stack, whose offset is in the BP register.

DS:SI is the segment offset:address of a byte in the data segment at which the source operand of a string instruction starts.

ES:DI is the segment:offset address of a byte in the extra segment at which the destination operand of a string instruction starts.

The segment registers must be loaded with the segment numbers. Just what values are loaded is dependent in part on how the and have assigned the logical segments to memory locations, and on how the segment registers have been initialized during the loading . Typically, the CS register will be loaded with the proper code segment number so that, in conjunction with the IP register, the program’s first executable instruction will be referenced. The SS and SP registers will also be properly loaded if the stack segment is explicitly defined in the program.

The other segment registers, DS and ES, must be explicitly loaded by the programmer if they are used by the program.

Types of Segmentation

Overlapping segment

• A segment starts at a particular address and its maximum size can go up to 64 Kbytes. But if another segment starts along this 64 Kbytes location of the first segment, the two segments are said to be overlapping segment.

• The area of memory from the start of the second segment to the possible end of the first segment is called as overlapped segment. 2

Non Overlapped Segment • A segment starts at a particular address and its maximum size can go up to 64 Kbytes. But if another segment starts before this 64 Kbytes location of the first segment, the two segments are said to be Non- overlapping segment.

Conclusion The session is concluded with some questions

1. Explain the need of memory segmentation?

2. What is the size of memory segment?

3. How many numbers of memory segments are present?

Upon completion Students will be able to: -

Describe the segmentation of 8086

Explain the need of memory segmentation.

Teaching Learning Material

Black board, chalk and talk, PPTs, Notes, nptel video,

Session 3

8086 Register block Diagram

Session Plan

Time (in Content Learning Faculty Typical Skill min) Aid/Methodology Approach Student /Competency Activity Developed 10 Recap of Quiz List Listens Knowledge 8086 Facilitates Participate Intrapersonal segmentation monitors Discuss 40 Explain Black board Introduces Listens Comprehension diagram of all Explain Participate Application register sets Presentation Facilitates Discuss Knowledge & Usage of Summarizes Interpersonal all registers Visual Spatia 10 Conclusion Key Words and List Identifies Knowledge and Summary Quiz Facilitates Comprehension

Register Organization in 8086

The 8086 has a powerful set of registers It includes general purpose register, segment register, pointer and and flag register.

General Purpose Registers of 8086

These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to have AX, BX, CX, and DX.

1. AX Register: AX register is also known as register that stores operands for arithmetic operation like divided, rotate. 2. BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment. 3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter. 4. DX Register: DX register is used to contain I/O port address for I/O instruction.

Segment Register

Additional registers called segment registers generate memory address when combined with other in the microprocessor. In 8086 microprocessor, memory is divided into 4 segments as follow:

Fig. 2: Memory Segments of 8086

1. Code Segment (CS): The CS register is used for addressing a memory location in the Code Segment of the memory, where the executable program is stored. 2. Data Segment (DS): The DS contains most data used by program. Data are accessed in the Data Segment by an offset address or the content of other register that holds the offset address. 3. Stack Segment (SS): SS defined the area of memory used for the stack. 4. Extra Segment (ES): ES is additional data segment that is used by some of the string to hold the destination data. Index and Pointer register

To get 20-bit physical address, one or more pointer or index registers are associated with each segment registers.

The pointer registers IP, BP and SP are associated with code, data and stack segments.

They hold the offset within the code, data and stack segments.

The Index register SI and DI are used as a general purpose registers as well as for offset storage in case of indexed , base indexed and relative based indexed addressing modes.

Flag Registers of 8086

Flag register in EU is of 16-bit and is shown in fig. 3:

Fig. 3: Flag Register of 8086

Flags Register determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. 8086 has 9 flags and they are divided into two categories:

1. Conditional Flags 2. Control Flags

Conditional Flags

Conditional flags represent result of last arithmetic or logical instruction executed. Conditional flags are as follows:

(CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic.  Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally by the processor to perform Binary to BCD conversion.  (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity Flag is reset.  (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.  Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set.  Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF indicates that the result has exceeded the capacity of machine.

Control Flags

Control flags are set or reset deliberately to control the operations of the execution unit. Control flags are as follows:

1. Trap Flag (TP): a. It is used for single step control. b. It allows user to execute one instruction of a program at a time for debugging. . When trap flag is set, program can be run in single step mode.

2. Interrupt Flag (IF):

a. It is an interrupt enable/disable flag. b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. c. It can be set by executing instruction sit and can be cleared by executing CLI instruction.

3. Direction Flag (DF):

a. It is used in string operation. b. If it is set, string bytes are accessed from higher memory address to lower memory address. c. When it is reset, the string bytes are accessed from lower memory address to higher memory address

Conclusion The session is concluded with some questions

1. Explain the usage of register sets.

Session 4

80386DX Block Diagram

Introduction of 80386DX processor

INTEL 80386

The Intel 80386 also known as or just 386, is a 32-bit microprocessor introduced in 1985. The first versions had 275,000 transistors] and were the CPU of many workstations and high-end personal computers of the time. As the original implementation of the 32-bit extension of the 80286 architecture, the 80386 instruction set, programming model, and binary encodings are still the common denominator for all 32-bit processors, which is termed the i386-architecture, x86, or IA-32, depending on context. The 32-bit 80386 can correctly execute most code intended for the earlier 16-bit processors such as 8088 and 80286 that were ubiquitous in early PCs. (Following the same tradition, modern 64-bit x86 processors are able to run most programs written for older x86 CPUs, all the way back to the original 16-bit 8086 of 1978.) Over the years, successively newer implementations of the same architecture have become several hundreds of times faster than the original 80386 (and thousands of times faster than the 8086). A 33 MHz 80386 was reportedly measured to operate at about 11.4 MIPS. The 80386 was launched in October 1985, but full-function chips were first delivered in the third quarter of 1986. Mainboards for 80386-based computer systems were cumbersome and expensive at first, but manufacturing was rationalized upon the 80386's mainstream adoption. The first personal computer to make use of the 80386 was designed and manufactured by Compaq and marked the first time a fundamental component in the IBM PC compatible de facto- standard was updated by a company other than IBM. In May 2006, Intel announced that 80386 production would stop at the end of September 2007.[9] Although it had long been obsolete as a personal computer CPU, Intel and others had continued making the chip for embedded systems. Such systems using an 80386 or one of many derivatives are common in aerospace technology and electronic musical instruments, among others. Some mobile phones also used (later fully static CMOS variants of) the 80386 processor, such as BlackBerry 950[10] and Nokia 9000 Communicator.

Fig: Architecture of 80386DX processor

The Internal Architecture of 80386 is divided into 3 sections - • • unit • Bus interface unit Central processing unit is further divided into Execution unit and Instruction unit Execution unit has 8 General purpose and 8 Special purpose registers which are either used for handling data or calculating offset addresses.

80386 (32-Bit) Processor It Supports following Features-  Multitasking.  Pipelining.  Segmentation.  Paging.

80386 operates in various modes as follows: 1. . 2. . 3. Virtual mode. The Instruction unit decodes the bytes received from the 16-byte instruction code queue and arranges them in a 3- instruction decoded instruction queue.

After decoding them pass it to the control section for deriving the necessary control signals. The barrel shifter increases the speed of all shift and rotate operations.

The multiply / divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time.

Even 32- bit multiplications can be executed within one microsecond by the multiply / divide logic.

The consists of a Segmentation unit and a Paging unit.

Segmentation unit allows the use of two address components, viz. segment and offset for relocability and sharing of code and data.

Segmentation unit allows segments of size 4Gbytes at max.

The Paging unit organizes the physical memory in terms of pages of 4kbytes size each.

Paging unit works under the control of the segmentation unit, i.e. each segment is further divided into pages. The is also organizes in terms of segments and pages by the memory management unit.

The Segmentation unit provides a 4 level protection mechanism for protecting and isolating the system code and data from those of the application program.

Paging unit converts linear addresses into physical addresses.

The control and attribute PLA checks the privileges at the level. Each of the pages maintains the paging information of the task. The limit and attribute PLA checks segment limits and attributes at segment level to avoid invalid accesses to code and data in the memory segments.

The Bus control unit has a prioritizer to resolve the priority of the various bus requests.

This controls the access of the bus. The address driver drives the bus enable and address signal A0 – A31. The pipeline and dynamic bus sizing unit handle the related control signals.

The data buffers interface the internal data bus with the system bus.

Conclusion The session is concluded with some questions

1. Draw the block diagram of 80386DX processor.

2. Explain the functionality of all blocks of 80386DX processor.

3. Compare the block diagram of 80386DX with 8086 processor

Session 5

80386DX Pin Diagram

Session Plan

Pin diagram of 80386 processor

These signals are separated in four major groups.

1. Memory/ IO interface

2. Interrupt interface

3. DMA interface

4. Co- processor interface

Data bus(D31-D0):-It consists of 32 pins. These lines are used to transfer 8,16,24 or 32 bit data at one time.

ADDRESS BUS(A31-A0):-It generates 32 bit address. The higher 30 bits of address are sent on the A31-A2. The lower 2 bits select one of four bytes of 32 bit data bus.

W/R#: The write / read output distinguishes the write and read cycles from one another.

D/C#: This data / control output pin distinguishes between a data transfer cycle from a machine control cycle like interrupt acknowledge.

• M/IO#: This output pin differentiates between the memory and I/O cycles.

• LOCK#: The LOCK# output pin enables the CPU to prevent the other bus masters from gaining the control of the system bus.

• NA#: The next address input pin, if activated, allows address pipelining, during 80386 bus cycles.

ADS#: The address status output pin indicates that the address bus and bus cycle definition pins( W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective valid signals. The 80383 does not have any ALE signals and so this signals may be used for latching the address to external latches.

• READY#: The ready signals indicates to the CPU that the previous bus cycle has been terminated and the bus is ready for the next cycle. The signal is used to insert WAIT states in a bus cycle and is useful for interfacing of slow devices with CPU.

• VCC: These are system power supply lines.

• VSS: These return lines for the power supply.

BS16#: The bus size – 16 input pin allows the interfacing of 16 bit devices with the 32 bit wide 80386 data bus. Successive 16 bit bus cycles may be executed to read a 32 bit data from a peripheral.

• HOLD: The bus hold input pin enables the other bus masters to gain control of the system bus if it is asserted.

• HLDA: The bus hold acknowledge output indicates that a valid bus hold request has been received and the bus has been relinquished by the CPU.

• BUSY#: The busy input signal indicates to the CPU that the coprocessor is busy with the allocated task.

ERROR#: The error input pin indicates to the CPU that the coprocessor has encountered an error while executing its instruction.

• PEREQ: The processor extension request output signal indicates to the CPU to fetch a data word for the coprocessor.

• INTR: This interrupt pin is a maskable interrupt, that can be masked using the IF of the flag register.

• NMI: A valid request signal at the non-maskable interrupt request input pin internally generates a non- maskable interrupt of type2. RESET: A high at this input pin suspends the current operation and restart the execution from the starting location.

• N / C : No connection pins are expected to be left open while connecting the 80386 in the circuit.

Conclusion The session is concluded with some questions 1. Draw the pin diagram of 80386DX processor.

2. Compare the Pin diagram of 80386DX with 8086 processor.

Session 6

Register sets of 80836

Registers The 80386 contains a total of sixteen registers that are of interest to the applications programmer. As Figure 2-5 shows, these registers may be grouped into these categories:

1. General registers. These eight 32-bit general-purpose registers are used primarily to contain operands for arithmetic and logical operations. 2. Segment registers. These special-purpose registers permit systems software designers to choose either a flat or segmented model of memory organization. These six registers determine, at any given time, which segments of memory are currently addressable. 3. Status and instruction registers. These special-purpose registers are used to record and alter certain aspects of the 80386 processor state.

General Registers

The general registers of the 80386 are the 32-bit registers EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. These registers are used interchangeably to contain the operands of logical and arithmetic operations. They may also be used interchangeably for operands of address computations (except that ESP cannot be used as an index operand).

As Figure 2-5 shows, the low-order word of each of these eight registers has a separate name and can be treated as a unit. This feature is useful for handling 16-bit data items and for compatibility with the 8086 and 80286 processors. The word registers are named AX, BX, CX, DX, BP, SP, SI, and DI. fig. also illustrates that each byte of the 16-bit registers AX, BX, CX, and DX has a separate name and can be treated as a unit. This feature is useful for handling characters and other 8-bit data items. The byte registers are named AH, BH, CH, and DH (high bytes); and AL, BL, CL, and DL (low bytes).

All of the general-purpose registers are available for addressing calculations and for the results of most arithmetic and logical calculations; however, a few functions are dedicated to certain registers. By implicitly choosing registers for these functions, the 80386 architecture can encode instructions more compactly. The instructions that use specific registers include: double- precision multiply and divide, I/O, string instructions, translate, loop, variable shift and rotate, and stack operations.

Segment Registers

The segment registers of the 80386 give systems software designers the flexibility to choose among various models of memory organization. Implementation of memory models is the subject of Part II -- Systems Programming. Designers may choose a model in which applications programs do not need to modify segment registers, in which case applications programmers may skip this section.

Complete programs generally consist of many different modules, each consisting of instructions and data. However, at any given time during program execution, only a small subset of a program's modules are actually in use. The 80386 architecture takes advantage of this by providing mechanisms to support direct access to the instructions and data of the current module's environment, with access to additional segments on demand.

At any given instant, six segments of memory may be immediately accessible to an executing 80386 program. The segment registers CS, DS, SS, ES, FS, and GS are used to identify these six current segments. Each of these registers specifies a particular kind of segment, as characterized by the associated mnemonics ("code," "data," or "stack") shown in Figure 2-6 . Each register uniquely determines one particular segment, from among the segments that make up the program, that is to be immediately accessible at highest speed.

The segment containing the currently executing sequence of instructions is known as the current code segment; it is specified by means of the CS register. The 80386 fetches all instructions from this code segment, using as an offset the contents of the instruction pointer. CS is changed implicitly as the result of intersegment control-transfer instructions (for example, CALL and JMP), interrupts, and exceptions.

Subroutine calls, parameters, and procedure activation records usually require that a region of memory be allocated for a stack. All stack operations use the SS register to locate the stack. Unlike CS, the SS register can be loaded explicitly, thereby permitting programmers to define stacks dynamically.

The DS, ES, FS, and GS registers allow the specification of four data segments, each addressable by the currently executing program. Accessibility to four separate data areas helps programs efficiently access different types of data structures; for example, one data segment register can point to the data structures of the current module, another to the exported data of a higher-level module, another to a dynamically created data structure, and another to data shared with another task. An operand within a data segment is addressed by specifying its offset either directly in an instruction or indirectly via general registers.

Depending on the structure of data (e.g., the way data is parceled into one or more segments), a program may require access to more than four data segments. To access additional segments, the DS, ES, FS, and GS registers can be changed under program control during the course of a program's execution. This simply requires that the program execute an instruction to load the appropriate segment register prior to executing instructions that access the data.

The processor associates a base address with each segment selected by a segment register. To address an element within a segment, a 32-bit offset is added to the segment's base address. Once a segment is selected (by loading the segment selector into a segment register), a data manipulation instruction only needs to specify the offset. Simple rules define which segment register is used to form an address when only an offset is specified.

Stack Implementation

Stack operations are facilitated by three registers:

1. The stack segment (SS) register. Stacks are implemented in memory. A system may have a number of stacks that is limited only by the maximum number of segments. A stack may be up to 4 gigabytes long, the maximum length of a segment. One stack is directly addressable at a -- one located by SS. This is the current stack, often referred to simply as "the" stack. SS is used automatically by the processor for all stack operations. 2. The stack pointer (ESP) register. ESP points to the top of the push-down stack (TOS). It is referenced implicitly by PUSH and POP operations, subroutine calls and returns, and interrupt operations. When an item is pushed onto the stack (see Figure 2-7 ), the processor decrements ESP, then writes the item at the new TOS. When an item is popped off the stack, the processor copies it from TOS, then increments ESP. In other words, the stack grows down in memory toward lesser addresses. 3. The stack-frame base pointer (EBP) register. The EBP is the best choice of register for accessing data structures, variables and dynamically allocated work space within the stack. EBP is often used to access elements on the stack relative to a fixed point on the stack rather than relative to the current TOS. It typically identifies the base address of the current stack frame established for the current procedure. When EBP is used as the base register in an offset calculation, the offset is calculated automatically in the current stack segment (i.e., the segment currently selected by SS). Because SS does not have to be explicitly specified, instruction encoding in such cases is more efficient. EBP can also be used to index into segments addressable via other segment registers.

Flags Register

The is a 32-bit register named EFLAGS. Figure 2-8 defines the bits within this register. The flags control certain operations and indicate the status of the 80386.

The low-order 16 bits of EFLAGS is named FLAGS and can be treated as a unit. This feature is useful when executing 8086 and 80286 code, because this part of EFLAGS is identical to the FLAGS register of the 8086 and the 80286.

The flags may be considered in three groups: the status flags, the control flags, and the systems flags. Discussion of the systems flags is delayed until Part II.

Status Flags The status flags of the EFLAGS register allow the results of one instruction to influence later instructions. The arithmetic instructions use OF, SF, ZF, AF, PF, and CF. The SCAS (Scan String), CMPS (Compare String), and LOOP instructions use ZF to signal that their operations are complete. There are instructions to set, clear, and complement CF before execution of an arithmetic instruction. Refer to Appendix C for definition of each status flag.

Control Flag

The control flag DF of the EFLAGS register controls string instructions. DF (Direction Flag, bit 10) Setting DF causes string instructions to auto-decrement; that is, to process strings from high addresses to low addresses. Clearing DF causes string instructions to auto-increment, or to process strings from low addresses to high addresses.

Instruction Pointer

The instruction pointer register (EIP) contains the offset address, relative to the start of the current code segment, of the next sequential instruction to be executed. The instruction pointer is not directly visible to the programmer; it is controlled implicitly by control-transfer instructions, interrupts, and exceptions.

As Following fig. shows, the low-order 16 bits of EIP is named IP and can be used by the processor as a unit. This feature is useful when executing instructions designed for the 8086 and 80286 processors.

Conclusion The session is concluded with some questions 1. What are different general purpose registers present? 2. What is the use of Instruction Pointer?

Session 7

Flags, Physical address

space in 80386

Flags Register

The flags register is a 32-bit register named EFLAGS. Figure 2-8 defines the bits within this register. The flags control certain operations and indicate the status of the 80386.

The low-order 16 bits of EFLAGS is named FLAGS and can be treated as a unit. This feature is useful when executing 8086 and 80286 code, because this part of EFLAGS is identical to the FLAGS register of the 8086 and the 80286.

The flags may be considered in three groups: the status flags, the control flags, and the systems flags. Discussion of the systems flags is delayed until Part II.

Status Flags

The status flags of the EFLAGS register allow the results of one instruction to influence later instructions. The arithmetic instructions use OF, SF, ZF, AF, PF, and CF. The SCAS (Scan String), CMPS (Compare String), and LOOP instructions use ZF to signal that their operations are complete. There are instructions to set, clear, and complement CF before execution of an arithmetic instruction. Refer to Appendix C for definition of each status flag.

Control Flag

The control flag DF of the EFLAGS register controls string instructions. DF (Direction Flag, bit 10) Setting DF causes string instructions to auto-decrement; that is, to process strings from high addresses to low addresses. Clearing DF causes string instructions to auto-increment, or to process strings from low addresses to high addresses.

Physical address space

Memory Organization and Segmentation

The physical memory of an 80386 system is organized as a sequence of 8-bit bytes. Each byte is assigned a unique address that ranges from zero to a maximum of 2^(32) -1 (4 gigabytes).

80386 programs, however, are independent of the physical address space. This means that programs can be written without knowledge of how much physical memory is available and without knowledge of exactly where in physical memory the instructions and data are located.

The model of memory organization seen by applications programmers is determined by systems- software designers. The architecture of the 80386 gives designers the freedom to choose a model for each task. The model of memory organization can range between the following extremes:

 A "flat" address space consisting of a single array of up to 4 gigabytes.  A segmented address space consisting of a collection of up to 16,383 linear address spaces of up to 4 gigabytes each.

Both models can provide . Different tasks may employ different models of memory organization. The criteria that designers use to determine a memory organization model and the means that systems programmers use to implement that model are covered in Part -- Programming.

The "Flat" Model

In a "flat" model of memory organization, the applications programmer sees a single array of up to 2^(32) bytes (4 gigabytes). While the physical memory can contain up to 4 gigabytes, it is usually much smaller; the processor maps the 4 gigabyte flat space onto the physical address space by the address translation mechanisms described in . Applications programmers do not need to know the details of the mapping.

A pointer into this flat address space is a 32-bit ordinal number that may range from 0 to 2^(32) - 1. of separately-compiled modules in this space must be performed by systems software (e.g., linkers, locators, binders, loaders).

The Segmented Model In a segmented model of memory organization, the address space as viewed by an applications program (called the logical address space) is a much larger space of up to 2^(46) bytes (64 terabytes). The processor maps the 64 terabyte logical address space onto the physical address space (up to 4 gigabytes ) by the address translation mechanisms described in Chapter 5 . Applications programmers do not need to know the details of this mapping.

Applications programmers view the logical address space of the 80386 as a collection of up to 16,383 one-dimensional subspaces, each with a specified length. Each of these linear subspaces is called a segment. A segment is a unit of contiguous address space. Segment sizes may range from one byte up to a maximum of 2^(32) bytes (4 gigabytes).

A complete pointer in this address space consists of two parts :

1. A segment selector, which is a 16-bit field that identifies a segment. 2. An offset, which is a 32-bit ordinal that addresses to the byte level within a segment.

During execution of a program, the processor associates with a segment selector the physical address of the beginning of the segment. Separately compiled modules can be relocated at run time by changing the base address of their segments. The size of a segment is variable; therefore, a segment can be exactly the size of the module it contains.

• 80386 transforms logical addresses into physical address two steps:

• Segment translation: a logical address is converted to a linear address.

• Page translation: a linear address is converted to a physical address.(optional)

• These translations are performed in a way that is not visible to applications programmers.

Conclusion The session is concluded with some questions

1.What is Logical Address? 2. What is Physical address 3.Demonstrate the conversion of Logical Address to physical address.

Session 8

Data Types

Data Types- Bytes, words, and double words are the fundamental data types. A byte is eight contiguous bits starting at any logical address. The bits are numbered 0 through 7; bit zero is the least significant bit.

A word is two contiguous bytes starting at any byte address. A word thus contains 16 bits. The bits of a word are numbered from 0 through 15; bit 0 is the least significant bit. The byte containing bit 0 of the word is called the low byte; the byte containing bit 15 is called the high byte.

Each byte within a word has its own address, and the smaller of the addresses is the address of the word. The byte at this lower address contains the eight least significant bits of the word, while the byte at the higher address contains the eight most significant bits.

A doubleword is two contiguous words starting at any byte address. A doubleword thus contains 32 bits. The bits of a doubleword are numbered from 0 through 31; bit 0 is the least significant bit. The word containing bit 0 of the doubleword is called the low word; the word containing bit 31 is called the high word.

Each byte within a doubleword has its own address, and the smallest of the addresses is the address of the doubleword. The byte at this lowest address contains the eight least significant bits of the doubleword, while the byte at the highest address contains the eight most significant bits. Figure 2-3 illustrates the arrangement of bytes within words anddoublewords.

Note that words need not be aligned at even-numbered addresses and doublewords need not be aligned at addresses evenly divisible by four. This allows maximum flexibility in data structures (e.g., records containing mixed byte, word, and doubleword items) and efficiency in memory utilization. When used in a configuration with a 32-bit bus, actual transfers of data between processor and memory take place in units of doublewords beginning at addresses evenly divisible by four; however, the processor converts requests for misaligned words or doublewords into the appropriate sequences of requests acceptable to the memory interface. Such misaligned data transfers reduce performance by requiring extra memory cycles. For maximum performance, data structures (including stacks) should be designed in such a way that, whenever possible, word operands are aligned at even addresses and doubleword operands are aligned at addresses evenly divisible by four. Due to instruction prefetching and queuing within the CPU, there is no requirement for instructions to be aligned on word or doubleword boundaries. (However, a slight increase in speed results if the target addresses of control transfers are evenly divisible by four.)

Although bytes, words, and doublewords are the fundamental types of operands, the processor also supports additional interpretations of these operands. Depending on the instruction referring to the operand, the following additional data types are recognized:

Integer: A signed binary numeric value contained in a 32-bit doubleword, 16-bit word, or 8-bit byte. All operations assume a 2's complement representation. The sign bit is located in bit 7 in a byte, bit 15 in a word, and bit 31 in a doubleword. The sign bit has the value zero for positive integers and one for negative. Since the high-order bit is used for a sign, the range of an 8-bit integer is -128 through +127; 16-bit integers may range from -32,768 through +32,767; 32-bit integers may range from -2^(31) through +2^(31) -1. The value zero has a positive sign. Ordinal: An unsigned binary numeric value contained in a 32-bit doubleword, 16-bit word, or 8- bit byte. All bits are considered in determining magnitude of the number. The value range of an 8-bit ordinal number is 0-255; 16 bits can represent values from 0 through 65,535; 32 bits can represent values from 0 through 2^(32) -1. Near Pointer: A 32-bit logical address. A near pointer is an offset within a segment. Near pointers are used in either a flat or a segmented model of memory organization. Far Pointer: A 48-bit logical address of two components: a 16-bit segment selector component and a 32-bit offset component. Far pointers are used by applications programmers only when systems designers choose a segmented memory organization. String: A contiguous sequence of bytes, words, or doublewords. A string may contain from zero bytes to 2^(32) -1 bytes (4 gigabytes). Bit field: A contiguous sequence of bits. A bit field may begin at any bit position of any byte and may contain up to 32 bits. Bit string: A contiguous sequence of bits. A bit string may begin at any bit position of any byte and may contain up to 2^(32) -1 bits. BCD: A byte (unpacked) representation of a decimal digit in the range 0 through 9. Unpacked decimal numbers are stored as unsigned byte quantities. One digit is stored in each byte. The magnitude of the number is determined from the low-order half-byte; hexadecimal values 0-9 are valid and are interpreted as decimal numbers. The high-order half-byte must be zero for multiplication and division; it may contain any value for addition and subtraction. Packed BCD: A byte (packed) representation of two decimal digits, each in the range 0 through 9. One digit is stored in each half-byte. The digit in the high-order half-byte is the most significant. Values 0-9 are valid in each half-byte. The range of a packed decimal byte is 0-99. Figure 2-4 graphically summarizes the data types supported by the 80386.

Conclusion The session is concluded with some questions