EE586 VLSI Design Partha Pande School of EECS Washington State University [email protected] Lecture 1 (Introduction)

 Why is designing digital ICs different today than it was before?  Will it change in future? The First Computer

The Babbage Difference Engine (1832) 25,000 parts cost: £17,470 ENIAC - The first electronic computer (1946) The Transistor Revolution

First transistor Bell Labs, 1948 The First Integrated Circuits

Bipolar logic 1960’s

ECL 3-input Gate Motorola 1966 Intel 4004 Micro-Processor

1971 1000 transistors 1 MHz operation Intel Pentium (IV) microprocessor Moore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months Moore’s Law

16 15 14 13 12 11 10 9 8 7 6 OF THE NUMBER OF

2 5 4 LOG 3 2 1

COMPONENTS PER INTEGRATED FUNCTION 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975

Electronics, April 19, 1965. Evolution in Complexity Transistor Counts

1 Billion K Transistors 1,000,000

100,000 Pentium® III 10,000 Pentium® II Pentium® Pro 1,000 Pentium® i486 100 i386 80286 10 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected

Courtesy, Intel Moore’s law in Microprocessors

1000 2X growth in 1.96 years! 100

10 P6 Pentium® proc 1 486 386 0.1 286 Transistors (MT) Transistors 8086 Transistors8085 on Lead Microprocessors double every 2 years 0.01 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year

Courtesy, Intel Die Size Growth

100

P6 486 Pentium ® proc 10 386 286 8080 8086 Die size (mm) size Die 8085 ~7% growth per year 8008 4004 ~2X growth in 10 years

1 1970 1980 1990 2000 2010 Year Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel Frequency

10000 Doubles every 1000 2 years

100 P6 Pentium ® proc 486 10 386 8085 8086 286 Frequency (Mhz) 1 8080 8008 4004 0.1 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years

Courtesy, Intel Power Dissipation 100 P6 Pentium ® proc 10 486 8086 286 386 8085 1

(Watts) Power 8080 8008 4004

0.1 1971 1974 1978 1985 1992 2000 Year

Lead Microprocessors power continues to increase

Courtesy, Intel Power will be a major problem 100000 18KW 10000 5KW 1.5KW 1000 500W Pentium® proc 100 286 486 10 8086 386 (Watts) Power 8085 8080 8008 1 4004

0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive

Courtesy, Intel Power density

10000 Rocket Nozzle 1000 Nuclear Reactor 100

8086 10 4004 Hot Plate P6

Power Density (W/cm2) Density Power 8008 8085 386 Pentium® proc

8080 286 486 1 1970 1980 1990 2000 2010 Year

Power density too high to keep junctions at low temp

Courtesy, Intel Not Only Microprocessors

Cell Phone

Small Power Signal RF RF

Digital Cellular Market

(Phones Shipped) Power Management 1996 1997 1998 1999 2000

Analog Units 48M 86M 162M 260M 435M Baseband

Digital Baseband (DSP + MCU)

(data from Texas Instruments)

MOS Transistor Scaling (1974 to present)

Scaling factor s=0.7 per node (0.5x per 2 nodes)

Metal pitch Technology Node set by 1/2 pitch (interconnect)

Poly width Gate length (transistor) Ideal Technology Scaling (constant field)

Quantity Before Scaling After Scaling

Channel Length L L’ = L * s

Channel Width W W’ = W * s

Gate Oxide thickness tox t’ox = tox * s

Junction depth xj x’j = xj * s

Power Supply Vdd Vdd’ = Vdd * s

Threshold Voltage Vth V’th = Vth * s

Doping Density, p N A NA’ = NA / s

n+ ND ND’ = ND / s

Challenges in Digital Design

∝ DSM ∝ 1/DSM

“Microscopic Problems” “Macroscopic Issues” • Ultra-high speed design • Time-to-Market • Interconnect • Millions of Gates • Noise, Crosstalk • High-Level Abstractions • Reliability, Manufacturability • Reuse & IP: Portability • Power Dissipation • Predictability • Clock distribution. • etc.

Everything Looks a Little Different …and There’s a Lot of Them! ? Productivity Trends

10,000 100,000 10,000,000(M) 100,000,000

Logic Tr./Chip 1,000,0001,000 10,000,00010,000 Tr./Staff Month.

Mo.

100 1,000 100,000 1,000,000 -

10 58%/Yr. compounded 100 10,000 Complexity growth rate 100,000 1 10 Complexity 1,000 10,000

x Productivity 0.1 x 1 100 x x 21%/Yr. compound 1,000 x x x Productivity growth rate Trans./Staff (K) Logic Transistor per Chip Logic Transistor x 0.0110 1000.1

0.0011 100.01 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009

Source: Sematech Complexity outpaces design productivity

Courtesy, ITRS Roadmap Why Scaling?

 Technology shrinks by 0.7/generation  With every generation can integrate 2x more functions per chip; chip cost does not increase significantly  Cost of a function decreases by 2x  But … . How to design chips with more and more functions? . Design engineering population does not double every two years…  Hence, a need for more efficient design methods . Exploit different levels of abstraction Design Abstraction Levels

SYSTEM

MODULE +

GATE

CIRCUIT

DEVICE G S D n+ n+ Design Metrics

 How to evaluate performance of a digital circuit (gate, block, …)? . Cost . Reliability . Scalability . Speed (delay, operating frequency) . Power dissipation . Energy to perform a function Cost of Integrated Circuits

 NRE (non-recurrent engineering) costs . design time and effort, mask generation . one-time cost factor  Recurrent costs . silicon processing, packaging, test . proportional to volume . proportional to chip area NRE Cost is Increasing Die Cost

Single die

Wafer

Going up to 12” (30cm)

From http://www.amd.com Cost per Transistor

cost: ¢-per-transistor 1 0.1 Fabrication capital cost per transistor (Moore’s law) 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012 What about Interconnect

 Global wires . Non-scalable delay . Delay exceeds one clock cycle

 Non-scalable interconnects  Excessive power dissipation  Non reliability in signal transmission Emerging Interconnect Technologies

Three Dimensional Integration

Optical Interconnects Wireless/RF Interconnects

Lower Latency and Energy Dissipation Summary

 Digital integrated circuits have come a long way and still have quite some potential left for the coming decades  Some interesting challenges ahead . Getting a clear perspective on the challenges and potential solutions is the purpose of this course  Understanding the design metrics that govern digital design is crucial . Cost, reliability, speed, power and energy dissipation

Course Structure

 MOS Transistors  MOS Inverter Circuits  Static MOS Gate Circuits  High-Speed CMOS Logic Design  Transfer Gate and Dynamic Logic Design  Semiconductor Memory Design  Advanced Devices beyond CMOS

Course Structure

 Extensive use of CAD tools  Homework assignments  One to two midterm exams and one final exam  Course Project

Suite of two courses EE 466/586 and EE587 will cover various aspects starting from circuits to systems

References  Textbook: . CMOS VLSI Design, Weste and Harris, Fourth Edition  Additional Reference: . Analysis and Design of Digital Integrated Circuits - In Deep Submicron Technology, Hodges, Jackson and Saleh, McGraw-Hill, Third Edition, 2004. . J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective. Second Edition, Prentice Hall, 2003.  Important announcements will be posted in the course website . www.eecs.wsu.edu/~ee586