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White Paper Introduction to ® Architecture

Introduction to Intel® Architecture

The Basics

Executive Summary The term Intel® architecture encompasses a combination of and supporting hardware that creates the building blocks for a variety of systems. Although the architecture is straightforward and remarkably well-supported, the workings of these components may not be obvious to engineers, programmers, or product developers with no previous Intel architecture experience. This paper describes the basic operations and functions of the relevant components, using three example systems. Specifically, the paper will focus on the Intel® Core™ i7 (high-performance) and the Intel® ™ processor (low-) implementations. In each case, the paper will walk the reader through the operation of the ’s communication with memory and I/O devices, the interaction between different types of components, and related design criteria. The goal of this paper is to The various system components are described along with the services they provide. describe the basic operation This paper will also define common terms used when describing Intel architecture designs and their operation. The final section highlights design aids, support, and and function of three classes of collateral provided by Intel and its partner provides to help create successful products. hardware platforms based on the Intel architecture and the components used.

Jim Turley Principal Analyst, Silicon Insider White Paper Introduction to Intel® Architecture

Table of Contents What is Intel® Architecture? experience. can be reused across generations of products, and product Intel® is the world’s oldest and most- What is Intel® Architecture?. . . . . 1 teams can protect their investment (in established microprocessor company, both hardware and software) in a cost- Introduction to Intel® Architecture. . . 1 producing the world’s most popular efficient manner. Although original work microprocessor chips. Although perhaps Basics of an Intel® Architecture may be required to take advantage of the best known for its PC processors, Intel System...... 4 newest microprocessor features, the old devices are used in virtually every field Intel® Core™ i7 Processor–Based software will still work as-is. of , including automotive, System...... 5 industrial, automation, robotics, consumer Intel architecture chips have obviously The Intel® Core™ i7 Processor. . . . 5 electronics, image processing, networking, undergone many changes over the past Intel’s encryption, military, construction, medical, 40+ years. A list of currently available 1 (DMI)...... 6 energy, and other industries. devices is available here. Early chips were given technical part numbers, such (PCH). . . 6 Designers unfamiliar with the Intel as 8086, 80386, or 80486. This led to Intel® Atom™ Processor–Based architecture may have concerns about the commonly used shorthand of “ System...... 9 the architecture’s fundamental concepts, architecture,” in reference to the last its inner workings, or its complexity. The two digits of each ’s part number. The Intel® Atom™ Processor. . . . 9 goal of this paper is to educate skilled Beginning in 1993, the “x86” naming Tools for New Designs...... 9 developers with no previous exposure convention gave way to more memorable Conclusion ...... 10 to the Intel architecture and to provide (and pronounceable) product names guidance regarding system components such as Intel® ® processor, Intel® References...... 10 and concepts. ® processor, Intel® Core™ processor, and Intel® Atom™ processor. Introduction to Intel® Architecture Although every branch of the broad Since the first tiny Intel architecture (or x86) family tree microprocessor chip was made in 1971, retains the same basic features and Intel has produced an unbroken series functionality as the earlier chips, and of upgrades and improvements to the retains backward compatibility with them, world’s best known microprocessor family. each new generation also adds its own From its early 8-bit beginnings, the Intel unique features to the mix. For example, architecture now encompasses a range Intel Pentium processor added of 32-bit and 64-bit microprocessors extensions (called MMX™ ) that that address a range of applications, accelerated audio and video processing. performance requirements, power levels, Extended temperature Intel Pentium and price points. processor with MMX technology is with The cornerstone of Intel architecture’s more streaming-media capabilities known popularity is its compatibility. Each as Intel® Streaming SIMD Extensions (Intel® new generation of Intel architecture SSE) and Intel® Streaming SIMD Extensions microprocessor is a superset of its 2 (Intel® SSE2). Floating-point units (FPUs) predecessors, providing backward went from optional upgrade to standard compatibility with older chips and older feature of Intel architecture processors, software, while also adding new or and today encryption/decryption enhanced features. This compatibility extensions, power-management features, allows engineers, programmers, and and multilevel caches are now found on development teams to reuse the most Intel architecture processors. software and software-development paths have widened from 8 bits to 32 tools from earlier projects, protecting bits, 64 bits, and even 128 bits and more. their investment in time and talent. It Operating frequencies have jumped from 1 http://ark.intel.com also makes developing new Intel-based a few megahertz to 2 GHz (two billion systems easier by leveraging developers’ cycles per second) and beyond.

2 White Paper Introduction to Intel® Architecture

Some abbreviations used in the diagrams below: LPC ; a simple interface SATA Serial ATA; a popular to slower I/O devices disk-interface standard BIOS Basic Input/Output System; a boot ROM PCH Platform Controller Hub; SPI Serial Peripheral Interface; a companion chip simple interface to DDR3 Double Data-Rate v3; a popular slower devices DRAM interface standard PCI Peripheral Component Interconnect; a popular DMI Direct Memory Interface; a expansion video graphics standard PCIe* PCI Express*; an upgraded PCI FIVR Fully Integrated standard Regulator

Figure 1: Typical system based on the Intel® Core™ i7 processor

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*

Figure 2: Typical system with Intel® Atom™ processor (SoC)

Similarly, many Intel® architecture chips ever more capable, there have been not stand alone, but works in concert now boast multicore performance, similar advances with the support logic, with compatible support chips. Different meaning that two or more Intel the development tools, and completely Intel architecture processors work with architecture processor cores, or “engines,” integrated hardware “platforms.” Every different support chips, and this paper operate within a single chip. Many also Intel architecture processor is supported outlines two representative examples. offer multithreading, a technique that by one or more chip sets that provide The first example describes a typical is designed to improve performance by needed system-level functions, and some hardware platform based on the allowing a single Intel architecture core to Intel architecture processors include their high-performance Intel® Core™ i7 processor perform multiple tasks. All the while, the own integrated functions such as memory combined with similarly high-performance power consumption and heat controllers, graphics engines, or network support logic (see Figure 1). The second of these processor chips has been kept interfaces. Sometimes the “chip set” is example focuses on a small, low-cost Intel in check thanks to aggressive on-chip internal, and the processor becomes a Atom processor–based system power-management hardware (some of standalone SoC – a . (see Figure 2). which is adjustable through software) and industry-leading - Basics of an Intel® Architecture Generally speaking, every Intel manufacturing technology. An in-depth System architecture hardware platform will description of the Intel architecture include two major components: the The hardware requirements for each technical features can be found in the microprocessor chip, and a companion customer application will be different, of Intel Software Developer’s Manual, chip known as the platform controller hub course, but some basics apply to all. The available here.2 (PCH). In earlier times, Intel® processors processor chip itself is just the beginning. were paired with two companion chips, And while the processors have gotten With few exceptions, the processor does often called the “north bridge” and

2 http://download.intel.com/design/processor/ manuals/253665.pdf 4 White Paper Introduction to Intel® Architecture

the “south bridge,” or the MCH and the Intel® Core™ i7 Processor–Based The i7 processor achieves its ICH. Nowadays, the functions of the System high performance through its multiple CPU north bridge are usually included in cores and its Simultaneous Multithreading the processor itself, while the south The example in Figure 1 illustrates a (SMT) feature. Between the four cores bridge has been replaced by the much high-performance system based on the (in this example) and the two-way more capable PCH. In single-chip (SoC) quad-core Intel Core i7 processor, the multithreading per core, the Intel Core i7 configurations, there is no PCH; its Intel® Q87 (Intel® DH82Q87 PCH), processor appears to software as eight functions are included in the processor two banks of external DDR3 DRAM, and independent 64-bit CPUs. itself. several peripheral devices and interfaces. This configuration represents a high-end Figure 3 shows a representation of the Surrounding these two components system with maximum performance with silicon for Intel Core i7 processor, with (i.e., processor and PCH) will be other maximum capability and expandability. its four independent CPU cores and other customer-supplied components including features highlighted. Figure 4 shows a DRAM, a boot ROM, a power supply, and The Intel® Core™ i7 Processor conceptual diagram of the same processor, the peripheral interfaces appropriate for The heart of this system design is illustrating how the four CPUs each has the system, such as a network or the Intel® Core™ i7-4770S processor, a its own L1 and L2 caches, and the shared connection. Most systems will also include high-end 64-bit implementation of the L3 . some nonvolatile memory (e.g. flash or Intel architecture. The particular 4th The processor’s on-chip DRAM controller E2PROM), and perhaps some “” generation, or “Haswell,” Intel Core i7 is responsible for . If data that is specific to the application. processor shown in the diagram has at the address requested is not in one As these diagrams show, one of the example several notable features, including: of the processor’s caches, or if the data systems is based on a two-chip set (processor • Four independent CPU cores in external memory is newer than the and PCH), while the second example cached copy, the is uses only a single chip (the processor) • Two-way multithreading per CPU core told to retrieve the data at the requested with integrated controllers. The former • A built-in two-channel DDR3 DRAM address. Data transfers between the is designed for higher performance and controller processor and memory are always 64 more expansion capability, while latter bits wide, the full width of the L2 cache is optimized for small size and low cost. • Integrated L1, L2, and L3 caches on the processor. If only a of data is These examples highlight just two of the • Direct Media Interface (DMI) connection requested, the full 64 bits are retrieved many options available to designers of Intel between the processor and the PCH but the processor may use only 8 of those architecture systems.

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Figure 3: Intel® Core™ i7 processor internal die photograph

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bits. The memory controller is configurable via the BIOS to support multiple speeds and/or sizes of memory. DRAM refresh is also handled by the memory controller, after it’s initially configured. The specific type, size, and speed of memory supported varies by processor. The PCI Express (PCIe) interface is the highest bandwidth I/O interface in the Intel architecture system. The number of PCIe lanes can vary depending on the processor used, but will usually be in multiples of four. A common width for PCIe is 16 lanes, as this is the maximum width for discrete PCIe graphics cards. The PCIe interface uses the same as the DMI, although PCIe supports higher rates. The original PCIe specification specifies data rates of 2.5 GT/sec (250 MB/sec) per lane, the same as DMI. The second generation of PCIe doubles the data rate to 5 GT/sec (500 MB/sec). Intel’s Direct Media Interface (DMI) DMI is the name given to the link between the Intel Core i7 processor and its companion chip, the Intel Q87 chipset (Intel® DH82Q87 PCH). The same DMI interface is used by several different processor and PCH implementations, including the Intel Core i7-4770S, Intel® Core™ i5-4570S, Intel® Core™ i3-4330 Figure 4: Intel® Core™ i7 processor internal block diagram. processors, Intel® Pentium® processor G3420, Intel Q87 chipset, Intel® H81 Express chipset, and Intel® C226 chipset. and all use differential signaling. Thus, the Platform Controller Hub (PCH) The DMI bus is a high-speed, point-to- DMI is 4 lanes × Transmit and Receive (2) point link between two chips, as shown The Platform Controller Hub (PCH) chip is × differential signaling (2) = 16 pins. DMI in the diagram. It differs from Intel® a highly integrated device intended to supports signaling of 2.5 billion transfers/ QuickPath Interconnect (Intel® QPI) in that prove all the high-value features and sec. (Other chips implementing DMI 2.0 it supports only two chips: a processor interfaces required for a midrange to may achieve 5 GT/sec.) and a PCH, whereas Intel QPI is used in high-end system. Depending on the multi-socket configurations with two or DMI also integrates advanced priority- particular model of PCH chip, it may more processors. DMI supports transfers based servicing, allowing for concurrent provide a controller for multiple banks of rates of 2 GB/second over each of two traffic and isochronous transfer DRAM, a controller for multiple graphics unidirectional lanes. capabilities that improve performance displays (an accelerator for which may be over the earlier QPI interface. This ensures present on the processor itself), several DMI is implemented as four serial links that the I/O subsystem (PCI Express, audio, USB interfaces, SATA controller for with dedicated transmit and receive pins. SATA, USB, etc.) receives the bandwidth disk drives and other storage media, an These serial links are referred to as “lanes” necessary for peak performance. LAN port, Intel® High Definition

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Figure 5: PCH internal block diagram

Audio (Intel® HD Audio), and more. eight PCI Express 2.0 root ports • Clock controller, DMA controllers, event supporting up to 5 GT/second (five , real-time clock, JTAG boundary As the diagram in Figure 5 shows, the PCH billion transfers per second). scan, low-pin-count interface for a connects directly to the processor’s DMI (TPM), interface, with no additional engineering • Up to six SATA ports, with integrated serial-peripheral interface (SPI), and required from the developer. Simply AHCI controller, and data rates of 6.0, much more. connect the appropriate pins and go. 3.0, and 1.5 Gb/sec on all ports. The PCH itself is a complex and software- • An IEEE 802.3 Ethernet LAN MAC programmable component with several supporting 10/100/1000 Mbit/sec data features to enhance system performance rates and jumbo frames. and reliability. Chief among them are: • Intel® Technology (Intel® • PCI Express Root Port Controllers. In VT) for Directed I/O (Intel® VT-d); Intel® the case of the Intel Q87 chipset (Intel® Anti-Theft Technology (Intel® AT); Intel® DH82Q87 PCH), the PCH supports up to Trusted Execution Technology (Intel® TXT)

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Modern I/O Interfaces • Serial Peripheral Interface (SPI) is used • Advanced Programmable to interface to BIOS flash devices that Controller (APIC) is a more modern The PCH acts a bridge or controller for a contain boot and initialization interrupt controller than the earlier variety of industry-standard interfaces code. Up to two SPI flash devices 82C59 (see below). It supports allowing the system designer to choose operating at 33 MHz can be connected. multiprocessor/multicore interrupt from a wide range of , Note that the flash devices connected to management by allowing including: the LPC interface are quickly becoming to be directed to a specific processor. • PCI interface operates at 33 MHz and obsolete and SPI is expected to be The I/O APIC in the PCH can support allows for a number of external bus standard interface for BIOS flash in the up to 24 interrupt vectors and works masters. The PCH acts as the central future. The PCH is always a master on in conjunction with I/O APICs in other arbiter and root of the PCI bus. the SPI interface. devices to help eliminate the need for share interrupts among • PCI Express root port controllers. The • Low Pin Count Interface (LPC) This multiple devices. number of ports varies with the specific interface replaces the ISA bus originally PCH component but is generally in the developed by IBM in the early 1980s, Compatibility Peripherals range of 1 to 4. Link widths of ×1 ×4 are but uses only 7 signals plus a clock. It The PCH contains peripherals compatible support at speeds of 2.5 GT/sec. can be used to connect to a variety low with those dating back to the earliest speed devices that don’t require the • Serial ATA (SATA) controllers supporting IBM PCs with an ISA bus. Modern systems bandwidth of PCI or PCI Express. This both legacy operation using I/O space replace the ISA bus with the Low interface is typically used to interface and the Advanced Host Controller Pin-Count (LPC) bus, but the peripherals with Super I/O devices which contain Interface (AHCI) using memory-mapped that were once discrete components are many interfaces such as floppy driver I/O, as well as allowing advanced now integrated into the PCH. One key controller, PS2 keyboard/mouse features such has hot-plug and native strength of Intel architecture is its controls and serial ports. command queuing. SATA II supports data combination of backward compatibility rates of 1.5 Gb/sec and 3 Gb/sec. • JTAG Boundary Scan allows testing of and continuing innovation. PCB board after assembly. • Integrated Drive Electronics (IDE) The PCH contains two 82C37 DMA controllers are also used to control hard Support Peripherals controllers, two ISA-compatible 82C59 disc drives and CD/DVD drives. They have interrupt controllers, and three 82C54 The PCH integrates numerous support been replaced in some platforms by the programmable interval equivalents. peripherals that replace many external newer SATA interface since SATA offers components. better performance over a smaller interface. • Real Time Clock (RTC): The RTC is compatible with the popular MC146818A. • Universal Serial Bus (USB) supporting It contains 256 of RAM that can High Speed USB 2.0 (480 Mb/sec) be maintained with a 3V battery. Of operation as well as full-speed (12 Mb/ processor is that space, 242 bytes are available for sec) and low-speed signaling. programmer use, while the remaining a fairly recent addition to • General Purpose I/O (GPIO) pins for are dedicated to the clock function. the Intel architecture family system customization. Many pins can The RTC can generate wake events up also be configured to cause interrupts to 30 days in the future. An external of 32-bit processors. It is or wake events. 32.768-KHz crystal is required for intended for embedded systems operation. •  (SMBus where small size, modest 2 .0) The SMBus Host interface allows • High Precision Event Timers These the processor to communicate with are high-resolution timers that can be power consumption, and SMBus slaves. This interface is also used to generate periodic or one-shot low cost are important. compatible with most I2C devices. Slave interrupts. There are eight comparators, functionality, including the Host Notify which share a common that is protocol is implemented. clocked from a 14.31818-MHz source.

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The 82C37 DMA controllers should not Intel® Boot Loader Development Kit Like the Intel Core i7 processor, Intel be confused with the DMA engines found (Intel® BLDK), which can be used to Atom processor E3800 product family in some earlier MCH (Memory Controller create a UEFI-compliant (Unified has its own on-chip DRAM controller, able Hub) components. These DMA controllers Extensible Firmware interface) boot to handle two channels of DDR3 DRAM. are tied to the ISA/LPC bus and used loader compatible with many One channel can optionally support ECC mostly for transfers to/from slow operating systems. (error correction), further enhancing devices such as floppy disk controllers. system reliability. For a more minimally functional boot The ISA-compatible 82C59 interrupt loader, Intel® Firmware Support Package Tools for New Designs controllers have been largely supplanted (Intel® FSP) may be sufficient. Intel FSP by the Advanced Programmable Interrupt includes royalty-free code that supports This section gives an overview of some Controller (APIC, see above) since the the most critical functions of Intel reference documentation available to letter offers support for more than architecture processors and . help with an Intel architecture design. 15 interrupt sources and supports The Intel FSP code may be included in a Many of these documents are available multicore/multiprocessor systems. more fully featured UEFI-compliant at http://developer.intel.com/design/ However, the 82C59 controllers are still boot loader, if desired. index.htm. Others may require a used by some older operating systems non-disclosure agreement (NDA) and will that run only on single-processor (single Intel® Atom™ Processor–Based be made available through your sales CPU) systems. System representative. The BIOS Compared to the Intel Core i7 Intel® Embedded Design Center site (http://edc.intel.com) also provides a Like any , an Intel architecture processor–based system described wealth of information, documentation, system requires a boot ROM to bootstrap above, an Intel Atom processor-based and two-way communication with other the processor and, optionally, load system is almost trivially simple. This Intel architecture developers. an and configure example is based on an Intel® Atom™ components. In an Intel architecture processor E3800 product family, which Platform Design Guides are available system, this boot ROM has typically been has all the necessary controllers and under nondisclosure agreement and give known as the BIOS: the basic peripherals already integrated into it, detailed printed-circuit board design input/output system. doing away with the need for a companion recommendation including PCB stack-up, chip. Refer back to Figure 2 for an impedance targets, material selection, The BIOS controls the activity of the Intel overview of this system configuration. and layout recommendations. architecture hardware until the operating system takes over. One job of the BIOS is The Intel® Atom™ Processor Platform Reference Schematics given to configure registers and components Intel Atom processor is a fairly recent an example system implantation. and set up the devices to the particulars addition to the Intel architecture family Thermal and Mechanical Design Guide of the system hardware into which of 32-bit processors. It is intended for covers heat sink design recommendations the Intel architecture is designed. In a embedded systems where small size, and package/socket attachment to the typical PC design, some of the hardware modest power consumption, and low cost . is dedicated by the design based on the are important. For that reason, Intel design, but other hardware Atom processor includes its own on-chip Datasheets (Processors) contain aspects vary based on what the end DRAM controller, PCI Express interface, electrical, thermal and package user may plug into the motherboard. optional display controller, USB controllers, mechanical information for Intel As the BIOS executes, after the initial real-time clock, timers, interfaces to processors. configuration is done, it will determine the system-management functions. The Datasheets (MCH/IOH/ICH/PCH) type and amount of memory, then it goes overall system thus enjoys small size contains a functional and register through a discovery phase. Once all the with high integration. description of the device. Pinout and devices and hardware are configured the package mechanical information is also BIOS will turn over control of the system With no DMI (nor any need for one), included. Electrical Electrical specifications to an operating system. Intel Atom processor uses PCI Express as its primary means of expansion. PCIe may be in the datasheet or might Many Intel architecture platforms come has sufficient bandwidth for extensive require a non-disclosure agreement. with the necessary boot firmware already expansion capability, and its standardized installed. To create a boot ROM for a interface is compatible with many devices custom or updated system, Intel offers its from multiple vendors. 9 White Paper Introduction to Intel® Architecture

Intel® 64 and IA-32 Architectures Software Developer’s Manuals These manuals describe the architecture and programming environment of the Intel® Acronyms 64 and IA-32 processors. CPU Specification Updates contain lists of errata and the most recent changes to the BLDK Boot Loader Development other documents. Specification updates should always be consulted for the latest Kit available information. DMI Direct Media Interface Intel’s Packaging Databook is intended to serve only as a data reference FSB Front Side Bus guide to Intel package selection and availability. As the packaging landscape changes very rapidly, information can become outdated very quickly. Please refer FSP Firmware Support Package to the product specifications on the products site for the most current detailed GLCI Gigabit LAN Connection package information. Interface

Conclusion ICH Input / Output Control Hub IOH Input / Output Hub The Intel architecture offers a complete and well-thought-out launching point for a variety of systems. It spans an array of features, performance, and power levels. LAN Local Area Network The ability to reuse software and software tools across different generations and LCI LAN Connection Interface different product families is a great benefit to product teams and gives designers LPC Low Pin Count Interface the ability to scale performance and features without new software rewrites. The basic building blocks of an Intel architecture system are highly integrated and make MCH Memory Controller Hub system design as straightforward as possible. Intel provides all of the resources PCH Platform Controller Hub necessary to design leading-edge products, so go to http://www.intel.com and PCI Peripheral Component start creating. Interconnect References PCIe Peripheral Component Interconnect Express Intel CPU History http://www.intel.com/pressroom/kits/quickreffam.htm QPI QuickPath Interconnect Current Intel® Product Information http://ark.intel.com SPI Serial Peripheral Interface Intel Developers Centers http://developer.intel.com/design/index.htm UEFI Unified Extensible Firmware Interface x86 Common shorthand for Intel® architecture

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