Madison Processor

Home , 130 nm process, 65 nm process, Datapath, Intel 4004, Memory controller, Montecito (processor)

TheThe RoadRoad toto BillionBillion TransistorTransistor ProcessorProcessor ChipsChips inin thethe NearNear FutureFuture

DileepDileep BhandarkarBhandarkar RogerRoger GolliverGolliver

Intel Corporation

April 22th, 2003

yy SemiconductorSemiconductor TechnologyTechnology EvolutionEvolution yy Moore’sMoore’s LawLaw VideoVideo yy ParallelismParallelism inin MicroprocessorsMicroprocessors TodayToday yy MultiprocessorMultiprocessor SystemsSystems yy TheThe PathPath toto BillionBillion TransistorsTransistors yy SummarySummary

IntroducedIntroduced NovemberNovember 15,15, 19711971 108108 KHz,KHz, 5050 KIPsKIPs ,, 23002300 1010μμ transistorstransistors 20012001 –– Pentium®Pentium® 44 ProcessorProcessor

Introduced November 20, 2000

@1.5 GHz core, 400 MT/s bus 42 Million 0.18µ transistors

August 27, 2001

@2 GHz, 400 MT/s bus 640 SPECint_base2000* 704 SPECfp_base2000*

SourceSource:: hhtttptp:/://www/www.specbench.org/cpu2000/results/.specbench.org/cpu2000/results/ 3030 YearsYears ofof ProgressProgress yy40044004 toto PentiumPentium®® 44 processorprocessor –– TransistorTransistor count:count: 20,000x20,000x increaseincrease –– Frequency:Frequency: 20,000x20,000x increaseincrease –– 39%39% CompoundCompound AnnualAnnual GrowthGrowth raterate 20022002 –– Pentium®Pentium® 44 ProcessorProcessor

November 14, 2002

@3.06 GHz, 533 MT/s bus

1099 SPECint_base2000* 1077 SPECfp_base2000*

55 Million 130 nm process

SourceSource:: hhtttptp:/://www/www.specbench.org/cpu2000/results/.specbench.org/cpu2000/results/ ItaniumItanium® 22 ProcessorProcessor OverviewOverview y .18μm bulk, 6 layer Al Branch Unit Floating Point Unit process IA32 Pipeline Control y 8 stage, fully stalled in- L1I order pipeline cache ALAT Integer Multi- Int L1D Medi y Symmetric six integer- Datapath RF cache a issue design CLK unit HPW y IA32 execution engine DTLB integrated y 3 levels of cache on-die 21.6 mm L2D Array and Control L3 Tag totaling 3.3MB y 221 Million transistors Bus Logic y 130W @1GHz, 1.5V y 421 mm2 die 2 y 142 mm CPU core L3 Cache

19.5mm MadisonMadison ProcessorProcessor Branch Unit Floating Point Unit y 130 nm process Pipeline Control y ~1.5 GHz L1I y ~1.5 GHz IA32 Cache Multi- ALAT Integer Int Media y 6 MB L3 Cache L1D DataPath y 6 MB L3 Cache RF Unit Cache CLK HPW y 24 way set DTLB associative L2D Cache L3 Tag/LRU PADS y ~130W y 410 M transistors Bus Logic y 374 square mm

L3 Cache ContinuingContinuing atat thisthis RateRate byby EndEnd ofof thethe DecadeDecade

10,000

1,000

Itanium ® 2 100 • 221M in 2002 • 410M in 2003 Pentium® 4 Million 10 Million Pentium® Pro Transistors 1 486 Pentium proc

386 0.1 286

8085 8086 0.01 8080 8008 4004 0.001

’70 ’80 ’90 ’00 ’10

Billion Transistors possible within 4 years NanotechnologyNanotechnology AdvancementsAdvancements

Influenza virus

50nm

90nm Node Lgate = 50nm 65nm Node Production - 2003 45nm Node Lgate = 30nm Lgate = 20nm Production - 2005 Production - 2007 30nm Node Lgate = 15nm Production - 2009 Process Advancements Fulfill Moore’s Law

Source: Intel SemiconductorSemiconductor ManufacturingManufacturing ProcessProcess EvolutionEvolution

Actual Forecast

Process name P852 P854 P856 P858 Px60 P1262 P1264

Production 1993 1995 1997 1999 2001 2003 2005

Generation 0.50 0.35 0.25 0.18µm 130 nm 90 nm 65 nm

Gate Length 0.50 0.35 0.20 0.13 <70 nm <50 nm <35 nm

Wafer Size (mm) 200 200 200 200 200/300 300 300

New generation every 2 years Outline

©2002, Intel Corporation Intel, the Intel logo, Pentium, Itanium and Xeon are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries *Other names and brands may be claimed as the property of others DifferentDifferent FormsForms ofof ParallelismParallelism yyWithinWithin aa processorprocessor corecore –– multiplemultiple issueissue processorsprocessors withwith lotslots ofof executionexecution unitsunits –– widerwider superscalarsuperscalar –– explicitexplicit parallelismparallelism yyMultipleMultiple processorsprocessors onon aa chipchip –– HardwareHardware MultiMulti ThreadingThreading –– MultipleMultiple corescores EPICEPIC ArchitectureArchitecture FeaturesFeatures Explicitly Parallel Instruction Computing y Enable wide execution by providing processor implementations that compiler can take advantage of

y Performance through parallelism – Multiple execution units and issue ports in parallel – 2 bundles (up to 6 Instructions) dispatched every cycle y Massive on-chip resources – 128 general registers, 128 floating point registers y 64 predicpredicateate registers, 8 branch registers – Exploit parallelism – Efficient management engines (register stack engine) y Provide features that enable compiler to reschedule programs using advanced features (predication, speculation, software pipelining) y Enable, enhance, express, and exploit parallelism ItaniumItanium® 22 ProcessorProcessor ArchitectureArchitecture

Itanium 2 processor 6.4 GB/s 6.4 GB/s High speed 128 bits wide System bus 400 MHz System bus

3 MB L3, 256k L2, 32k L1 all on-die Large on-die cache, reduced latency 8-stage pipeline 8

12345678910 11 11 Issue ports 328 on-board Registers Large number of Execution units Lots of 6 Integer, 2 FP, 2 Load & 3 Branch 1 SIMD 2 Store parallelism within a 1 GHz single core 6 Instructions / Cycle

Itanium 2 processor 221 million transistors total 25 million in CPU core logic HighHigh PerformancePerformance DesignDesign SpaceSpace

With Each Process Generation y Frequency increases by about 1.5X y Vcc will scale by only ~0.8 y Active power will scale by ~0.9 y Active power density will increase by ~30-80% y Leakage power will make it even worse

Doubling performance requires more than 4 times the transistors

Instruction Thread Level Level Parallelism Parallelism Single-Stream Perf HW Multi-Threading Chip Multiprocessing

Faster frequency Multi-Core Wider Superscalar More Out-of-order speculation Challenges: Power and Design Complexity PowerPower && PerformancePerformance TradeoffsTradeoffs y Throughput Perf α SQRT(Frequency) y But Power α Capacitance * Voltage2 * Frequency – Frequency α Voltage y Power increases non-linearly with Frequency y Throughput Performance can be achieved at Lower Power with multiple low power cores y Tradeoff between single stream and throughput performance for a constant power envelop

Can optimize for either Throughput or Single Stream SingleSingle--streamstream PerformancePerformance vsvs CostsCosts 25 SPECInt vs 486 vs 486 20 SPECFP perf perf Die Size 15 Power

5 Relative power/die size/ Relative power/die Relative power/die size/ Relative power/die 0 486 Pentium® Pentium® III Pentium® 4 Processor Processor Processor

Die Size and Power have increased with Scalar Performance LongLong LatencyLatency DRAMDRAM Accesses:Accesses: NeedsNeeds MemoryMemory LevelLevel ParallelismParallelism (MLP)(MLP)

1400

1200

1000

800

600 ions during DRAM Access ions during DRAM ions during DRAM Access ions during DRAM 400

200 Peak Instruct Peak Instruct 0 Pentium® Pentium-Pro Pentium III Pentium 4 Future CPUs Processor Processor Processor Processor 66 MHz 200 MHz 1100 MHz 2 GHz MultithreadingMultithreading y Introduced on Intel® Xeon™ Processor MP y Two logical processors for < 5% additional die area y Executes two tasks simultaneously – Two different applications – Two threads of same application – Overlap execution behind memory access y CPU maintains architecture state for two processors – Two logical processors per physical processor y Power efficient performance gain y 20-30% performance improvement on many throughput oriented workloads HyperThreadingHyperThreading Technology:Technology: WhatWhat waswas addedadded toto IntelIntel XeonXeon MPMP Processor?Processor? Instruction Streaming Buffers Next Instruction Pointer

Return Stack Predictor Trace Cache Next IP Trace Cache Fill Buffers

Instruction TLB Register Alias Tables

<5% die size (& max power), up to 30% performance increase IBMIBM Power4Power4 DualDual ProcessorProcessor onon aa ChipChip

Two cores (~30M transistors each)

Large Shared L2: Multi-ported: 3 independent L3 & Mem slices Controller: L3 tags Chip-to-Chip & on-die for MCM-to-MCM full-speed Fabric: coherency Glueless SMP checks

*Other names and brands may be claimed as the property of others MontecitoMontecito DetailsDetails

yy DualDual--corecore processorprocessor Montecito Die

yy EachEach corecore withwith itsits ownown L3L3 Core Core cachecache yy LargerLarger cachecache thanthan previousprevious L3 Cache L3 Cache processorprocessor Arbiter yy ArbiterArbiter managesmanages twotwo corescores asas 11 busbus interfaceinterface System Bus – Enables same socket and protocol Outline

Historically,Historically, systemsystem levellevel featuresfeatures havehave migratedmigrated toto microprocessormicroprocessor chipschips asas transistortransistor densitiesdensities havehave increasedincreased IBMIBM eServereServer pSeriespSeries 690690

y 1.3 GHz Power4 y 8 to 32 CPU y 8-way MCM @ $275,000** y 403,255 tpmc @ $17.80 per tpmC*** y 95 Linpack Gflops

***http://www-132.ibm.com/content/home/store_IBMPublicUSA/en_US/eServer/pSeries/high_end/pSeries_highend.html ***Source: http://www.tpc.org/results/individual_results/IBM/IBMp690es_08142002.pdf *Other names and brands may be claimed as the property of others NECNEC Express5800/1320XcExpress5800/1320Xc SMPSMP ServerServer Up to ® 8 Up to 32 Itanium 2 processors Ce lls Cell Itanium2Itanium2 Itanium2Itanium2 Up to 512GB memory (with 2GB DIMMs) Itanium2Itanium2 Itanium2Itanium2

Up to 112 PCI-X I/O slots MemoryMemory ControllerController CellCell Low latency and high bandwidth ControllerController MemoryMemory ControllerController cross-bar interconnect DDR DIMMs Inter-cell memory interleaving ECC protected data transfer CrossCross-bar-bar interconnectinterconnect ** 433,107 tpmC @ $12.98 per tpmC PCI-X PCIPCI-X-X bridgebridge PCI-X bridge PCI-XPCI-X bridge bridgePCI-XPCI-XPCI-X bridge bridge bridge PCI-XPCI-X1414 bridgePCI-XPCI-X bridge slots slotsPCI-XPCI-X bridge bridge Up to 112slots PCI-X14PCI-X14 PCI-X bridgePCI-X bridge slots slotsPCI-XPCI-X bridge bridge PCI-X1414 PCI-X bridgePCI-X slots slotsPCI-X bridge 101 Linpack GigaFlops 1414 PCI-X PCI-X slots slots 32 Processors + 512GB @ $2,126,090**

**http://www.tpc.org/results/individual_results/NEC/nec.express5800.1320xc.c5.030220.es.pdf *Other names and brands may be claimed as the property of others HPCHPC ClustersClusters yy CommercialCommercial OffOff TheThe ShelfShelf (COTS)(COTS) componentscomponents – Processors – Packaging – Interconnects – Operating systems

15 node dual 2.4GHz Pentium® Xeon® cluster

*Other names and brands may be claimed as the property of others Outline

Process ® Itanium Processor Family Roadmap 0.180.18 µµmm Focus on Compatibility Preserves OEM and End-user Investments 0.130.13 µmµm 9090 nmnm 2002 2003 2004 2005

® ®® ® Itanium®® 2 ItaniumItanium 22 ItaniumItanium 22 ItaniumItanium 22 MP IPF ProcessorProcessor MontecitoMontecito ProcessorProcessor ProcessorProcessor (Madison)(Madison) (Madison(Madison Refresh)Refresh) (Dual Core) Roadmap (1 GHz, 3MB L3) (Dual Core) (1(1 GHz,GHz, 3MB3MB L3)L3) (1.5GHz(1.5GHz,, 6MB6MB L3)L3) (>(>1.5GHz,1.5GHz, 9MB9MB LL33))

® DP IPF ItaniumItanium® 22 ProcessorProcessor InIn DefinitionDefinition InIn DefinitionDefinition Roadmap (De(Deeerfield)rfield)

All dates specified are target dates, are provided for planning purposes only and are subject to change.

Steady Performance Growth Over Time 20022002 VintageVintage ItaniumItanium® 22 ProcessorProcessor Record Setting Performance for Technical Computing

Sun USIII* 1.05GHz IBM Power4* 1.3GHz Itanium® 2 processor 1.0GHz

New New New Industry Industry Industry Record Record Record

125 4.0

1431 1202 1.6 51 711 32 0.9

72P 32P 64P

Floating Point 1P Stream 32P+ Stream (GB/sec) (GB/sec) (specfp_base2000)

Source: http://www.spec.org/ for Sun results as of July 2, 2002. Itanium® 2 Source for Single processor Triad: 5 Source: Itanium® 2 processor measurements done on a SGI processor results measured on HP server rx5670 using Itanium® 2 processor http://www.emsl.pnl.gov:2080/capabs/mscf/?/capabs/mscf/hardware/results Scalable Linux System using 64 Itanium® 2 processors, 128GB 1GHz with integrated 3MB L3 cache, Linux operating system, measured in Nov _hpcs for Itanium® 2 processor and IBM Power 4 results. Sun result from memory, Linux OS. Sun result of 51 from http://cs.virginia.edu/stream 2002. SPECfp* is a trademark of SPEC*. http://cs.virginia.edu/stream website. on Sun 15K with 72 processors at 1050MHz.

Alpha* 1.25GHz IBM Power4* 1.3GHz Itanium® 2 Processor 1.0GHz

Beats New Beats both Sun Industry Best RISC & IBM Record by >45%

87.7k $9.44

Sun USIII* 56.3k 1.05GHz $5.03 804 810 845 537

Integer2 4P 4P ((specint_base2000)specint_base2000) Transaction Price / Processing1 Performance (TPC-C) ($ / TPC-C) DaDatata Sources: 1) TPC-C: www.tpc.org , 2) SPEC benchmabenchmarks:rks: www.spec.org, 3) SAP SD www.sap.com//benchmark

Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, reference www.intel.com/procs/perf/limits.htm or call (U.S.) 1-800-628-8686 or 1-916-356-3104 20032003 ItaniumItanium® 22 ProcessorsProcessors Madison / Deerfield Overview Pre-Production Madison Processor ® y Extends Itanium 2 processor architecture to .13u Performance ReResultssults – Sept. ‘02 process technology – Production targets May - July 2003 1.40X 1.09X +28% y Delivers full platform compatibility 137K – Socket and system bus compatible – Binary compatible with Itanium software – Binary compatible with Itanium software Alpha* 4P 1.25 GHz y Madison processor features – 1.5GHz, 6 MB L3 Cache – +30%-50% performance than Itanium® 2 processor 4P SAP APO Itanium® 2 processor, 1.0 GHz

Madison processor 1.3 GHz (pre-production – Sept. ‘02) Emphasis on compatibility preserves OEM and end-user investment in today’s Itanium 2-based systems

2 Source: Alpha results using HP Alphaserver ES45, 4P SMP, Alpha 2164C 1.25GHz, 16MB L2 cache, 32GB, APO rel. 3.0, Live Cache rel. 7.2.5.7, Oracle 9i Itanium® 2 processor and Madison numbers are preliminary lab results using HP server RX5670, 4 Itanium 2 processors 1.0GHz w/ 3M integrated L3 cache or 4 Madison 6M integrated L3 cache, 32 GB, APO rel. 3.0, Live Cache 7.4.2, Windows .Net Enterprise Server LE1.2 , SQL Server Enterprise Edition (64-bit) beta. Source: Intel estimates. All products, dates and information are preliminary and subject to change without notice.

Itanium® 2 Processor (Deerfield) Summary

y Key features – 1.0GHz core frequency, 1.5MB L3 cache, DP only – 62W maximum power y Compatibility – Based on the Itanium® 2 microarchitecture – Binary compatible with Itanium® processor software – Socket and system bus compatible with Itanium® 2-based DP systems – Intel® 870 chipset support y Target market – Performance rack or blade servers and high-end workstations y Schedule – Platform release target is 2H03, after Madison

Performance of today’s Itanium® 2 processor 1.0 GHz at less than half the power ALL PRODUCTS, DATES and INFORMATION ARE PRELIMINARY AND SUBJECT TO CHANGE WITHOUT NOTICE Intel®Intel® Itanium®Itanium® ArchitectureArchitecture ProcessorProcessor RoadmapRoadmap Next + Two cores per die Next . . . + Higher frequency GenerationGeneration + New thermal technologies PlatformPlatform + Multi-core + Larger caches + 10s of MB of cache + Frequency MontecitoMontecito + Fast, high capacity increase (Dual(Dual Core)Core) memory + Larger caches + Larger caches + Same platform + High RAS memory & I/O + 50% + frequency + PCI Express ® increase ItaniumItanium® 22 nd + Same platform Processor NextNext + 2nd Generation Processor . . . EPIC architecture ® (Madison(Madison 9M)9M) GenerationGeneration EPIC architecture ItaniumItanium® 22 + on-die L3 cache (>1.5GHz,(>1.5GHz, 9MB9MB L3)L3) PlatformPlatform ProcessorProcessor DeerfieldDeerfield + 6.4GB/s bus follow-on (Madison) followfollow-on-on + New levels of RAS (Madison) (1.5GHz, 6MB L3) (1.5GHz, 6MB L3) Itanium®® 2 ® Itanium 2 + Same power envelope as Deerfield ItaniumItanium® 22 Processor ProcessorProcessor + Enhanced Microarchitecture Processor ®® ProcessorProcessor ItaniumItanium 22 (Deerfield)(Deerfield) (1(1 GHz,GHz, 3MB3MB L3)L3) ProcessorProcessor + Increase in frequency (Deerfield)(Deerfield) + Same platform (1.0GHz,(1.0GHz, 1.5MB1.5MB L3)L3) Performance , RAS, Scalability Performance Performance , RAS, Scalability Performance + Same microarchitecture, approximately half the power + Optimized for density: Dual-Processor rack, blade 2002 2003 2004 2005 2006-Beyond From Itanium®2 processor to Montecito: 2-4X Performance* Source: IIntelntel data, IBM.com, Sun.com OnOn--DieDie CacheCache TrendsTrends • Significantly better latencies for on-die cache • Higher cache bandwidth on-die (48GB/s for Madison)

® 10 Itanium Processor Family

On-Die Cache [MB] 2

2001 2002 2003 2004 On-die Cache = Superior Latency & Bandwidth FutureFuture ItaniumItanium ProcessorProcessor FamilyFamily TechnologiesTechnologies

y Higher frequencies y Larger caches y Lower power implementations y Multi-core technology y Multi-threading y Faster system bus y Additional RAS technologies

Multiple new technologies to exploit Increasing transistor counts AA SimpleSimple ExtrapolationExtrapolation

4 Processor system on a chip, Integrating: • 4 Itanium® 2 processor Cores ~120 M transistors • Shared Cache 16 MB ~900 M transistors • Leaf interconnect

1B Transistors Possible in 65 nm process with < 500 sq mm die size ItaniumItanium® 22 ProcessorProcessor BaselineBaseline

Itanium® 2 Processor Core ~30 M transistors L3 Cache ~65 M transistors per MB

1 Core 2 Cores 4 Cores 3MB Cache ~ 225 M ~ 255 M ~ 315 M 6 MB Cache ~ 420 M ~ 450 M ~ 510 M 9 MB Cache ~ 615 M ~ 645 M ~ 705 M 12 MB Cache ~ 810 M ~ 840 M ~ 900 M 18 MB Cache ~ 1.2 B ~ 1.23 M ~1.3 B

Several paths to 1B Transistors CMPCMP ChallengesChallenges y How much Thread Level Parallelism is there in non-embarassingly parallel workloads? y Ability to generate code with lots of threads & performance scaling y Thread synchronization y Operating systems for parallel machines y Single thread performance y Power limitations y On-chip interconnect infrastructure y Off-chip interconnect infrastructure y Memory and I/O bandwidth required DesignDesign ChallengesChallenges forfor 11 BB TransistorsTransistors

yyDesignDesign ComplexityComplexity – Productivity Tools and Methods Advance – …But at slower rate than Moore’s Law – Replicating cores improves productivity yyVisibilityVisibility forfor TestTest && DebugDebug – Pin Bandwidth/Transistor continues to decline – Shrinking dimensions, increasing speeds, … yyPowerPower – Power Delivery – di/dt of Amps/nano-second – Thermals: Overall power and thermal density Outline

©2002, Intel Corporation Intel, the Intel logo, Pentium, Itanium and Xeon are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries *Other names and brands may be claimed as the property of others SummarySummary y One billion transistors feasible within the next 4 years y Chip Level Multiprocessing and large caches will get us there y Semiconductor technology will continue to drive higher performance y Itanium® 2 processor achieving record results today y Madison extends performance by 30%-50% in 2003 y Innovation for Itanium processor family occurring on multiple vectors – Multi-core Montecito planned for 2005 – Multi-threading – Higher frequencies – larger caches – Faster buses