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Technology & Energy This Unit: Technology & Energy • Technology basis • Fabrication (manufacturing) & cost • Transistors & wires CIS 501: Computer Architecture • Implications of transistor scaling (Moore’s Law) • Energy & power Unit 3: Technology & Energy Slides'developed'by'Milo'Mar0n'&'Amir'Roth'at'the'University'of'Pennsylvania'' with'sources'that'included'University'of'Wisconsin'slides' by'Mark'Hill,'Guri'Sohi,'Jim'Smith,'and'David'Wood' CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 1 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 2 Readings Review: Simple Datapath • MA:FSPTCM • Section 1.1 (technology) + 4 • Section 9.1 (power & energy) Register Data Insn File PC s1 s2 d Mem • Paper Mem • G. Moore, “Cramming More Components onto Integrated Circuits” • How are instruction executed? • Fetch instruction (Program counter into instruction memory) • Read registers • Calculate values (adds, subtracts, address generation, etc.) • Access memory (optional) • Calculate next program counter (PC) • Repeat • Clock period = longest delay through datapath CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 3 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 4 Recall: Processor Performance • Programs consist of simple operations (instructions) • Add two numbers, fetch data value from memory, etc. • Program runtime = “seconds per program” = (instructions/program) * (cycles/instruction) * (seconds/cycle) • Instructions per program: “dynamic instruction count” • Runtime count of instructions executed by the program • Determined by program, compiler, instruction set architecture (ISA) • Cycles per instruction: “CPI” (typical range: 2 to 0.5) • On average, how many cycles does an instruction take to execute? • Determined by program, compiler, ISA, micro-architecture Technology & Fabrication • Seconds per cycle: clock period, length of each cycle • Inverse metric: cycles per second (Hertz) or cycles per ns (Ghz) • Determined by micro-architecture, technology parameters • This unit: transistors & semiconductor technology CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 5 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 6 Semiconductor Technology Transistors and Wires gate gate insulator source drain source drain Substrate channel channel • Basic technology element: MOSFET • Solid-state component acts like electrical switch • MOS: metal-oxide-semiconductor • Conductor, insulator, semi-conductor • FET: field-effect transistor • Channel conducts source→drain only when voltage applied to gate • Channel length: characteristic parameter (short → fast) • Aka “feature size” or “technology” • Currently: 0.022 micron (µm), 22 nanometers (nm) • Continued miniaturization (scaling) known as “Moore’s Law” ©IBM • Won’t last forever, physical limits approaching (or are they?) From slides © Krste Asanović, MIT CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 7 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 8 Manufacturing Steps Intel Pentium M Wafer Source: P&H CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 9 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 10 Manufacturing Steps Manufacturing Defects • Multi-step photo-/electro-chemical process Correct: • Defects can arise • More steps, higher unit cost • Under-/over-doping + Fixed cost mass production ($1 million+ for “mask set”) • Over-/under-dissolved insulator Defective: • Mask mis-alignment • Particle contaminants • Try to minimize defects Defective: • Process margins • Design rules • Minimal transistor size, separation Slow: • Or, tolerate defects • Redundant or “spare” memory cells • Can substantially improve yield CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 11 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 12 Cost Implications of Defects Manufacturing Cost • Chips built in multi-step chemical processes on wafers • Chip cost vs system cost • Cost / wafer is constant, f(wafer size, number of steps) • Cost of memory, storage, display, battery, etc. • Chip (die) cost is related to area • Cost vs price • Larger chips means fewer of them • Relationship complicated; microprocessors not commodities • Cost is more than linear in area • Specialization, compatibility, different cost/performance/power • Why? random defects • Economies of scale • Larger chip, more chance of defect • Unit costs: die manufacturing, testing, packaging, burn-in • Result: lower “yield” (fewer working chips) • Die cost based on area & defect rate (yield) • Package cost related to heat dissipation & number of pins • Fixed costs: design & verification, fab cost • Wafer yield: % wafer that is chips • Amortized over “proliferations”, e.g., Core i3, i5, i7 variants • Die yield: % chips that work • Building new “fab” costs billions of dollars today • Yield is increasingly non-binary - fast vs slow chips • Both getting worse; trend toward “foundry” & “fabless” models CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 13 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 14 A Transistor Analogy: Computing with Air • Use air pressure to encode values • High pressure represents a “1” (blow) • Low pressure represents a “0” (suck) • Valve can allow or disallow the flow of air • Two types of valves N-Valve P-Valve Low (Off) Low (On) Transistor Switching Speed hole High (On) High (Off) CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 15 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 16 Pressure Inverter Pressure Inverter (Low to High) High High P-Valve P-Valve In Out Low High N-Valve N-Valve Low Low CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 17 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 18 Pressure Inverter Pressure Inverter (High to Low) High High P-Valve P-Valve High Low N-Valve N-Valve Low Low CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 19 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 20 Analogy Explained Transistors as Switches • Pressure differential → electrical potential (voltage) • Air molecules → electrons • Two types N-Valve N-MOSFET • Pressure (molecules per volume) → voltage • N-type • High pressure → high voltage • P-type • Low pressure → low voltage • Properties • Air flow → electrical current P-Valve P-MOSFET • Solid state (no moving parts) • Pipes → wires • Reliable (low failure rate) • Air only flows from high to low pressure • Small (45nm channel length) • Electrons only flow from high to low voltage • Fast (<0.1ns switch latency) • Flow only occurs when changing from 1 to 0 or 0 to 1 • Valve → transistor • The transistor: one of the century’s most important inventions CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 21 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 22 Complementary MOS (CMOS) Basic CMOS Logic Gate • Voltages as values • Inverter: NOT gate • One p-transistor, one n-transistor • Power (VDD) = “1”, Ground = “0” power (1) • Basic operation • Two kinds of MOSFETs 0 p-transistor • Input = 0 1 • N-transistors input output • P-transistor closed, n-transistor open • Conduct when gate voltage is 1 (“node”) • Power charges output (1) • Good at passing 0s • Input = 1 n-transistor • P-transistors • P-transistor open, n-transistor closed • Conduct when gate voltage is 0 • Output discharges to ground (0) ground (0) • Good at passing 1s 1 0 • CMOS • Complementary n-/p- networks form boolean logic (i.e., gates) • And some non-gate elements too (important example: RAMs) CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 23 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 24 Another CMOS Gate Example Technology Basis of Transistor Speed • What is this? Look at truth table A B • Physics 101: delay through an electrical component ~ RC • 0, 0 → 1 • Resistance (R) ~ length / cross-section area • Slows rate of charge flow • 0, 1 → 1 output • Capacitance (C) ~ length * area / distance-to-other-plate • 1, 0 → 1 A • Stores charge • 1, 1 → 0 B • Voltage (V) • Result: NAND (NOT AND) • Electrical pressure • NAND is “universal” • Threshold Voltage (Vt) A • Voltage at which a transistor turns “on” • What function is this? • Property of transistor based on fabrication technology B • Switching time ~ to (R * C) / (V – Vt) output • Two kinds of electrical components A B • CMOS transistors (gates, sources, drains) 25 • Wires CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 26 Resistance Capacitance • Channel resistance 1 • Gate capacitance 1 • Wire resistance • Source/drain capacitance • Negligible for short wires 1→0 • Wire capacitance 1→0 • Linear in length for long wires • Negligible for short wires • Linear in length for long wires 1 1 I I 0 1 0 1 1→0 → 1→0 → 1→0 1→0 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 27 CIS 501: Comp. Arch. | Prof. Milo Martin | Technology & Energy 28 Transistor Geometry: Width Transistor Geometry: Length & Scaling Length" Gate Drain Length" Gate Drain Source Source Gate Gate Width Width Source Drain Width" Source Drain Width" Bulk Si Bulk Si Length Length Diagrams © Krste Asanovic, MIT Diagrams © Krste Asanovic, MIT • Transistor width, set by designer for each transistor • Transistor length: characteristic of “process generation” • Wider transistors: • “22nm” refers to the transistor gate length • Lower resistance of channel (increases drive strength) – good! • Each process generation
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