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Lecture 5: Scaled MOSFETS for Ics Lecture 5: Scaled MOSFETS for ICs MSE 6001, Semiconductor Materials Lectures Fall 2006 5 MOSFETS and scaling Silicon is a mediocre semiconductor, and several other semiconductors have better electrical and optical properties. However, the very high quality of the electrical properties of the silicon-silicon dioxide interface allows very good metal-oxide-semiconductor field-effect transistors (MOSFETs) to be fabricated. These devices have several properties, such as operation frequency and power con- sumption, that improve as their size is scaled down to smaller dimensions, which also allows more transistors to be packed onto a chip. The smaller sizes are achieved using higher-resolution pho- tolithography, which is improved by steadily improving the fabrication technologies. The trends of steadily improving performance and greater integration density with time are generically refered to A 70 Mbit SRAM test vehicle with >as0.5 “Moore’s billion trans Law”.istors Of course, scaling has to end eventually, somewhere before the scale of atoms and incorporating all of the features described in this paper has been fabricated on this technologyis. reached.The aggressive de- sign rules allow for a small 0.57Pm2 6-T SRAM cell that is also compatible with high performance logic processing. A top view of the cell after poly patterni5.1ng is show Basicn in Figur MOSFETe 12. In addition to small size, this cell has a robust static noise margin down to 0.7V VDD to alloMOSFETsw low voltage turnopera- on and off via the non-linear gate capacitor between the gate electrode and the tion (Fig. 13). Figure 14 is a Shmosubstrate.o plot for the The 70 M MOSFETb of Fig. 1 controls the flow of electrons (an NMOSFET) from the n-type SRAM operating frequency vs voltage, showing the SRAM operates at 3.43 GHz at 1.2V. A die photsourceo is show electroden in Fig- to the n-type drain electrode. ure 15. A positive gate potential attracts a very thin layer of electrons to the surface of the substrate, VII. Conclusionat its interface with the oxide, forming a “channel” that allows current to be conducted from the We have developed an industry leading 65nm CMOS tech- Figure 2: Transistor size trend for technology nodes. nology for high performance microprocessors with excel- lent transistor and interconnect performance, along with aggressive dimensional scaling. A high performance, high density 70 Mbit SRAM test vehicle has been successfully fabricated utilizing all of the 65nm process features. This 65nm technology is on track for high volume manufactur- ing in 2005. L = 35 nm References [1] K. Mistry, et al., Symp. VLSI Tech. Dig., 2004. [2] T. Ghani, et al., IEDM Tech. Dig., pp. 197-200, 2003. Layer Pitch Thick AspectRatio Transmission electron (nm) (nm) micrograph of MOSFET, Isolation 220 320 - Intel 65 nm process Polysilicon 220 90 - Contacted gate pitch 220 - - Figure 3: TEM cross section of 35nm NMOS Metal 1 210 170 1.6 P. Bai, et al., “65 nm Logic Technology Featuring 35 nm Gate Lengths, Enhanced Metal 2 210 190 1.8 Channel Strain, 8 Cu Interconnect Layers, Low-k ILD, and 0.57 µm2 SRAM Cell”, Metal 3 220 200 1.8 IEDM Proceedings , 2004 Metal 4 280 250 1.8 Metal 5 330 300 1.8 Metal 6 480 430 1.8 FIGURE 1: The MOSFET gate controls the conductivity between the source and drain. Metal 7 720 650 1.8 Metal 8 1080 975 1.8 Table 1: Layer pitch, thickness and aspect ratio 5-1 10 10 ) ) m 2 u SRAM Cell Area ( 250nm m h 0.5x every 2 years u ( c t i 180nm a P e r e A PMOS t 130nm l a 1 1 l e G C d 90nm Figure 4: TEM cross section of 35nm PMOS e t M c A a t 65nm R n Contacted Gate Pitch S o 0.7x every 2 years C 0.1 0.1 1994 1996 1998 2000 2002 2004 2006 Figure 1: Intel contacted gate pitch and SRAM area trends thicknessoftheburiedoxide.Forthickburiedoxide,thereisno backsidescreeningofthedrainpotential,resultinginrelatively poor scaling characteristics compared to other device types [10]–[13]. Since such devices are not likely to be used at the limits of scaling they are not discussed here. We do, however, discuss the scaling advantages of the more novel double gated type of FD-SOI MOSFETs, wherein both the insulator on the back side of the Si channel layer and the Si layer itself are very thin so that both sides of the channel are gated. There are also in-between FD-SOI MOSFETs with buried oxide thin enough to offer some screening, but not thin enough for use in active Fig. 1. Schematic illustration of the scaling of Si technology by a switching. These devices are interesting from a circuit point of factor alpha. Adapted from [5]. view since the back gate can be used to dynamically adjust the thresholdvoltage,butarenotdiscussedhereforlackofspace. Table 1 FIGURE 2: Scaling the size of a MOSFET. The outline of the paper is as follows. Section II ad- Technology Scaling Rules for Three Cases dresses some of the more fundamental limitationssource to drain.the The gate length L is the separation between the source and drain. The smallest continued scaling of MOSFETs that appear featureto be on thatthe can be fabricated in an IC technology is approximated by the “half-pitch width”, which horizon. Based only on these fundamental limits,characterizesit may the IC technology and is a measure of L. For example, this year 65 nm technology be possible to scale FETs down to very smallICsdimensions, have been in full production, and 45 nm technology chips will be introduced. The gate lengths e.g., 10-nm channel length or smaller. SectionforIII thedescribes 65 nm technology is approximately 35 nm. The thin gate oxide, made from silicon dioxide, research results related to this fundamental limit regime: has a thickness tox, which in the current advanced chips is approximately 2 nm thick. very tiny one-of-a-kind FETs. In the more practical world of manufacturing, however, there are many types of variations and fluctuations that require the design of MOSFETs5.2 Scalingwith tolerances. In Section IV, we look at some of theseFigurepractical 2 (Frank, et al., “Device scaling limits of Si MOSFETs and their application dependencies”, limitations and their consequences for deviceProc.design. IEEESec-, 2001) depicts the effects of scaling and Fig. 3 tables the resulting changes in transistor tion V describes how the concepts of the previousand circuitsections properties. play out when they are applied to meeting the Scalingneeds of will be limited by a number of issues. For a very thin gate oxide, less than about 1 specific classes of applications. The paper endsnm,in Section electronsVI can quantum mechanically tunnel directly from the gate electrode to the conducting by summarizing all of the limits into a large table,channel,follo givingwed large leakage currents. For very short channels, electrons can tunnel directly from by the conclusion in Section VII. the source to drain, for L less than about 5 nm. Some of the smallest transistors made to date have L ≈ 6 nm. Doping becomes a problem, because the random distribution of dopant atoms means II. FUNDAMENTAL SCALING LIMITS that different MOSFETs have different numbers of dopants and thus different electrical properties. At the highest doping levels, which can approach 1019 cm−3, the dopant atom spacing is only A. Scaling Theory about 3 nm. The gate metalis the isdimensional also expectedscaling toparameter change., Sinceis the approximatelyelectric field scaling 1980, heavily-doped For many years now, the shrinking of MOSFETspolycrystallinehas been siliconparameter (poly), and has beenand theare preferredseparate dimensional gate “metal”.scaling However,parameters for at oxide thicknesses governed by the ideas of scaling [14], [15]. Thebelowbasic aboutidea is 1.5 nm,the theselecti semiconductingve scaling case. propertiesis applied ofto thethe de polyvice becomevertical dimensions important, manifested as a illustrated in Fig. 1: a large FET is scaled down∼ 1bynma f scaleactor depletionand g layer,ate length, andwhile actual metalsapplies to willthe needdevice towidth be used.and the wiring. to produce a smaller FET with similar behavior. When all of the voltages and dimensions are reduced by the scaling been slow because of the nonscaling of the subthreshold factor and the doping and charge densities 5.3are increased 25 nm MOSFETslope and technologiesthe OFF current. To accommodate this trend, by the same factor, the electric field configurationWithininside a fewthe years,more thegeneralized semiconductorscaling industryrules expectshave been to producecreated, in 25which nm MOSFETs, where, FET remains the same as it was in the originalbyde comparison,vice. This thethe currentelectric Intelfield 65is nmallo technologywed to increase has 35by nma physicalfactor gate[17]. lengths, A generic is called constant field scaling, which results indevicecircuit thatspeed has beenFurthermore, studied is schematicallythe device widths givenand in Fig.wiring 4 (Frank,dimensions et al.).hav Thise IC technology increasing in proportion to the factor and circuit density not been scaled as fast as the channel lengths, leading to increasing as . These scaling relations are shown in the a further scaling parameter for those dimensions. These second column of Table 1 along with the scaling behavior of generalized rules are also sho5-2wn in Table 1 and are described some of the other important physical parameters. in more detail in [5], [9], and [18]. Fig. 2 illustrates the actual past and projected future The preceding scaling rules do not tell a designer how scaling behavior of several of these parameters versus the short he can make a MOSFET for given doping profiles and channel length [16]. As can be seen, the voltages have not layer thicknesses; they only describe how to shrink a known been scaled at the same rate as the length, in violation of the good design.
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