Perspectives of 65nm CMOS technologies for high performance front-end electronics in future applications

G. Traversia, L. Gaionia, M. Manghisonia, L. Rattib, V. Rea

aUniversità degli Studi di Bergamo and INFN Pavia bUniversità degli Studi di Pavia and INFN Pavia

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea Motivations

 Pixelated detectors in cutting-edge scientific experiments at high luminosity particle accelerators and advanced X-ray sources will need to fulfill very stringent requirements on pixel pitch, material budget, readout speed and radiation tolerance  Designers are currently considering two different approaches:  moving to higher density 2D technology nodes  moving to technologies with vertical integration techniques (3D-IC)  The 65nm is starting to be considered as a new attractive solution in view of the development of high-density, high-performance, mixed-signal readout circuits  In the nanometer range, the impact of new dielectric materials and processing techniques (e.g.: silicon strain, gate oxide nitridation) on the analog behavior of MOSFETs has to be carefully evaluated

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 2 65 nm process options

 Several variants of the 65nm process technology are available

 High Speed: highest possible speed at the price o f v e r y h i g h l e a k a g e c u r r e n t ( f o r microprocessors, fast DSP, …). Lower operation voltage (Vdd=1V), low threshold voltage devices  General Purpose: speed is not critical -> leakage current one order of magnitude lower than HS

 Low Power (or Low Leakage): thicker gate oxide Low Moderate Fast thickness, Vdd=1.2V, higher threshold voltage (-50%) (0%) (+50%) devices (for low power applications)

 The characterization results of the 65nm technology shown in this talk are referred to a Low Power option (compared with 90nm LP, 90nm GP and 130nm GP from different foundries)

“SEE and TID. Radiation Test Results on ST Circuits in 65nm CMOS Technologies”, Final Presentation of ESTEC Contract 2006-2007. No. 18799/04/NL/AG, COO-3. January 2009

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 3 Outline

 Analog performance of MOS transistors in 65nm technology  Intrinsic gain  Gate leakage current  Noise performance  Radiation hardness

 Prototype chip with mixed-signal readout circuits in 65nm CMOS  Features of the designed structures  Experimental results

 Collaborative activities under the AIDA WP3.3  Proposed IP blocks

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 4 Intrinsic gain in different CMOS nodes

The intrinsic gain is the maximum gain obtainable from a single transistor

60 g Gain m L 130 nm Foundry B Intrinsic = ∝α 50 90 nm Foundry B gds 65 nm Foundry A  gm channel transconductance 40  gds output conductance

Gain  α scaling factor (for constant field 30 € scaling) NMOS € devices are biased at the same Intrinsic 20 VDS=1.0 V inversion level expressed by the IC =10 inversion coefficient 10 0 ID IC 0 = * 0 IZ ⋅W L 0.05 0.1 0.15 0.2 0.25 * where IZ is the characteristic As-drawn Gate Length [µm] normalized drain current

 Keeping the intrinsic gain constant with scaling is considered€ one of the major challenges in the design of analog circuits in scaled down technologies  The intrinsic gain:  is proportional to the channel length

 is maintained across technology nodes (Lmin scales by the same factor α) 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 5 Intrinsic gain in 65nm node

1000 Weak Moderate Strong As a function of the inversion coefficient: L=700 nm L=500 nm

L=350 nm  The intrinsic gain is maximum in weak inversion L=200 nm where it is independent of the drain current Gain 100  It decreases with the drain current in strong L=130 nm inversion (increases with L but with different Intrinsic L=100 nm slopes for short and long L)

L=65 nm 400 DIBL effects 10 0.001 0.01 0.1 1 10 100 350 dominate on g ds IC0=0.1 Inversion Coefficient 300 65 nm node Weak 250

As a function of the gate length: Gain IC0=1 200  The intrinsic gain is proportional to Moderate 150 the channel length for L close to Lmin Intrinsic 100 IC0=10 (DIBL dominates on gds) Strong

 It shows a reduced slope for L>5Lmin 50 CLM effects dominate on g (CLM effects dominates on g ) ds ds 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 As-drawn Gate Length [µm] The intrinsic gain is larger in weak inversion for long channel devices and is lower in strong inversion for short channel devices 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 6 Gate leakage current

102  The gate current density is used to evaluate the 2 1 1 A/cm impact of the gate oxide thickness reduction on ] 10 2 the static power consumption NMOS A PMOS A 100

[A/cm NMOS B  JG is the IG/WL measured at VDS=0 |V GS|=1.0PMOS V B  I is due to discrete charge randomly crossing a -1 G 10 VDS=V BS=0 potential barrier Density 10-2

-3 Current 10 Foundry B GP devices -4 Gate 10 Foundry A LP devices 10-5 130 90 65 Technology Node [nm]

 Oxynitride gate allows to reduce tunneling effects  The gate current changes between 90nm processes from two different foundries  65nm MOSFETs are in the same region of current density values of 90nm Foundry A and 130nm Foundry B devices  This region is well below the commonly used limit of 1 A/cm2  CMOS scaling beyond 100nm does not necessarily lead to very leaky devices

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 7 Noise in MOS transistors

Noise in the drain current of a MOSFET can be represented through an equivalent noise voltage source in series with the device gate

SW - white noise • channel thermal noise (main contribution in the considered operating conditions)

• kB Boltzmann’s constant D • T absolute temperature • Γ channel thermal noise G coefficient • contributions from parasitic resistances

S1/f - 1/f noise S • technology dependent contribution

• kf 1/f noise parameter

• αf 1/f noise slope-related coefficient

White and 1/f noise have been measured on test devices with different geometries and biased at different drain currents 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 8 White noise

Evaluated in terms of the equivalent channel thermal noise resistance:

• αw excess noise coefficient • n proportional to the reciprocal of the slope of ID(VGS) in subthreshold • γ channel thermal noise coeff.

 aw close to unity for NMOS and PMOS with L > 65 nm  no sizeable short channel effects in the considered operating regions (except for 65 nm devices with aw ≈1.3 )  Negligible contributions from parasitic resistances

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 9 Noise in different CMOS nodes

 NMOSFETs belonging to different CMOS nodes, with the minimum L allowed by each process

 The oxide thickness tOX and the minimum L scale with the same coefficient, the NMOSFETs feature approximately the same value of the gate capacitance

CG=WLCOX

 Devices exhibit a similar 1/f noise => the values of the kf parameter changes little across different CMOS generations

 White noise: devices are biased close to weak inversion => white noise is not sizably affected by L and CMOS node variations even at minimum gate length, as it appears in the high frequency portion of the spectra

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 10 Ionizing radiation effects in sub-100 nm CMOS

The oxide thickness reduction and the substrate doping increase, due to the device scaling in CMOS technologies, improve the radiation hardness of deep submicron MOS transistors. The main degradation effects of devices exposed to ionizing radiation, are associated to the thick lateral isolation oxides (STI = Shallow Trench Isolation)  Radiation induced positive charge is removed from the gate oxide by tunneling (which also prevents the formation of interface states)  Isolation oxides remain thick (order of 100nm) also in nanoscale CMOS, and they are radiation soft  Radiation-induced positive charge trapped in isolation oxides may invert a P-type region in the well/substrate of NMOSFETs creating a leakage path between source and drain  In an interdigitated device this can be modeled considering that two lateral transistors for each finger are turned on  The effect of these parasitic devices on the noise and static characteristic must be carefully evaluated

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 11 Ionizing radiation effects

100 100 NMOS 65 nm NMOS W/L=1000/0.13

W/L = 1000/0.13 ] and 130 nm NMOS W/L=1000/0.35

-2 V =0.6V 1/2 Id=100 µA @ Vds=0.6 V 10 DS

10-4 130 nm

10

-6 10 total ID after irradiation ID before irradiation Drain Current[A] ID,lat 10-8 total ID after irradiation 65 nm, before irradiation 65 nm ID before irradiation 65 nm, 10 Mrad Noise Voltage Spectrum [nV/Hz ID,lat 10 Mrad 130 nm, before irradiation 130 nm, 10 Mrad 10-10 1 -0.2 0 0.2 0.4 0.6 0.8 1 103 104 105 106 107 Gate-to-Source Voltage [V] Frequency [Hz]

 A large amount of lateral leakage takes places in  Noise voltage spectra in the low frequency region 130nm devices are very similar before irradiation (similar gate capacitance)  The smaller ID,lat of 65nm devices suggests that the sensitivity to positive charge buildup in STI  1/f noise increase in the 130 nm device is oxides is mitigated by the higher doping of the P- significantly larger than in the 65 nm one type body with respect to less scaled technology

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 12 Noise in NMOSFETs

100 100 ] ] 1/2 1/2 before irradiation before irradiation 5 Mrad 5 Mrad

10 10

NMOS 65 nm NMOS 65 nm 1 W/L=200/0.50 1 W/L=200/0.50 @ Id=50 A, Vds=0.6 V µ @ Id=500 µA, Vds=0.6 V Noise Voltage Spectrum [nV/Hz Noise Voltage Spectrum [nV/Hz 3 4 5 6 7 8 10 10 10 10 10 10 103 104 105 106 107 108 Frequency [Hz] Frequency [Hz]

 No increase in the white noise region is detected  At higher currents the degradation is barely detectable because the impact of the parasitic lateral devices on the overall drain current is negligible  PMOSFETs (not shown) do not feature any significant change in their static and noise properties after irradiation, following the trend of the most recent CMOS nodes

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 13 Some remarks on the 65nm node

 According to the study of key analog parameters, low-noise analog design in the 65nm CMOS node is viable

 Intrinsic gain is not degraded by scaling

 Gate leakage current is well below the limit of 1 A/cm2

 Channel thermal noise behavior is consistent with equations valid in weak and moderate inversion

 Flicker noise comparison with previous CMOS nodes shows that scaling to the 65nm process does not affect 1/f noise performance significantly

 The comparison with data from previous generations confirms the high degree of radiation tolerance to ionizing radiation that appears to be typical of sub-100 nm technologies

 Data analysis does not point out any novel damage mechanisms which could be related to the technological advances associated to an aggressively scaled process

 We designed a prototype chip with mixed-signal readout circuits in the 65nm IBM CMOS process

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 14 Apsel65: deep n-well monolithic active pixel sensor

 Classical signal processing chain for capacitive detectors  The analog processor includes a charge sensitive amplifier, a shaping stage and a threshold discriminator  binary readout

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 15 Chip description

 Chi Standalone channels

 Cinj = 30fF  Detector simulating cap.

 CD=250fF (CH1)

 CD=350fF (CH2)

 CD=450fF (CH3)  DNW sensor not connected  M1 3x3 matrix  40 µm pixel pitch  all analog outputs accessible

 Cinj = 30fF for central pixel  360 µm2 DNW electrode area  FCi FFE channels   M2 8x8 matrix Cinj = 10fF  Detector simulating cap.  40 µm pixel pitch  C =50fF (FC1)  Row by row, 8-parallel digital readout D  CD=100fF (FC2)  360 µm2 DNW electrode area  CD=150fF (FC3)

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 16 Apsel65: measurements

Measured ENC in good agreement Recovery time increases linearly with with the simulated values the signal amplitude (C2 discharged by Signal amplitude distribution for X- a constant current source) rays from an 55 Fe source Charge sensitivity has an average value (courtesy of S.Bettarini - INFN PI) of 760 mV/fC (725 mV/fC simulated)

 Charge collected by the central pixel as a function of the laser position

 Signal magnitude (normalized with respect to Vpk) is plotted in the z (colour) axis for each position of the laser spot  5 µm step in X and Y (1064nm wavelength)  The layout of the DNW and n-well layers has been superimposed (exact position unknown)

 σxy of the laser ≈ 3 µm  The main purpose of this measurement is to show the relative charge collection versus position (the amount of charge that is deposited has not been calibrated)

L. Gaioni, M. Manghisoni, L. Ratti, V. Re, G. Traversi, “A 65 nm CMOS prototype chip with monolithic pixel sensors and fast front-end electronics”, accepted for publication on IEEE Trans. on Nucl. Sci..

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 17 Fast front-end for high resistivity pixels

 W/L PA input device: 27/0.25  Power consumption: 6 µW - -  ENC = 204 e @ CD = 100 fF (measured: 214 e )  Simulated charge sensitivity: 42 mV/fC (measured: 37 mV/fC)  Peaking time: ~ 25 ns (measured about 25 ns)  Integral non linearity: ~ 3.5 % (32 ke- input dynamic range)

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 18 AIDA (Advanced european Infrastructures for Detectors at Accelerators)

The AIDA project addresses infrastructures required for detector development for future particle physics experiments The infrastructures covered by the AIDA project are key facilities required for an efficient development of the future experiments, such as: test beam infrastructures (at CERN and DESY), specialised irradiation facilities (in several European countries), common software tools, common microelectronic tools and engineering coordination offices 4 year project More than 80 institutions and laboratories from 23 countries 3 main activities:  Networking  WP2: Development of software common tools  WP3: Microelectronics and detector/electronics integration  WP3.1: Coordination and communication  WP3.2: 3D Interconnection  WP3.3: Shareable IP blocks for HEP (65nm CMOS and SiGe)  WP4: Relations with industry  Joint research  WP8: Improvement and equipment of irradiation and test beam lines  WP9: Advanced infrastructure for detector R&D  Transnational access: supports small teams to carry out dedicated activities at one of the 5 European test facilities (DESY, CERN, JSI, KIT, UCL)

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 19 AIDA WP3.3: collaborative activities on 65nm

 WP3.3 task defines the plans for the creation of microelectronic libraries and IP blocks in advanced technologies to be made available to the community of users in HEP

 The choice of the 65nm technology was prompted by the needs of future vertex detectors

 The complexity of advanced microelectronic technologies demands for a critical mass of designers which shares knowledge and designs. This activity allows to exploit synergy in the HEP community

 AIDA WP3.3 members set a common choice of technology option (65nm Low Power) and blocks of general interest to be developed

 CERN is working to provide by Q2 2013 a new frame contract with a foundry

 A common set of radiation characterization steps for the IP blocks has to be defined in order to have a uniform performance of the blocks in the applications

 Some web-pages for documenting activities and results are being prepared allowing collaborative editing

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 20 Proposed IP Blocks

Block Group Standard Cell Library CERN CMOS IO Standard Library PADs CERN LVDS IO PADs Bonn, INFN Pavia, AGH Krakow SLVDS IO PADs Bonn, INFN Pavia, AGH Krakow DAC LAL, CPPM, INFN Pavia SRAM INFN Milano Radiation Hardened Standard Cells INFN Milano, LAPP, CPPM, LPNHE ADC Monitoring LAL, LAPP, CERN Temperature Sensor CPPM, INFN Pavia Bandgap References LAPP, CPPM, INFN Pavia PLL AGH Krakow ADC fast AGH Krakow

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 21 Conclusion and future plans

 Static, signal and noise measurements and radiation tests have been performed on devices belonging to a 65nm CMOS process

 A test chip including deep N-well MAPS has been submitted in a 65nm CMOS process

 Measurement results from this prototype circuit are encouraging and provide useful information for future submissions of larger chips

 The 65nm CMOS technology is considered by designers a new attractive solution for the development of high performance front-end electronics in future applications

 Shareable IP blocks for HEP

 Organization of regular Microelectronics User Group meeting to exchange information, plan and coordinate actions related to the creation of a shared library of IP blocks

 First submission of IP blocks in 65nm CMOS foreseen in 2013

21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 22