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Perspectives of 65Nm CMOS Technologies for High Performance Front-End Electronics in Future Applications

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Perspectives of 65Nm CMOS Technologies for High Performance Front-End Electronics in Future Applications Perspectives of 65nm CMOS technologies for high performance front-end electronics in future applications G. Traversia, L. Gaionia, M. Manghisonia, L. Rattib, V. Rea aUniversità degli Studi di Bergamo and INFN Pavia bUniversità degli Studi di Pavia and INFN Pavia 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea Motivations Pixelated detectors in cutting-edge scientific experiments at high luminosity particle accelerators and advanced X-ray sources will need to fulfill very stringent requirements on pixel pitch, material budget, readout speed and radiation tolerance Designers are currently considering two different approaches: moving to higher density 2D technology nodes moving to technologies with vertical integration techniques (3D-IC) The 65nm is starting to be considered as a new attractive solution in view of the development of high-density, high-performance, mixed-signal readout circuits In the nanometer range, the impact of new dielectric materials and processing techniques (e.g.: silicon strain, gate oxide nitridation) on the analog behavior of MOSFETs has to be carefully evaluated 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 2 65 nm process options Several variants of the 65nm process technology are available High Speed: highest possible speed at the price o f v e r y h i g h l e a k a g e c u r r e n t ( f o r microprocessors, fast DSP, …). Lower operation voltage (Vdd=1V), low threshold voltage devices General Purpose: speed is not critical -> leakage current one order of magnitude lower than HS Low Power (or Low Leakage): thicker gate oxide Low Moderate Fast thickness, Vdd=1.2V, higher threshold voltage (-50%) (0%) (+50%) devices (for low power applications) The characterization results of the 65nm technology shown in this talk are referred to a Low Power option (compared with 90nm LP, 90nm GP and 130nm GP from different foundries) “SEE and TID. Radiation Test Results on ST Circuits in 65nm CMOS Technologies”, Final Presentation of ESTEC Contract 2006-2007. No. 18799/04/NL/AG, COO-3. January 2009 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 3 Outline Analog performance of MOS transistors in 65nm technology Intrinsic gain Gate leakage current Noise performance Radiation hardness Prototype chip with mixed-signal readout circuits in 65nm CMOS Features of the designed structures Experimental results Collaborative activities under the AIDA WP3.3 Proposed IP blocks 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 4 Intrinsic gain in different CMOS nodes The intrinsic gain is the maximum gain obtainable from a single transistor 60 g Gain m L 130 nm Foundry B Intrinsic = ∝α 50 90 nm Foundry B gds 65 nm Foundry A gm channel transconductance 40 gds output conductance Gain α scaling factor (for constant field 30 € scaling) NMOS € devices are biased at the same Intrinsic 20 VDS=1.0 V inversion level expressed by the IC =10 inversion coefficient 10 0 ID IC 0 = * 0 IZ ⋅W L 0.05 0.1 0.15 0.2 0.25 * where IZ is the characteristic As-drawn Gate Length [µm] normalized drain current Keeping the intrinsic gain constant with scaling is considered€ one of the major challenges in the design of analog circuits in scaled down technologies The intrinsic gain: is proportional to the channel length is maintained across technology nodes (Lmin scales by the same factor α) 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 5 Intrinsic gain in 65nm node 1000 Weak Moderate Strong As a function of the inversion coefficient: L=700 nm L=500 nm L=350 nm The intrinsic gain is maximum in weak inversion L=200 nm where it is independent of the drain current Gain 100 It decreases with the drain current in strong L=130 nm inversion (increases with L but with different Intrinsic L=100 nm slopes for short and long L) L=65 nm 400 DIBL effects 10 0.001 0.01 0.1 1 10 100 350 dominate on g ds IC0=0.1 Inversion Coefficient 300 65 nm node Weak 250 As a function of the gate length: Gain IC0=1 200 The intrinsic gain is proportional to Moderate 150 the channel length for L close to Lmin Intrinsic 100 IC0=10 (DIBL dominates on gds) Strong It shows a reduced slope for L>5Lmin 50 CLM effects dominate on g (CLM effects dominates on g ) ds ds 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 As-drawn Gate Length [µm] The intrinsic gain is larger in weak inversion for long channel devices and is lower in strong inversion for short channel devices 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 6 Gate leakage current 102 The gate current density is used to evaluate the 2 1 1 A/cm impact of the gate oxide thickness reduction on ] 10 2 the static power consumption NMOS A PMOS A 100 [A/cm NMOS B JG is the IG/WL measured at VDS=0 |V GS|=1.0PMOS V B I is due to discrete charge randomly crossing a -1 G 10 VDS=V BS=0 potential barrier Density 10-2 -3 Current 10 Foundry B GP devices -4 Gate 10 Foundry A LP devices 10-5 130 90 65 Technology Node [nm] Oxynitride gate allows to reduce tunneling effects The gate current changes between 90nm processes from two different foundries 65nm MOSFETs are in the same region of current density values of 90nm Foundry A and 130nm Foundry B devices This region is well below the commonly used limit of 1 A/cm2 CMOS scaling beyond 100nm does not necessarily lead to very leaky devices 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 7 Noise in MOS transistors Noise in the drain current of a MOSFET can be represented through an equivalent noise voltage source in series with the device gate SW - white noise • channel thermal noise (main contribution in the considered operating conditions) • kB Boltzmann’s constant D • T absolute temperature • Γ channel thermal noise G coefficient • contributions from parasitic resistances S1/f - 1/f noise S • technology dependent contribution • kf 1/f noise parameter • αf 1/f noise slope-related coefficient White and 1/f noise have been measured on test devices with different geometries and biased at different drain currents 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 8 White noise Evaluated in terms of the equivalent channel thermal noise resistance: • αw excess noise coefficient • n proportional to the reciprocal of the slope of ID(VGS) in subthreshold • γ channel thermal noise coeff. aw close to unity for NMOS and PMOS with L > 65 nm no sizeable short channel effects in the considered operating regions (except for 65 nm devices with aw ≈1.3 ) Negligible contributions from parasitic resistances 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 9 Noise in different CMOS nodes NMOSFETs belonging to different CMOS nodes, with the minimum L allowed by each process The oxide thickness tOX and the minimum L scale with the same coefficient, the NMOSFETs feature approximately the same value of the gate capacitance CG=WLCOX Devices exhibit a similar 1/f noise => the values of the kf parameter changes little across different CMOS generations White noise: devices are biased close to weak inversion => white noise is not sizably affected by L and CMOS node variations even at minimum gate length, as it appears in the high frequency portion of the spectra 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 10 Ionizing radiation effects in sub-100 nm CMOS The oxide thickness reduction and the substrate doping increase, due to the device scaling in CMOS technologies, improve the radiation hardness of deep submicron MOS transistors. The main degradation effects of devices exposed to ionizing radiation, are associated to the thick lateral isolation oxides (STI = Shallow Trench Isolation) Radiation induced positive charge is removed from the gate oxide by tunneling (which also prevents the formation of interface states) Isolation oxides remain thick (order of 100nm) also in nanoscale CMOS, and they are radiation soft Radiation-induced positive charge trapped in isolation oxides may invert a P-type region in the well/substrate of NMOSFETs creating a leakage path between source and drain In an interdigitated device this can be modeled considering that two lateral transistors for each finger are turned on The effect of these parasitic devices on the noise and static characteristic must be carefully evaluated 21th International Workshop on Vertex Detectors, 16-21 September, 2012, Jeju, Korea 11 Ionizing radiation effects 100 100 NMOS 65 nm NMOS W/L=1000/0.13 W/L = 1000/0.13 ] and 130 nm NMOS W/L=1000/0.35 -2 V =0.6V 1/2 Id=100 µA @ Vds=0.6 V 10 DS 10-4 130 nm 10 -6 10 total ID after irradiation ID before irradiation Drain Current[A] ID,lat 10-8 total ID after irradiation 65 nm, before irradiation 65 nm ID before irradiation 65 nm, 10 Mrad Noise Voltage Spectrum [nV/Hz ID,lat 10 Mrad 130 nm, before irradiation 130 nm, 10 Mrad 10-10 1 -0.2 0 0.2 0.4 0.6 0.8 1 103 104 105 106 107 Gate-to-Source Voltage [V] Frequency [Hz] A large amount of lateral leakage takes places in Noise voltage spectra in the low frequency region 130nm devices are very similar before irradiation (similar gate capacitance) The smaller ID,lat of 65nm devices suggests that the sensitivity to positive charge buildup in STI 1/f noise increase in the 130 nm device is oxides is mitigated by the higher doping of the P- significantly larger than in the 65 nm one type body with respect
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