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The 4-bit processors Intel 4004 Microprocessor (1970)

 First microprocessor (single-chip IC processor)  Clock rate 740 kHz  0.07 MIPS  Bus width 4 bits (multiplexed address/data due to limited pins)  PMOS  Number of transistors 2,300 at 10 μm  Addressable Memory 640 bytes  Program Memory 4 KB  One of the earliest Commercial Microprocessors  Originally designed to be used in Busicom calculator Intel 4040 Microprocessor (1971)

 4040 – CPU  4 MHz Clock Generator  .185 MHz Clock Generator Crystal for 4004/4201A or 4040/4201A  Introduced 1971 The 8-bit processors 8008 Microprocessor (1972)

 Introduced April 1, 1972  Clock rate 500 kHz (8008–1: 800 kHz)  0.05 MIPS  Bus width 8 bits (multiplexed address/data due to limited pins)  Enhancement load PMOS logic  Number of transistors 3,500 at 10 μm  Addressable memory 16 KB  Typical in early 8-bit microcomputers, dumb terminals, general calculators, bottling machines  Developed in tandem with 4004

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8080 Microprocessor (1974)

 Introduced April 1, 1974  Clock rate 2 MHz (very rare 8080B: 3 MHz)  0.29 MIPS  Bus width 8 bits data, 16 bits address  Enhancement load NMOS logic  Number of transistors 4,500, 6 μm  Assembly language downwards compatible with 8008.  Addressable memory 64 KB  Up to 10X the performance of the 8008  Used in the Altair 8800, Traffic light controller, cruise missile  Required six support chips versus 20 for the 8008 8085 Microprocessor (1976)

 Introduced March 1976  Clock rate 3 MHz  0.37 MIPS  Bus width 8 bits data, 16 bits address  Depletion load NMOS logic  Number of transistors 6,500 at 3 μm  Binary compatible downwards with the 8080.  Used in Toledo scales. Also was used as a computer peripheral controller – modems, hard disks, printers, etc.  CMOS 80C85 in Mars Sojourner, Radio Shack Model 100 portable. The 16-bit processors: MCS-86 family 8086 Microprocessor (1978)

 Introduced June 8, 1978  Clock rates:  5 MHz with 0.33 MIPS[3]  8 MHz with 0.66 MIPS  10 MHz with 0.75 MIPS  The memory is divided into odd and even banks; it accesses both banks concurrently to read 16 bits of data in one clock cycle  Bus width 16 bits data, 20 bits address  Number of transistors 29,000 at 3 μm  Addressable memory 1 megabyte  Up to 10X the performance of 8080 Upendra Sharma 3 Upsharma.in

 First used in the Compaq Deskpro IBM PC-compatible computers. Later used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line).  Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.  The first x86 CPU.  Later renamed the iAPX 86 8088 Microprocessor (1979)

 Introduced June 1, 1979  Clock rates:  4.77 MHz with 0.33 MIPS  8 MHz with 0.66 MIPS[3]  Internal architecture 16 bits  External bus Width 8 bits data, 20 bits address  Number of transistors 29,000 at 3 μm  Addressable memory 1 megabyte  Identical to 8086 except for its 8-bit external bus (hence an 8 instead of a 6 at the end); identical Execution Unit (EU), different Bus Interface Unit (BIU)  Used in IBM PC and PC-XT and compatibles  Later renamed the iAPX 88

80186 Microprocessor (1982)

 Introduced 1982  Clock rates  6 MHz with > 1 MIPS  Number of transistors 55000  Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (these were at fixed addresses which differed from the IBM PC, although it was used by several PC compatible vendors such as Australian company Cleveland).  Address calculation and shift operations are faster than 8086  Used in several non-PC-Compatible MS-DOS computers including RM Nimbus, Tandy 2000, and CP/M 86 Televideo PM16 server  Later renamed the iAPX 186

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80286 Microprocessor (1982)

 Introduced February 2, 1982  Clock rates:  6 MHz with 0.9 MIPS  8 MHz, 10 MHz with 1.5 MIPS  12.5 MHz with 2.66 MIPS  16 MHz, 20 MHz and 25 MHz available.  Bus width: 16 bits data, 24 bits address.  Included memory protection hardware to support multitasking operating systems with per-process address space.  Number of transistors 134,000 at 1.5 μm  Addressable memory 16 MB  Added protected-mode features to 8086 with essentially the same instruction set  3–6X the performance of the 8086  Widely used in IBM-PC AT and AT clones contemporary to it. 32-bit processors: the non-x86 microprocessors IAPX 432 or 80432 Microprocessor(1981)

 Introduced January 1, 1981 as Intel's first 32-bit microprocessor  Multi-chip CPU; Intel's first 32-bit microprocessor  Object/capability architecture  Microcoded operating system primitives  One terabyte virtual address space  Hardware support for fault tolerance  Two-chip General Data Processor (GDP), consists of 43201 and 43202  43203 Interface Processor (IP) interfaces to I/O subsystem  43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems  43205 Memory Control Unit (MCU)  Architecture and execution unit internal data base paths 32 bit  Clock rates:  5 MHz  7 MHz  8 MHz

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80386DX Microprocessor

 Introduced October 17, 1985  Clock rates:  16 MHz with 5 MIPS  20 MHz with 6 to 7 MIPS, introduced February 16, 1987  25 MHz with 7.5 MIPS, introduced April 4, 1988  33 MHz with 9.9 MIPS (9.4 SPECint92 on Compaq/i 16K L2), introduced April 10, 1989  Bus width 32 bits data, 32 bits address  Number of transistors 275,000 at 1 μm  Addressable memory 4 GB  Virtual memory 64 TB  First x86 chip to handle 32-bit data sets  Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required at the time by Xenix and Unix. This memory capability spurred the development and availability of OS/2 and is a fundamental requirement for modern operating systems like Linux, Windows, andOS X.  First used by Compaq in the Deskpro 386. Used in desktop computing  Unlike the DX naming convention of the 486 chips, it had no math co-processor.  Later renamed Intel386 DX 80386SX Microprocessor

 Introduced June 16, 1988  Clock rates:

 16 MHz with 2.5 MIPS  20 MHz with 3.1 MIPS, introduced January 25, 1989  25 MHz with 3.9 MIPS, introduced January 25, 1989  33 MHz with 5.1 MIPS, introduced October 26, 1992

 Internal architecture 32 bits  External data bus width 16 bits  External address bus width 24 bits  Number of transistors 275,000 at 1 μm  Addressable memory 16 MB  Virtual memory 32 GB  Narrower buses enable low-cost 32-bit processing  Used in entry-level desktop and portable computing  No math co-processor Upendra Sharma 6 Upsharma.in

 No commercial software used for protected mode or virtual storage for many years  Later renamed Intel386 SX

80386SL Microprocessor

 Introduced October 15, 1990  Clock rates:

20 MHz with 4.21 MIPS

25 MHz with 5.3 MIPS,

 Internal architecture 32 bits  External bus width 16 bits  Number of transistors 855,000 at 1 μm  Addressable memory 4 GB  Virtual memory 1 TB  First chip specifically made for portable computers because of low power consumption of chip  Highly integrated, includes cache, bus, and memory controllers 80386EX Microprocessor

 Introduced August 1994  Variant of 80386SX intended for embedded systems  On-chip peripherals:  Clock and power management  Timers/counters  Watchdog timer  Serial I/O units (sync and async) and parallel I/O  DMA  RAM refresh  Used aboard several orbiting satellites and microsatellites  Used in NASA's Flight Linux project

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80486DX Microprocessor

 Introduced April 10, 1989  Clock rates:  25 MHz with 20 MIPS  33 MHz with 27 MIPS  50 MHz with 41 MIPS  Bus width 32 bits  Number of transistors 1.2 million at 1 μm; the 50 MHz was at 0.8 μm  Addressable memory 4 GB  Virtual memory 1 TB  Level 1 cache of 8 KB on chip  Math coprocessor on chip  Officially named Intel486 DX  Used in Desktop computing and servers 80486SX Microprocessor

 Introduced April 22, 1991  Clock rates:  16 MHz with 13 MIPS  20 MHz with 16.5 MIPS,  25 MHz with 20 MIPS (33 MHz with 27 MIPS  Bus width 32 bits  Number of transistors 1.185 million at 1 μm and 900,000 at 0.8 μm  Addressable memory 4 GB  Virtual memory 1 TB  Officially named Intel486 SX  Used in low-cost entry to 486 CPU desktop computing, as well as extensively used in low cost mobile computing. 80486DX2 Microprocessor

 Introduced March 3, 1992  Clock rates:  40 MHz  50 MHz  66 MHz

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Pentium Processor (1992)

 Bus width 64 bits  System bus clock rate 60 or 66 MHz  Address bus 32 bits  Addressable Memory 4 GB  Virtual Memory 1 TB  Superscalar architecture  Runs on 3.3 Volts (except the very first generation "P5")  Used in desktops  8 KB of instruction cache  8 KB of data cache Pentium with MMX Technology (1997)

 Introduced January 8, 1997  Intel MMX (instruction set) support  Socket 7 296/321 pin PGA (pin grid array) package  16 KB L1 instruction cache  16 KB L1 data cache  Number of transistors 4.5 million  System bus clock rate 66 MHz  Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8 Pentium Pro

 Introduced November 1, 1995  Precursor to Pentium II and III  Primarily used in server systems  Socket 8 processor package (387 pins) (Dual SPGA)  Number of transistors 5.5 million  Family 6 model 1

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Pentium II Processor

 Introduced May 7, 1997  Pentium Pro with MMX and improved 16-bit performance  242-pin Slot 1 (SEC) processor package  Voltage identification pins  Number of transistors 7.5 million  32 KB L1 cache  512 KB external L2 cache  66 MHz system bus clock rate Pentium III

 Introduced February 26, 1999  Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)  Number of transistors 9.5 million  512 KB L2 External cache  242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package  System Bus clock rate 100 MHz, 133 MHz (B-models)  Slot 1

Pentium 4 Processor

 Introduced November 20, 2000  L2 cache was 256 KB Advanced Transfer Cache (Integrated)  Processor Package Style was PGA423, PGA478  System Bus clock rate 400 MHz  SSE2 SIMD Extensions  Number of transistors 42 million  Used in desktops and entry-level workstations

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64-bit processors: Pentium 4

 Introduced February 20, 2005  Same features as Prescott with the addition of:  2 MB cache  Intel 64-bit  Enhanced Intel SpeedStep Technology (EIST)  L2 cache was 256 KB Advanced Transfer Cache (Integrated)  Processor Package Style was PGA423, PGA478  System Bus clock rate 400 MHz  SSE2 SIMD Extensions  Number of transistors 42 million  Used in desktops and entry-level workstations Pentium Dual-core microprocessor

 Desktop CPU (SMP support restricted to 2 CPUs)  Two cores on one die  Introduced January 21, 2007  SSSE3 SIMD instructions  Number of transistors 167 million  TXT, enhanced security hardware extensions  Execute Disable Bit  EIST (Enhanced Intel SpeedStep Technology) Core i3

 2 physical cores/4 threads  32+32 Kb (per core) L1 cache  256 Kb (per core) L2 cache  3 MB L3 cache  624 million transistors  Introduced January, 2012  Socket 1155 LGA  2-channel DDR3-1333  Variants ending in 'T' have a peak TDP of 35 W, others 65 W  Integrated GPU  Variants

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Core i5

 4 physical cores/4 threads (except for i5-2390T which has 2 physical cores/4 threads)  32+32 Kb (per core) L1 cache  256 Kb (per core) L2 cache  6 MB L3 cache (except for i5-2390T which has 3 MB)  995 million transistors  Introduced January, 2011  Socket 1155 LGA  2-channel DDR3-1333  Variants ending in 'S' have a peak TDP of 65 W, others – 95 W except where noted  Variants ending in 'K' have unlocked multipliers; others cannot be over clocked  Integrated GPU Core i7

 4 physical cores/8 threads  32+32 Kb (per core) L1 cache  256 Kb (per core) L2 cache  8 MB L3 cache  995 million transistors  Introduced January, 2011  Socket 1155 LGA  2-channel DDR3-1333  Variants ending in 'S' have a peak TDP of 65 W, others – 95 W  Variants ending in 'K' have unlocked multipliers; others cannot be overclocked  Integrated GPU