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Intel 4004 Datasheet

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Intel 4004 Datasheet 8n+_I- I. .~ 4004 SINGLE CHIP 4-BIT P-CHANNEL MICROPROCESSOR . 4-Bit Parallel CPU With 46 . CPU Directly Compatible Instructions With MC5-40 ROMs and . Instruction Set Includes RAMs Conditional Branching, . Easy Expansion - One CPU Jump to Subroutine and can Directly Drive up to Indirect Fetching 32,768 Bits of ROM and up . Binary and Decimal to 5120 Bits of RAM Arithmetic Modes . Standard Operating . 10.8 Microsecond T~mper~ture Range of Instruction Cycle 0 to 70 C . Also Available With -400 to +850 C Operating Range The Intel. 4004 is a complete 4-blt parallel central processing unit (CPU) The 4004 easIly Interfaces with keyboardS. swItches, displays, A-O converters. printers and other peripheral equipment The CPU can directly addre. 4K 8-bit instruction words of progrwn memory and 5120 bits of data storage RAM. Sixteen index registers are provided for temporary data storage. Up to 16 4-bit input ports af'd 16 4.bit output ports may also be directly addr818d. The 4004 is fabricated with P-ch8nnelsilicon pie MOS technology. 0. ~ II O'.'CTIo.AI. ft DATA- DATA - ~ -". - I.'ITI '.'.TI INTIRNAl DATA" INTI~ DATA- STACa ~ - ~i~~~~:~ ITIP\. I -I R '..GISTI..-. PROGR-C_TIR .& ".. i LIVtLNO' "" 2 . ,.. ~J ,.~. .. LIVI"~J;;;;;.; "" ... ~r . '- _I. ... STACK I![ ! ..'8' I - 1M I"~ T"'NG KRATCH PAD ~ ~f~ ~. { - .1W - ~ I ~III - oW ~~ ~T~ TIlT Sy~ CL~.sI 1 .1111. r ~ r-'~~f~ ~~ .' ',' '. TOT s~ .'., AIIIT ~~ N In~ CorpOrallOna.-- ~ r8SPCWISI~for DIeuse 01 8IY CRUI1ryo«ner tn8n ~ ;)OOI8G., an Intel product. No 01- arcUIIpaIInt lICenses are ~ InformatIOn ~t8ln8d 1Ier~ ~ ~ ~1t'8cI specificatIOns on DIeM ~ from _rell 1887 ~ ~ CorpOr81lon 1981 Order Number: 231882 4004 Pin Description 00-0, CM-ROM BIDIRECTIONAL DATA BUS.Alladdr..1nd dau CM.ROM output. This is the ROM selectionsignal ~mmuniC8tion betwMn the pr~r and the RAM .m out by the pr-~ when d8ta is r~ir~ and ROM chips occurs on t~ 4 lin... from pr~m memory. RESET CM.AAMQ- CM.AAM3 ,. input. A logic "'" lewf It this input cl88t'S RESET CM.RAM outputs. Ttte. .re the ~ .Iection sig- III fllgllnd Ntus regilt'" Ind forces the prow-m n.ls for the 4002 RAM ~;ps ;n the System. ~unt8l' to Z8'O. To completely clear III address Ind index regilt'", RESETmust be Ipplied for 64 -,- -2 clock cycles (8 mKhine cyclesl. Two pM. clodt inputs. TEST Va TEST input. The togal -8 of this sipl may be MOlt po8tive ~tt8g8. tlltm with the JCN instruction. SYNC Voo V. -15 .t5% m8in .,pply wit8gl. SYNC OUtput. SyndvoniUtion lignel ~WIt8d by the iJf~r and - to the ROM Ind RAM chips. It indic8t8 the beginning of an instruction cycle. 2 4004 Instruction Set Format A. Maine Instructions . 1 word instruction- 8-bits requiring8 clod< periods(instruction cycle). 2 word instruction- 16-bits requiring 16 clock periods (2 instruction cycles). Each instruction is divided into two four-bit fields. The upper 4-bits is the OPR field containing the operation code.The lower 4-bits is the OPA field containingthe modifier. For two word instructions, the second word contains address information or data. The upper 4-bits (OPRI will always be fetched before the lower 4-bits (OPAl during M1 and M2 times respectively. ONE WORD INSTRUCTIONS TWO WORD INSTRUCTIONS I. --,~ cnl.l ~ -~- CYCLI 0, 0, 0, ~ 0, 0, 0, ~ OJ 0, 0, De 0, OJ 0, De 1.1.1.1.1.'.'.'.j 1-'-1-1-'-'-'-'-] DJ DJ D. ~ DJ DJ D. ~ - ~. - - 1-1-1-1-1-1-1-1-1- .. I . I . I - I -. -IS I I _I_I. I ~~._. I ..'.I.!.IA, A, A, A,I I At A, A, A, I A, A, A, A, I 0. I - I .8 I 8.8 I - I ~::~5:::J---.. ~IGISTI- ,. I . I . I . I c. CC*OI'I~c. c. c... ~ ~ ~ ~ ~ OR I 8 I 8 I - I - 17~~~:-':':18_I. IGIST' A'- I I I I . 1 :O-:;:"~I;'~~I.~'GIS". I . ~ ~ ~ ~ "00\1A_I. I .-- ~I. I - ~ ~ . .. L at at A, at I A, a, a, a, I ~ ~ I , I I w I DA'A I 1 . I . I ... I . 17.A~r.:.. ~A;-I.A~'.-'GII1'- ~AI- . I -- OA'A I M'A I .8,8181-10 0 '001 - I °t Dt D. O. I 0, 0, 0, 0, I Table I. ~i,. IMtnlCtion Form8t B. Input/Output and RAM Instructions and Accumulator Group Instructions In these instructions (which are all single word) the CPR contains a 4.bit code which identifies either the I/O instruction or the accumulator group instruction and the CPA contains a 4.bit code which identifies the operation to be performed. Table II illustrates the contents of each 4.bit field. ~o,"~Dto,D, ~ 1-1-1-1-1-1-1-\-) ~ - IWllfIOuT"'" I , I , I , I . I - I - I - I - I .-~.~T~I'I'I'I.I~t~I~I~1 --Af~-I,I,I,I,I_'_I.I.1 l_f.~T~I'I'I'I'I~I~I-I~1 _. IITMI.A""'~ A -,~ T'" II. 110and A-..,Ia.. Group I..tructen F.nwu 3 4004 4004 Instruction Set BASIC INSTRUCTIONS(8 = 2 Word Instructions) ON R OUCRlrTDI OF 0PIMT8 c.- It It 0, De It 0. D,De 00 NOP 0000 0000 NoOO8flt~n Jumpto ROMaddress A, I., A, A,. A, A, A, A. (WIIfIIItile ~ 1 . .JCN a a a 1 c, c. c, C. ROM III. COIItIIIS thIS JCN "SfI~nllf ~t*' C. C. c, c. - A, A. A. A. A. At A. A. IStr... otIWw.. go to till nul .,str~*' 2. -AM 0 0 1 0 R R R 0 FtIdI m~ (~rKt) from ROM Dati 0, 0, 0, 0, O. O. O. O. 01010101 D. O. D. D. 10 ._1 reg..,. ~catal RRR fttcIImrKI from N)M s.Id contl- of Indli reo-- ,. 3 . ~ 0 0 1 1 A A A 0 pp~cat~n klcaal0 out MRu an add,... Oatll8Cllld IS placid !RIa r 3 . JIM 0 0 1 1 A A A 1 Ju~ '"~'ecI SInd conI"'- 01 'evaa. ~ MA out .. 81 ~ II A, 8Id A, I.,. WI u. I".~" cycle 4 . J~ 0' 0 0 A,As As A. JumpunCOfdlGIIIl1O N)M ~ AsA, A, A, A, A, A. A. AsAt As A. A.A. A. A. A.A, A. A.. 5. JMS 0 1 0 1 AsAs A. A, Jump10 S~utMIe N)M ~ A.A, A, A, A, A, A, A, .. .~ A.A.A.As A. A, A.A. A.A.A.A"SIW~lddms(..1~,"tIX*) . ,Nt 0 1 1 0 A A A A 11ICr1rllln1conlin- of reo.., MRA 7 . 0 1 1 1 A A A A IIICr-"-'tCO"'-'ls 01 ,.,.,. MAR Go~ ROMIddrns A, A, A, A, .. SZ AsAs A. As A.A A,A A.A.A.A,(~u.S8'-N)MNcont_s~ISZ,"S1'~1OrI1 . ' -. -.. d mull.. O.0 00~ lilt nut Wlstr~D"WI SlQI*a . ADO '0 0 0 A A A A Add~1nII of rIIlSWMAA ~ KC~1II8r .If! ~'Y . SUI '0 0 1 A A A A S'*rKt CO~.. of ~., MAR m ~, WI" bOrrow A . La 1 0 t 0 A A A A ~ con... of rtOtII8f MAA 10 ~.-- I . D 1 0 1 1 A A A A EICI\InGI cu,*"- 01,"*. I1I8IW AARR 8Id KC~r C . - 1 1 0 ODD D D IrnII bKk (8Mt 1 level WI stK-11IId ~ d*I DOOO ~ Kcum'** D. laM 1 1 0 1 D D D D LOaddati DODO10 ccu".-. Fa ClI 1 1 1 1 0 0 0 0 CIt8'DotII (Accwn.--r andc.ry) F1 CLC 1 1 1 1 0 0 0 1 a.. c.ry F2 I~ 1 1 1 1 0 0 1 0 1~1~",,'--r F3 C* 1111 0011 F5 ML 1 1 1 1 o 1 o 1 ~ left (Acaimw. 8Id ~ry) ~ AM 1 1 1 1 O, 1 0 AOI8 rlQllt (Accu"" aIIdClrry) F7 TCC '" 1 o 1 " Tr--~toCUftU8fIndc-.~ .. OAC '" 1 1 o 0 ° ~ "~ FI TCS 1 1 1 1 1 o o 1 T,... ~ -*at Md c-. ~ . STC - - 1111 1010 $It~ - Fa OM 1111 'O" FC .., 1 1 1 1 1 100 ~.,-. r...1Su.~ott_CIIN"~I. - - - - - - - 0.. outOf ... *' toI ~y ca8 Fa oa. 1111 1101 . 4004 .001/.002/.008/.009/.289 INPUTIOUTPUT ANO RAM INSTRUCTIONS HI. .IEMOMC 0" ON DESCRIPTIO- DF OPE-.. CMe 0,0, D. D. 0, D, D. D. Send '1OIS1,r control Send the Iddress (contents ot tn.. 2 - SAC 0 0 1 0 R R R 1 ',gIst" pal'RRR) to ROMand RAM at x, andX,lmt In'lie Instruct~n cyCle EO WAM 1 1 1 0 0 0 0 0 Wrd, t.,. conttMs 01 tile accumulator Into tilt prhtOuS~ se~. RAM mam mlfftOfy ctlaractlr E 1 WMP 1 1 1 0 0 0 0 1 WrMt Ifte caIM,"ts 01 I" ICwmulitOf 111OI'" prevIOuSly ..ctld RAMOu1put POfI (OutputllftlSI E2 WRR 1 1 1 0 0 0 1 0 Write Ifte cantlIMs 01 tilt Iccumuillor 1"'° Ifte prevD~ ..dld ROM Outtul POIt (I/O lllllSl Wrltt Ifte contents 01 I" accumuillor Into I" pltW1OUSIy..ctld EJ WPM 1 1 1 0 0 0 1 1 IIaWDytl Of rUdlwrlti prOGrammemory tultd wltll 4008/4009 or 42" 011.,1 £4 WAG 1 1 1 0 0 1 0 0 Wr_t I" COfttIfttS 01 Ifte ICCUm~or 1110 I'" pltYlOU$ly st~ RAM stilUS Cftafldtr 0 Write till ~","'I of IlIIlCcumUlator Into 1111prevIOusly SI~~ WA1 E5 1 1 1 0 0 1 0 1 RAM aitul ctllrlCtl' 1 Write 'III contents0' ,~. Iccumuiltor Into 'III prevIOuslyndld E7 -3 1 1 1 0 a t t , RAMslltuS c~lrldef J Reid llIe Pf~~USIy sa_clld RAMma., memoryC""actl' Into ROM E9 1 1 1 0 1 0 0 1 llIe accum.-ator EA ADA 1 1 1 0 1 0 1 0 Ae~ tIle contents01 Iftl preVIOuslySl8C11d AOM ,nout 00f11llto ,.
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