Great Microprocessors of the Past and Present Editor's Note: John's Remote Copy May Be More Up-To-Date
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Arm Cortex-R52
Arm Cortex-R52 Product Brief Benefits Overview 1. Software Separation The Cortex-R52 is the most advanced processor in the Cortex-R family delivering real-time Robust hardware-enforced software performance for functional safety. As the first Armv8-R processor, Cortex-R52 introduces separation provides confidence that support for a hypervisor, simplifying software integration with robust separation to protect software functions can’t interfere with safety-critical code, while maintaining real-time deterministic operation required in high each other. For safety-related tasks, dependable control systems. this can mean less code needs to be certified, saving time, cost and effort. Cortex-R52 addresses a range of applications such as high performance domain controllers for vehicle powertrain and chassis systems or as a safety island providing 2. Multiple OS upportS protection in complex ADAS and Autonomous Drive systems. Virtualization support gives developers flexibility, readily allowing consolidation Safety Ready of applications using multiple operating systems within a single CPU. This eases Arm Cortex-R52 is part of Arm’s Safety Ready portfolio, a collection of Arm IP that the addition of functionality without have been through various and rigorous levels of functional safety systematic flows growing the number of electronic and development. control units. Learn more at www.arm.com/safety 3. Real-Time Performance High-performance multicore clusters of Cortex-R52 CPUs deliver real-time responsiveness for deterministic systems with the lowest Cortex-R latency. 1 Specifications Architecture Armv8-R Arm and Thumb-2. Supports DSP instructions and a configurable Floating-Point Unit either with Instruction Set single-precision or double precision and Neon. -
Atmel SMART | SAM V7: Cortex-M7 Tutorial Using the SAMV7 Xplained ULTRA Evaluation Board ARM Keil MDK 5 Toolkit Summer 2017 V 1.83 [email protected]
Atmel SMART | SAM V7: Cortex-M7 Tutorial Using the SAMV7 Xplained ULTRA evaluation board ARM Keil MDK 5 Toolkit Summer 2017 V 1.83 [email protected] Introduction: The latest version of this document is here: www.keil.com/appnotes/docs/apnt_274.asp The purpose of this lab is to introduce you to the Atmel Cortex®-M7 processor using the ARM® Keil® MDK toolkit featuring the IDE μVision®. We will demonstrate all debugging features available on this processer including Serial Wire Viewer and ETM instruction trace. At the end of this tutorial, you will be able to confidently work with these processors and Keil MDK. We recommend you obtain the new Getting Started MDK 5: from here: www.keil.com/gsg/. Keil Atmel Information Page: See www.keil.com/atmel. Keil MDK supports and has examples for most Atmel ARM processors and boards. Check the Keil Device Database® on www.keil.com/dd2 for the complete list. Additional information is listed in www.keil.com/Atmel/. Linux: Atmel ARM processors running Linux and Android are supported by ARM DS-5™. http://www.arm.com/ds5. Keil MDK-Lite™ is a free evaluation version that limits code size to 32 Kbytes. Nearly all Keil examples will compile within this 32K limit. The addition of a valid license number will turn it into a commercial version. Contact Keil Sales for details. Atmel 8051 Processors: Keil has development tools for many Atmel 8051 processors. See www.keil.com/Atmel/ for details. Atmel | Start: µVision is compatible with the Atmel | START configuration program. -
"Bob" Schreiner
Oral History of Robert “Bob” Schreiner Interviewed by: Stephen Diamond Recorded: June 10, 2013 Mountain View, California CHM Reference number: X6873.2014 © 2013 Computer History Museum Oral History of Robert “Bob” Schreiner Stephen Diamond: We're here at the Computer History Museum with Bob Schreiner. It's June 10th, 2013, and we're going to talk about the oral history of Synertek and the 6502. Welcome, Bob. Thanks for being here. Can you introduce yourself to us? Robert “Bob” Schreiner: Okay. My name is Bob Schreiner. I'm an ex-Fairchilder, one of the Fairchildren in the valley, and then involved in running a couple of other small semiconductor companies, and I started a semiconductor company. Diamond: So that would be Synertek. Schreiner: Synertek. Diamond: Tell us about that. Schreiner: Okay. As you know from an earlier session I left Fairchild Semiconductor around 1971. And at the time I left I was running the LSI program at Fairchild, and I was a big believer that the future marketplace for MOS technology would be in the custom area. And since Fairchild let that whole thing fall apart, I decided there's got to be room for a company to start up to do that very thing, work with big producers of hardware and develop custom chips for them so they would have a propriety product that would be difficult to copy. So I wrote a business plan, and I went around to a number of manufacturers. I had a computer guy [General Automation], and I had Bulova Watch Company, and I had a company that made electronic telephones [American Telephones], and who was the fourth guy? Escapes my memory right now, but the pitch basically was, "Your business, which now you manufacture things with discrete components, it's going to change. -
Configurable RISC-V Softcore Processor for FPGA Implementation
1 Configurable RISC-V softcore processor for FPGA implementation Joao˜ Filipe Monteiro Rodrigues, Instituto Superior Tecnico,´ Universidade de Lisboa Abstract—Over the past years, the processor market has and development of several programming tools. The RISC-V been dominated by proprietary architectures that implement Foundation controls the RISC-V evolution, and its members instruction sets that require licensing and the payment of fees to are responsible for promoting the adoption of RISC-V and receive permission so they can be used. ARM is an example of one of those companies that sell its microarchitectures to participating in the development of the new ISA. In the list of the manufactures so they can implement them into their own members are big companies like Google, NVIDIA, Western products, and it does not allow the use of its instruction set Digital, Samsung, or Qualcomm. (ISA) in other implementations without licensing. The RISC-V The main goal of this work is the development of a RISC- instruction set appeared proposing the hardware and software V softcore processor to be implemented in an FPGA, using development without costs, through the creation of an open- source ISA. This way, it is possible that any project that im- a non-RISC-V core as the base of this architecture. The plements the RISC-V ISA can be made available open-source or proposed solution is focused on solving the problems and even implemented in commercial products. However, the RISC- limitations identified in the other RISC-V cores that were V solutions that have been developed do not present the needed analyzed in this thesis, especially in terms of the adaptability requirements so they can be included in projects, especially the and flexibility, allowing future modifications according to the research projects, because they offer poor documentation, and their performances are not suitable. -
Validated Products List, 1995 No. 3: Programming Languages, Database
NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 QC 100 NIST .056 NO. 5693 1995 NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 (Supersedes April 1995 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary TECHNOLOGY ADMINISTRATION Mary L. Good, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Arati Prabhakar, Director FOREWORD The Validated Products List (VPL) identifies information technology products that have been tested for conformance to Federal Information Processing Standards (FIPS) in accordance with Computer Systems Laboratory (CSL) conformance testing procedures, and have a current validation certificate or registered test report. The VPL also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The VPL includes computer language processors for programming languages COBOL, Fortran, Ada, Pascal, C, M[UMPS], and database language SQL; computer graphic implementations for GKS, COM, PHIGS, and Raster Graphics; operating system implementations for POSIX; Open Systems Interconnection implementations; and computer security implementations for DES, MAC and Key Management. -
UBS Release Notes Version 8.10
Uniplex Release Notes Version 8.10 Manual version: 8.10 Document version: V1.0 COPYRIGHT NOTICE Copyright© 1987-1995 Uniplex Limited. All rights reserved. Unpublished - rights reserved under Copyright Laws. Licensed software and documentation. Use, copy and disclosure restricted by license agreement. ©Copyright 1989-1992, Bitstream Inc. Cambridge, MA. All rights reserved. U.S. Patent No. 5,009,435. ©Copyright 1991-1992, Bitstream Inc. Cambridge, MA. Portions copyright by Data General Corporation (1993) ©Gradient Technologies, Inc. 1991, 1992. ©Hewlett Packard 1988, 1990. Copyright© Harlequin Ltd. 1989, 1990, 1991, 1992. All rights reserved. ©Hewlett-Packard Company 1987-1993. All rights reserved. OpenMail (A.01.00) Copyright© Hewlett-Packard Company 1989, 1990, 1992. Portion Copyright Informix Software, Inc. IXI X.desktop Copyright© 1988-1993, IXI Limited, Cambridge, England. IXI Deskterm Copyright© 1988-1993, IXI Limited, Cambridge, England. Featuring MultiView DeskTerm Copyright© 1990-1992 JSB Computer Systems Ltd. Word for Word, Copyright, Mastersoft, Inc., 1986-1993. Tel: (602)-948-4888 Font Data copyright© The Monotype Corporation Plc 1989. All rights reserved. Copyright© 1990-1991, NBI, Inc. All rights reserved. Created using Netwise SystemTM software. Copyright 1984-1992 Soft-Art, Inc. All rights reserved. Copyrighted work incorporating TypeScalerTM, Copyright© Sun Microsystems Inc. 1989, 1987. All rights reserved. Copyright© VisionWare Ltd. 1989-1992. All Rights Reserved. ©1987-1993 XVT Software Inc. All rights reserved. Uniplex is a trademark of Redwood International Limited in the UK and other countries. onGO, Uniplex II PlusTM, Uniplex Advanced Office SystemTM, Uniplex Advanced GraphicsTM, Uniplex Business SoftwareTM, Uniplex DOSTM, Uniplex DatalinkTM and Uniplex WindowsTM are trademarks of Uniplex Limited. PostScript® is a registered trademark of Adobe Systems Inc. -
Antikernel: a Decentralized Secure Hardware-Software Operating
Antikernel A Decentralized Secure Hardware-Software Operating System Andrew Zonenberg (@azonenberg) Senior Security Consultant, IOActive Bülent Yener Professor, Rensselaer Polytechnic Institute This work is based on Zonenberg’s 2015 doctoral dissertation, advised by Yener. IOActive, Inc. Copyright ©2016. All Rights Reserved. Kernel mode = full access to all state • What OS code needs this level of access? – Memory manager only needs heap metadata – Scheduler only needs run queue – Drivers only need their peripheral – Nothing needs access to state of user-mode apps • No single subsystem that needs access to all state • Any code with ring 0 privs is incompatible with LRP! IOActive, Inc. Copyright ©2016. All Rights Reserved. Monolithic kernel, microkernel, … Huge Huge attack surface Small Better 0 code size - Ring Can we get here? None Monolithic Micro ??? IOActive, Inc. Copyright ©2016. All Rights Reserved. Exokernel (MIT, 1995) • OS abstractions can often hurt performance – You don’t need a full FS to store temporary data on disk • Split protection / segmentation from abstraction Word proc FS Cache Disk driver DHCP server IOActive, Inc. Copyright ©2016. All Rights Reserved. Exokernel (MIT, 1995) • OS does very little: – Divide resources into blocks (CPU time quanta, RAM pages…) – Provide controlled access to them IOActive, Inc. Copyright ©2016. All Rights Reserved. But wait, there’s more… • By removing non-security abstractions from the kernel, we shrink the TCB and thus the attack surface! IOActive, Inc. Copyright ©2016. All Rights Reserved. So what does the kernel have to do? • Well, obviously a few things… – Share CPU time between multiple processes – Allow processes to talk to hardware/drivers – Allow processes to talk to each other – Page-level RAM allocation/access control IOActive, Inc. -
Insider's Guide STM32
The Insider’s Guide To The STM32 ARM®Based Microcontroller An Engineer’s Introduction To The STM32 Series www.hitex.com Published by Hitex (UK) Ltd. ISBN: 0-9549988 8 First Published February 2008 Hitex (UK) Ltd. Sir William Lyons Road University Of Warwick Science Park Coventry, CV4 7EZ United Kingdom Credits Author: Trevor Martin Illustrator: Sarah Latchford Editors: Michael Beach, Alison Wenlock Cover: Wolfgang Fuller Acknowledgements The author would like to thank M a t t Saunders and David Lamb of ST Microelectronics for their assistance in preparing this book. © Hitex (UK) Ltd., 21/04/2008 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical or photocopying, recording or otherwise without the prior written permission of the Publisher. Contents Contents 1. Introduction 4 1.1 So What Is Cortex?..................................................................................... 4 1.2 A Look At The STM32 ................................................................................ 5 1.2.1 Sophistication ............................................................................................. 5 1.2.2 Safety ......................................................................................................... 6 1.2.3 Security ....................................................................................................... 6 1.2.4 Software Development .............................................................................. -
Mali-400 MP: a Scalable GPU for Mobile Devices
Mali-400 MP: A Scalable GPU for Mobile Devices Tom Olson Director, Graphics Research, ARM Outline . ARM and Mobile Graphics . Design Constraints for Mobile GPUs . Mali Architecture Overview . Multicore Scaling in Mali-400 MP . Results 2 About ARM . World’s leading supplier of semiconductor IP . Processor Architectures and Implementations . Related IP: buses, caches, debug & trace, physical IP . Software tools and infrastructure . Business Model . License fees . Per-chip royalties . Graphics at ARM . Acquired Falanx in 2006 . ARM Mali is now the world’s most widely licensed GPU family 3 Challenges for Mobile GPUs . Size . Power . Memory Bandwidth 4 More Challenges . Graphics is going into “anything that has a screen” . Mobile . Navigation . Set Top Box/DTV . Automotive . Video telephony . Cameras . Printers . Huge range of form factors, screen sizes, power budgets, and performance requirements . In some applications, a huge difference between peak and average performance requirements 5 Solution: Scalability . Address a wide variety of performance points and applications with a single IP and a single software stack. Need static scalability to adapt to different peak requirements in different platforms / markets . Need dynamic scalability to reduce power when peak performance isn’t needed 6 Options for Scalability . Fine-grained: Multiple pipes, wide SIMD, etc . Proven approach, efficient and effective . But, adding pipes / lanes is invasive . Hard for IP licensees to do on their own . And, hard to partition to provide dynamic scalability . Coarse-grained: Multicore . Easy for licensees to select desired performance . Putting cores on separate power islands allows dynamic scaling 7 Mali 400-MP Top Level Architecture Asynch Mali-400 MP Top-Level APB Geometry Pixel Processor Pixel Processor Pixel Processor Pixel Processor Processor #1 #2 #3 #4 CLKs MaliMMUs RESETs IRQs IDLEs MaliL2 AXI . -
ARM Architecture
ARM Architecture Comppgzuter Organization and Assembly ygg Languages Yung-Yu Chuang with slides by Peng-Sheng Chen, Ville Pietikainen ARM history • 1983 developed by Acorn computers – To replace 6502 in BBC computers – 4-man VLSI design team – Its simp lic ity comes from the inexper ience team – Match the needs for generalized SoC for reasonable power, performance and die size – The first commercial RISC implemenation • 1990 ARM (Advanced RISC Mac hine ), owned by Acorn, Apple and VLSI ARM Ltd Design and license ARM core design but not fabricate Why ARM? • One of the most licensed and thus widespread processor cores in the world – Used in PDA, cell phones, multimedia players, handheld game console, digital TV and cameras – ARM7: GBA, iPod – ARM9: NDS, PSP, Sony Ericsson, BenQ – ARM11: Apple iPhone, Nokia N93, N800 – 90% of 32-bit embedded RISC processors till 2009 • Used especially in portable devices due to its low power consumption and reasonable performance ARM powered products ARM processors • A simple but powerful design • A whlhole filfamily of didesigns shiharing siilimilar didesign principles and a common instruction set Naming ARM •ARMxyzTDMIEJFS – x: series – y: MMU – z: cache – T: Thumb – D: debugger – M: Multiplier – I: EmbeddedICE (built-in debugger hardware) – E: Enhanced instruction – J: Jazell e (JVM) – F: Floating-point – S: SthiiblSynthesizible version (source code version for EDA tools) Popular ARM architectures •ARM7TDMI – 3 pipe line stages (ft(fetc h/deco de /execu te ) – High code density/low power consumption – One of the most used ARM-version (for low-end systems) – All ARM cores after ARM7TDMI include TDMI even if they do not include TDMI in their labels • ARM9TDMI – Compatible with ARM7 – 5 stages (fe tc h/deco de /execu te /memory /wr ite ) – Separate instruction and data cache •ARM11 ARM family comparison year 1995 1997 1999 2003 ARM is a RISC • RISC: simple but powerful instructions that execute within a single cycle at high clock speed. -
Escuela Politécnica Superior De Jaén
UNIVERSIDAD DE JAÉN ESCUELA POLITÉCNICA SUPERIOR DE JAÉN Trabajo Fin de Grado DATALOGGER CON ENLACE BLUETOOTH A SISTEMA ANDROID Alumno: Juan Miguel Bejarano Bueno Tutor: Prof. D. Luis Miguel Nieto Nieto Dpto: Ingeniería Electrónica y Automática Escuela Politécnica Superior Jaén de Area: Tecnología Electrónica Septiembre, 2015 Juan Miguel Bejarano Bueno Datalogger con enlace Bluetooth a aplicación Android. Universidad de Jaén Escuela Politécnica Superior de Jaén Departamento de Electrónica y Automática Don LUIS MIGUEL NIETO NIETO, tutor del Trabajo Fin de Grado titulado: DATALOGGER CON ENLACE BLUETOOTH A ANDROID, que presenta JUAN MIGUEL BEJARANO BUENO, autoriza su presentación para defensa y evaluación en la Escuela Politécnica Superior de Jaén. Jaén, SEPTIEMBRE de 2015 El alumno: El tutor: JUAN MIGUEL BEJARANO BUENO LUIS MIGUEL NIETO NIETO 1 Escuela Politécnica Superior de Jaén Juan Miguel Bejarano Bueno Datalogger con enlace Bluetooth a aplicación Android. RESUMEN Este Trabajo de Fin de Grado consiste en el desarrollo de dos sistemas. En primer lugar, se dispondrá de un sistema de registro de datos por eventos o datalogger. El sistema está basado en un microcontrolador Microchip y dispondrá de una interfaz de comunicaciones Bluetooth. Este dispositivo será capaz de realizar mediciones con una duración mínima configurable. En segundo lugar y de manera simultánea, se ha diseñado una aplicación Android capaz de gestionar la comunicación con el dispositivo de una manera gráfica. El sistema se ha diseñado siempre teniendo en cuenta el ahorro económico, dispondrá de una alimentación autónoma y el mantenimiento será prácticamente nulo. Se pretende así obtener un datalogger funcional, económico e intuitivo para el manejo del mismo por cualquier tipo de usuario. -
Downloaded to the Test Chip Verified
- -------------------------------------------------------------------------------- - -------------------------------------------------------------------------------- SECURITIES AND EXCHANGE COMMISSION WASHINGTON, D.C. 20549 ------------------------ FORM 10-K ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(D) OF THE SECURITIES EXCHANGE ACT OF 1934 FOR THE FISCAL YEAR ENDED DECEMBER 31, 1997 COMMISSION FILE NUMBER 0-23006 ------------------------ DSP GROUP, INC. (Exact name of registrant as specified in its charter) DELAWARE 94-2683643 (State or other jurisdiction of (I.R.S. Employer Identification No.) incorporation and organization) 3120 SCOTT BOULEVARD, SANTA CLARA, CA 95054 (Address of principal executive offices, including zip code) (408) 986-4300 (Registrant's telephone number) Securities registered pursuant to Section 12(b) of the Act: NONE Securities registered pursuant to Section 12(g) of the Act: COMMON STOCK, $.001 PER SHARE (Title of class) Indicate by check mark whether the Registrant: (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the Registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes /X/ No / / Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of Registrant's knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. [ ] The aggregate market value of the voting stock held by non-affiliates of the Registrant, based on the closing price of the Common Stock on March 2, 1998, as reported on the Nasdaq National Market, was approximately $231,228,988.