DOCSLIB.ORG

Digital Semiconductor Alpha 21064 and Alpha 21064A Microprocessors Hardware Reference Manual

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Digital Semiconductor Alpha 21064 and Alpha 21064A Microprocessors Hardware Reference Manual Digital Semiconductor Alpha 21064 and Alpha 21064A Microprocessors Hardware Reference Manual Order Number: EC–Q9ZUC–TE Abstract: This document contains information about the following Alpha microprocessors: 21064-150, 21064-166, 21064-200, 21064A-200, 21064A-233, 21064A-275, 21064A-275-PC, and 21064A-300. Revision/Update Information: This manual supersedes the Alpha 21064 and Alpha 21064A Microprocessors Hard- ware Reference Manual (EC–Q9ZUB–TE). Digital Equipment Corporation Maynard, Massachusetts June 1996 While Digital believes the information included in this publication is correct as of the date of publication, it is subject to change without notice. Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description. © Digital Equipment Corporation 1996. All rights reserved. Printed in U.S.A. AlphaGeneration, Digital, Digital Semiconductor, OpenVMS, VAX, VAX DOCUMENT, the AlphaGeneration design mark, and the DIGITAL logo are trademarks of Digital Equipment Corporation. Digital Semiconductor is a Digital Equipment Corporation business. GRAFOIL is a registered trademark of Union Carbide Corporation. Windows NT is a trademark of Microsoft Corporation. All other trademarks and registered trademarks are the property of their respective owners. This document was prepared using VAX DOCUMENT Version 2.1. Contents Preface ..................................................... xix 1 Introduction to the 21064/21064A 1.1 Introduction ......................................... 1–1 1.2 The Architecture . ................................... 1–1 1.3 Chip Features ....................................... 1–2 1.4 Backward Compatibility ................................ 1–4 1.5 Section 1.5 21064A-275-PC Differences . ................... 1–4 2 Internal Architecture 2.1 Introduction ......................................... 2–1 2.2 21064/21064A Overview ................................ 2–3 2.3 Ibox ............................................... 2–4 2.3.1 Branch Prediction Logic . ........................... 2–5 2.3.1.1 21064 Branch Prediction Logic . ................... 2–5 2.3.1.2 21064A Branch Prediction Logic ................... 2–5 2.3.1.3 21064/21064A Subroutine Return Stack . .......... 2–6 2.3.2 Instruction Translation Buffers (ITBs) .................. 2–6 2.3.3 Interrupt Logic . ................................... 2–7 2.3.4 Performance Counters . ........................... 2–8 2.4 Ebox ............................................... 2–10 2.5 Abox ............................................... 2–10 2.5.1 Data Translation Buffer (DTB) ....................... 2–10 2.5.2 Bus Interface Unit (BIU) . ........................... 2–12 2.5.3 Load Silos ....................................... 2–12 2.5.4 Write Buffer . ................................... 2–13 2.6 Fbox ............................................... 2–15 2.6.1 Fbox Exception Handling . ........................... 2–16 2.7 IEEE Floating-Point Conformance ........................ 2–19 2.8 Cache Organization ................................... 2–22 iii 2.8.1 21064/21064A Instruction Cache (Icache) ............... 2–22 2.8.1.1 21064 Instruction Cache (Icache) . ................ 2–22 2.8.1.2 21064A Instruction Cache (Icache) . ................ 2–22 2.8.1.3 21064/21064A Icache Stream Buffer ................ 2–22 2.8.2 21064/21064A Data Cache (Dcache) .................... 2–23 2.8.2.1 21064 Data Cache (Dcache) ....................... 2–23 2.8.2.2 21064A Data Cache (Dcache) ...................... 2–23 2.9 Pipeline Organization . ................................ 2–23 2.9.1 Static and Dynamic Stages . ........................ 2–25 2.9.2 Aborts . ........................................ 2–25 2.9.3 Non-Issue Conditions............................... 2–26 2.10 Scheduling and Issuing Rules . ........................ 2–27 2.10.1 Instruction Class Definition . ........................ 2–27 2.10.2 Producer-Consumer Latency . ........................ 2–28 2.10.3 Producer-Producer Latency . ........................ 2–30 2.10.4 Instruction Issue Rules ............................. 2–30 2.10.5 Dual Issue Table . ................................ 2–31 2.11 PALcode ............................................ 2–34 2.11.1 Architecturally Reserved PALcode Instructions ........... 2–34 3 Instruction Set 3.1 Scope .............................................. 3–1 3.1.1 Instruction Summary ............................... 3–1 3.1.2 IEEE Floating-Point Instructions ...................... 3–7 3.1.3 VAX Floating-Point Instructions ...................... 3–9 3.1.4 Required PALcode Function Codes ..................... 3–10 3.1.5 Opcodes Reserved for PALcode ........................ 3–10 3.1.6 Opcodes Reserved for Digital . ........................ 3–10 4 Privileged Architecture Library Code 4.1 Introduction . ........................................ 4–1 4.2 PALcode ............................................ 4–1 4.3 PALmode Environment ................................ 4–2 4.4 Invoking PALcode .................................... 4–3 4.4.1 CALL_PAL Instruction .............................. 4–5 4.5 PALcode Entry Points . ................................ 4–6 4.6 PALmode Restrictions . ................................ 4–9 4.7 Memory Management . ................................ 4–16 4.7.1 TB Miss Flows .................................... 4–16 4.7.1.1 ITB Miss ..................................... 4–16 4.7.1.2 DTB Miss .................................... 4–18 iv 4.8 21064/21064A Implementation of the Architecturally Reserved Opcodes Instructions .................................. 4–19 4.8.1 HW_MFPR and HW_MTPR Instructions ................ 4–20 4.8.2 HW_LD and HW_ST Instructions . ................... 4–23 4.8.3 HW_REI Instruction ............................... 4–24 4.8.4 Required PALcode Instructions ....................... 4–25 5 Internal Processor Registers 5.1 Introduction ......................................... 5–1 5.2 Ibox Internal Processor Registers ......................... 5–1 5.2.1 Translation Buffer Tag Register (TB_TAG) .............. 5–1 5.2.2 Instruction Translation Buffer Page Table Entry Register (ITB_PTE) ....................................... 5–2 5.2.3 Instruction Cache Control and Status Register (ICCSR) . 5–3 5.2.3.1 Performance Counters ........................... 5–6 5.2.4 Instruction Translation Buffer Page Table Entry Temporary Register (ITB_PTE_TEMP) .......................... 5–8 5.2.5 Exceptions Address Register (EXC_ADDR) .............. 5–9 5.2.6 Clear Serial Line Interrupt Register (SL_CLR) . .......... 5–10 5.2.7 Serial Line Receive Register (SL_RCV) ................. 5–11 5.2.8 Instruction Translation Buffer ZAP Register (ITBZAP) . 5–11 5.2.9 Instruction Translation Buffer ASM Register (ITBASM) . 5–12 5.2.10 Instruction Translation Buffer IS Register (ITBIS) ........ 5–12 5.2.11 Processor Status Register (PS) ........................ 5–12 5.2.12 Exception Summary Register (EXC_SUM) ............... 5–12 5.2.13 PAL_BASE Address Register (PAL_BASE) .............. 5–14 5.2.14 Hardware Interrupt Request Register (HIRR) . .......... 5–14 5.2.15 Software Interrupt Request Register (SIRR) . .......... 5–16 5.2.16 Asynchronous Trap Request Register (ASTRR) . .......... 5–17 5.2.17 Hardware Interrupt Enable Register (HIER) . .......... 5–18 5.2.18 Software Interrupt Enable Register (SIER) .............. 5–19 5.2.19 AST Interrupt Enable Register (ASTER) ................ 5–20 5.2.20 Serial Line Transmit Register (SL_XMIT) ............... 5–20 5.3 Abox Internal Processor Registers ........................ 5–21 5.3.1 Translation Buffer Control Register (TB_CTL) . .......... 5–21 5.3.2 Data Translation Buffer Page Table Entry Register (DTB_PTE) ....................................... 5–21 5.3.3 Data Translation Buffer Page Table Entry Temporary Register (DTB_PTE_TEMP) .......................... 5–22 5.3.4 Memory Management Control and Status Register (MM_CSR) ....................................... 5–23 5.3.5 Virtual Address Register (VA) ........................ 5–24 v 5.3.6 Data Translation Buffer ZAP Register (DTBZAP) . ....... 5–24 5.3.7 Data Translation Buffer ASM Register (DTBASM) . ....... 5–24 5.3.8 Data Translation Buffer Invalidate Single Register (DTBIS) . ........................................ 5–24 5.3.9 Flush Instruction Cache Register (FLUSH_IC) ........... 5–24 5.3.10 Flush Instruction Cache ASM Register (FLUSH_IC_ASM) . ................................ 5–24 5.3.11 Abox Control Register (ABOX_CTL) . ................ 5–24 5.3.12 Alternate Processor Mode Register (ALT_MODE) . ....... 5–28 5.3.13 Cycle Counter Register (CC) . ........................ 5–28 5.3.14 Cycle Counter Control Register (CC_CTL) ............... 5–29 5.3.15 Bus Interface Unit Control Register (BIU_CTL) . ....... 5–30 5.3.16 Data Cache Status Register (DC_STAT—21064 Only) ...... 5–35 5.3.17 Cache Status Register (C_STAT, 21064A Only) ........... 5–35 5.3.18 Bus Interface Unit Status Register (BIU_STAT) . ....... 5–36 5.3.19 Bus Interface Unit Address Register (BIU_ADDR) . ....... 5–39 5.3.20 Fill Address Register (FILL_ADDR) .................... 5–40 5.3.21 Fill Syndrome Register (FILL_SYNDROME) ............. 5–41 5.3.22 Backup Cache Tag Register (BC_TAG) . ................ 5–43 5.4 PAL_TEMP Registers . ...............................
Load more

Recommended publications
  • Using the GNU Compiler Collection (GCC)
    Using the GNU Compiler Collection (GCC) Using the GNU Compiler Collection by Richard M. Stallman and the GCC Developer Community Last updated 23 May 2004 for GCC 3.4.6 For GCC Version 3.4.6 Published by: GNU Press Website: www.gnupress.org a division of the General: [email protected] Free Software Foundation Orders: [email protected] 59 Temple Place Suite 330 Tel 617-542-5942 Boston, MA 02111-1307 USA Fax 617-542-2652 Last printed October 2003 for GCC 3.3.1. Printed copies are available for $45 each. Copyright c 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with the Invariant Sections being \GNU General Public License" and \Funding Free Software", the Front-Cover texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in the section entitled \GNU Free Documentation License". (a) The FSF's Front-Cover Text is: A GNU Manual (b) The FSF's Back-Cover Text is: You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development. i Short Contents Introduction ...................................... 1 1 Programming Languages Supported by GCC ............ 3 2 Language Standards Supported by GCC ............... 5 3 GCC Command Options .........................
    [Show full text]
  • 6 Preparing to Port Applications 6.1 Ada
    Porting Applications from HP OpenVMS Alpha to HP OpenVMS Industry Standard 64 for Integrity Servers Order Number: BA442–90001 January 2005 This manual provides a framework for application developers who are migrating applications from HP OpenVMS Alpha to HP OpenVMS Industry Standard 64 for Integrity Servers. Revision/Update Information: This is a new manual. Software Version: OpenVMS I64 Version 8.2 OpenVMS Alpha Version 8.2 Hewlett-Packard Company Palo Alto, California © Copyright 2005 Hewlett-Packard Development Company, L.P. Confidential computer software. Valid license from HP required for possession, use or copying. Consistent with FAR 12.211 and 12.212, Commercial Computer Software, Computer Software Documentation, and Technical Data for Commercial Items are licensed to the U.S. Government under vendor’s standard commercial license. The information contained herein is subject to change without notice. The only warranties for HP products and services are set forth in the express warranty statements accompanying such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall not be liable for technical or editorial errors or omissions contained herein. Intel, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Java is a U.S. trademark of Sun Microsystems, Inc. UNIX is a registered trademark of The Open Group. Printed in the US ZK6673 This document was prepared using DECdocument, Version 3.3-1b. Contents Preface ............................................................ ix 1 Introduction 1.1 OpenVMS Industry Standard 64 for Integrity Servers . ............... 1–1 1.2 Overview of the Porting Process .
    [Show full text]
  • Alpha 21064A Microprocessors Data Sheet
    Alpha 21064A Microprocessors Data Sheet Order Number: EC–QFGKC–TE This document contains information about the following Alpha micro- processors: 21064A–200, 21064A–233, 21064A–275, 21064A–275–PC, and 21064A–300. Revision/Update Information: This document supersedes the Alpha 21064A–233, –275 Microprocessor Data Sheet, EC–QFGKB–TE. Digital Equipment Corporation Maynard, Massachusetts January 1996 While Digital believes the information included in this publication is correct as of the date of publication, it is subject to change without notice. Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description. © Digital Equipment Corporation 1995, 1996. All rights reserved. Printed in U.S.A. AlphaGeneration, Digital, Digital Semiconductor, OpenVMS, VAX, VAX DOCUMENT, the AlphaGeneration design mark, and the DIGITAL logo are trademarks of Digital Equipment Corporation. Digital Semiconductor is a Digital Equipment Corporation business. GRAFOIL is a registered trademark of Union Carbide Corporation. Windows NT is a trademark of Microsoft Corporation. All other trademarks and registered trademarks are the property of their respective owners. This document was prepared using VAX DOCUMENT Version 2.1. Contents 1 Overview ........................................... 1 2 Signal Names and Functions . ........................... 6 3 Instruction Set ....................................... 17 3.1 Instruction Summary ............................... 17 3.2 IEEE Floating-Point Instructions . ................... 23 3.3 21064A IEEE Floating-Point Conformance .............. 25 3.4 VAX Floating-Point Instructions . ................... 28 3.5 Required PALcode Function Codes .
    [Show full text]
  • Design of the RISC-V Instruction Set Architecture
    Design of the RISC-V Instruction Set Architecture Andrew Waterman Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2016-1 http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.html January 3, 2016 Copyright © 2016, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley Committee in charge: Professor David Patterson, Chair Professor Krste Asanovi´c Associate Professor Per-Olof Persson Spring 2016 Design of the RISC-V Instruction Set Architecture Copyright 2016 by Andrew Shell Waterman 1 Abstract Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman Doctor of Philosophy in Computer Science University of California, Berkeley Professor David Patterson, Chair The hardware-software interface, embodied in the instruction set architecture (ISA), is arguably the most important interface in a computer system. Yet, in contrast to nearly all other interfaces in a modern computer system, all commercially popular ISAs are proprietary.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Alpha AXP Firmware Porting Guide Revision/Update Information: Version 1.0
    Alpha AXP Firmware Porting Guide Revision/Update Information: Version 1.0 Order Number: EK-AXFRM-PG. A01 November, 1994 Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description. Reproduction or duplication of this courseware in any form, in whole or in part, is prohibited without the prior written permission of Digital Equipment Corporation. Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid written license from Digital or an authorized sublicensor. © Digital Equipment Corporation 1994. All Rights Reserved. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation: Alpha AXP, AXP, Bookreader, DEC, DECchip, DEC OSF/1, DECwindows, Digital, OpenVMS, VAX, VMS, VMScluster, the DIGITAL logo and the AXP mark. MIPS is a trademark of MIPS Computer Systems, Inc. NCR is a registered trademark of the NCR Corporation. NetWare is a registered trademark of Novell, Inc. OSF/1 is a registered trademark of the Open Software Foundation, Inc. UNIX is a registered trademark in the United States and other countries licensed exclusively through X/Open Company Ltd. Windows NT is a registered trademark of the Microsoft Corporation. All other trademarks and registered trademarks are the property of their respective holders. This document was prepared using VAX DOCUMENT Version 2.1. Contents Preface ............................................................ xiii 1 Porting Strategy Overview .......................................................
    [Show full text]
  • Virtual Memory CS740 October 13, 1998
    Virtual Memory CS740 October 13, 1998 Topics • page tables • TLBs • Alpha 21X64 memory system Levels in a Typical Memory Hierarchy cache virtual memory C 4 Ba 8 B 4 KB CPU c Memory CPU Memory diskdisk regs h regs e register cache memory disk memory reference reference reference reference size: 200 B 32 KB / 4MB 128 MB 20 GB speed: 3 ns 6 ns 100 ns 10 ms $/Mbyte: $256/MB $2/MB $0.10/MB block size: 4 B 8 B 4 KB larger, slower, cheaper – 2 – CS 740 F’98 Virtual Memory Main memory acts as a cache for the secondary storage (disk) Virtual addresses Physical addresses Address translation Disk addresses Increases Program-Accessible Memory • address space of each job larger than physical memory • sum of the memory of many jobs greater than physical memory – 3 – CS 740 F’98 Address Spaces • Virtual and physical address spaces divided into equal-sized blocks – “Pages” (both virtual and physical) • Virtual address space typically larger than physical • Each process has separate virtual address space Physical addresses (PA) Virtual addresses (VA) 0 0 address translation VP 1 PP2 Process 1: VP 2 2n-1 PP7 (Read-only library code) 0 Process 2: VP 1 VP 2 PP10 2n-1 2m-1 – 4 – CS 740 F’98 Other Motivations Simplifies memory management • main reason today • Can have multiple processes resident in physical memory • Their program addresses mapped dynamically – Address 0x100 for process P1 doesn’t collide with address 0x100 for process P2 • Allocate more memory to process as its needs grow Provides Protection • One process can’t interfere with another – Since
    [Show full text]
  • HP Openvms MACRO Compiler Porting and User's Guide
    HP OpenVMS MACRO Compiler Porting and User’s Guide Order Number: AA–PV64E–TE January 2005 This manual describes how to port Macro-32 source code written for the VAX MACRO compiler to the MACRO compiler for OpenVMS running on either an HP OpenVMS Industry Standard 64 or HP OpenVMS Alpha system. It also describes how to use the compiler. Revision/Update Information: This revised manual supersedes the OpenVMS MACRO-32 Porting and User’s Guide for OpenVMS Version 7.3. Software Version: OpenVMS I64 Version 8.2 OpenVMS Alpha Version 8.2 Hewlett-Packard Company Palo Alto, California © Copyright 2005 Hewlett-Packard Development Company, L.P. Confidential computer software. Valid license from HP required for possession, use or copying. Consistent with FAR 12.211 and 12.212, Commercial Computer Software, Computer Software Documentation, and Technical Data for Commercial Items are licensed to the U.S. Government under vendor’s standard commercial license. The information contained herein is subject to change without notice. The only warranties for HP products and services are set forth in the express warranty statements accompanying such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall not be liable for technical or editorial errors or omissions contained herein. Intel and Itanium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Printed in the US ZK5601 The HP OpenVMS documentation set is available on CD-ROM. This document was prepared using DECdocument, Version 3.3-1b. Contents Preface ............................................................ ix Part I Concepts and Methodology 1 Preparing to Port Macro-32 Code 1.1 Features of the MACRO Compiler ..............................
    [Show full text]
  • Address Translation & Caches Outline
    Operating Systems & Memory Systems: Address Translation & Caches CPS 220 Professor Alvin R. Lebeck Fall 2001 Outline • Review • TLBs • Page Table Designs • Interaction of VM and Caches Admin • HW #4 Due today • Project Status report due Thursday © Alvin R. Lebeck 2001 CPS 220 2 Page 1 Virtual Memory: Motivation Virtual • Process = Address Space + thread(s) of Physical control • Address space = PA – programmer controls movement from disk – protection? – relocation? • Linear Address space – larger than physical address space » 32, 64 bits v.s. 28-bit physical (256MB) • Automatic management © Alvin R. Lebeck 2001 CPS 220 3 Virtual Memory • Process = virtual address space + thread(s) of control • Translation – VA -> PA – What physical address does virtual address A map to – Is VA in physical memory? • Protection (access control) – Do you have permission to access it? © Alvin R. Lebeck 2001 CPS 220 4 Page 2 Segmented Virtual Memory • Virtual address (232, 264) to Physical Address mapping (230) • Variable size, base + offset, contiguous in both VA and PA Virtual Physical 0x1000 0x0000 0x1000 0x6000 0x2000 0x9000 0x11000 © Alvin R. Lebeck 2001 CPS 220 5 Paged Virtual Memory • Virtual address (232, 264) to Physical Address mapping (228) – virtual page to physical page frame Virtual page number Offset • Fixed Size units for access control & translation Virtual Physical 0x1000 0x0000 0x1000 0x6000 0x2000 0x9000 0x11000 © Alvin R. Lebeck 2001 CPS 220 6 Page 3 Page Table • Kernel data structure (per process) • Page Table Entry (PTE) – VA -> PA translations (if none page fault) – access rights (Read, Write, Execute, User/Kernel, cached/uncached) – reference, dirty bits • Many designs – Linear, Forward mapped, Inverted, Hashed, Clustered • Design Issues – support for aliasing (multiple VA to single PA) – large virtual address space – time to obtain translation © Alvin R.
    [Show full text]
  • Database Integration
    I DATABASE INTEGRATION ALPHA SERVERS & WORKSTATIONS Digital ALPHA 21164 CPU Technical Journal Editorial The Digital TechnicalJournal is a refereed Cyrix is a trademark of Cyrix Corporation. Jane C. Blake, Managing Editor journal published quarterly by Digital dBASE is a trademark and Paradox is Helen L. Patterson, Editor Equipment Corporation, 30 Porter Road a registered trademark of Borland Kathleen M. Stetson, Editor LJ02/D10, Littleton, Massachusetts 01460. International, Inc. Subscriptionsto the Journal are $40.00 Circulation (non-U.S. $60) for four issues and $75.00 EDA/SQL is a trademark of Information Catherine M. Phillips, Administrator (non-U.S. $115) for eight issues and must Builders, Inc. Dorothea B. Cassady, Secretary be prepaid in U.S. funds. University and Encina is a registered trademark of Transarc college professors and Ph.D. students in Corporation. Production the electrical engineering and computer Excel and Microsoft are registered pde- Terri Autieri, Production Editor science fields receive complimentary sub- marks and Windows and Windows NT are Anne S. Katzeff, Typographer scriptions upon request. Orders, inquiries, trademarks of Microsoft Corporation. Joanne Murphy, Typographer and address changes should be sent to the Peter R Woodbury, Illustrator Digital TechnicalJournal at the published- Hewlett-Packard and HP-UX are registered by address. Inquiries can also be sent elec- trademarks of Hewlett-Packard Company. Advisory Board tronically to [email protected]. Single copies INGRES is a registered trademark of Ingres Samuel H. Fuller, Chairman and back issues are available for $16.00 each Corporation. Richard W. Beane by calling DECdirect at 1-800-DIGITAL Donald Z. Harbert (1-800-344-4825).
    [Show full text]
  • Alpha AXP Architecture by Richard L
    Alpha AXP Architecture By Richard L. Sites 1 Abstract The Alpha AXP 64-bit computer architecture is designed for high performance and longevity. Because of the focus on multiple instruction issue, the architecture does not contain facilities such as branch delay slots, byte writes, and precise arithmetic exceptions. Because of the focus on multiple processors, the architecture does contain a careful shared- memory model, atomic-update primitive instructions, and relaxed read/write ordering. The first implementation of the Alpha AXP architecture is the world's fastest single-chip microprocessor. The DECchip 21064 runs multiple operating systems and runs native-compiled programs that were translated from the VAX and MIPS architectures. Thus in all these cases the Romans did what all wise princes ought to do; namely, not only to look to all present troubles, but also to those in the future, against which they provided with the utmost prudence. - Niccolo Machiavelli, The Prince 2 Historical Context The Alpha AXP architecture grew out of a small task force chartered in 1988 to explore ways to preserve the VAX VMS customer base through the 1990s. This group eventually came to the conclusion that a new reduced instruction set computer (RISC) architecture would be needed before the turn of the century, primarily because 32-bit architectures will run out of address bits. Once we made the decision to pursue a new architecture, we shaped it to do much more than just preserve the VMS customer base. This paper discusses the architecture from a number of points of view. It begins by making the distinction between architecture and implementation.
    [Show full text]
  • Thesis May Never Have Been Completed
    UvA-DARE (Digital Academic Repository) Digital Equipment Corporation (DEC): A case study of indecision, innovation and company failure Goodwin, D.T. Publication date 2016 Document Version Final published version Link to publication Citation for published version (APA): Goodwin, D. T. (2016). Digital Equipment Corporation (DEC): A case study of indecision, innovation and company failure. General rights It is not permitted to download or to forward/distribute the text or part of it without the consent of the author(s) and/or copyright holder(s), other than for strictly personal, individual use, unless the work is under an open content license (like Creative Commons). Disclaimer/Complaints regulations If you believe that digital publication of certain material infringes any of your rights or (privacy) interests, please let the Library know, stating your reasons. In case of a legitimate complaint, the Library will make the material inaccessible and/or remove it from the website. Please Ask the Library: https://uba.uva.nl/en/contact, or a letter to: Library of the University of Amsterdam, Secretariat, Singel 425, 1012 WP Amsterdam, The Netherlands. You will be contacted as soon as possible. UvA-DARE is a service provided by the library of the University of Amsterdam (https://dare.uva.nl) Download date:26 Sep 2021 Digital Equipment Corporation (DEC) (DEC) Corporation Digital Equipment David Thomas David Goodwin Digital Equipment Corporation (DEC): A Case Study of Indecision, Innovation and Company Failure David Thomas Goodwin Digital Equipment Corporation (DEC): A Case Study of Indecision, Innovation and Company Failure David Thomas Goodwin 1 Digital Equipment Corporation (DEC): A Case Study of Indecision, Innovation and Company Failure ACADEMISCH PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Universiteit van Amsterdam op gezag van de Rector Magnificus prof.
    [Show full text]