Computer Systems Architecture Dr Rob Williams

Computer Systems Architecture

Dr Rob Williams

Course text:

"Computer Systems Architecture - a networ king approach" Edition 2 Prentice Hall, 2006 CSA Ch 01

CSA Computers Fetch-execute cycle Hardware CPU Ar ithmetic Logic Unit Control Unit RISC features ARM processor Pentium Itanium Input-output Parallel communication Ser ial communication Networ king Local Area Networ ks Ether net USB Wide Area Networ ks Other Networ ks Point to point Visual output Memor y Memor y hierarchy Cache and main memory Disk ﬁling Parallel processing Software Operating systems Unix MS Windows Tools Compilers and assemblers Subroutines and stacks WIMPs Users’ viewpoints Hardware engineer HLL programmer Systems administrator Systems programmer

Computer Architecture?

h/w s/w Interaction of h/w & s/w

User code myprog.c Software Operating WIN32 API Systems Procedures O/S Ker nel

Hardware CPU Graphics Sound

Layered hierarchyofs/w on a h/w bed

CSA Rob Williams CSA ch 01 - p 3 Pearson Education (c) 2006 8 10 Intel PII NEC 64Mb DRAM 107 Siemens 16Mb DRAM 6 1MbDRAM 10 Motorola 68000 105 256kbbDRAM Number of Intel 8086 104 64kb DRAM transistors 1103 DRAM 103 Intel 4004 102 10 1 1970 1975 1980 1985 1990 1995 2000 Design year 10 Circuit 3µm 2.0µm line 1.0µm width µm 1 0.4µm 0.35µm 0.15µm 0.1 0.1µm?

Moore’sLaw oftechnological progress

ENTITY decoder8 IS PORT (sel: IN std_logic_vector (2 DOWNTO 0); -- select i/p signals sig: out std_logic_vector (7 downto 0)); -- eight o/p signals END decoder8;

ARCHITECTURE rtl OF decoder8 IS BEGIN s<="0000_0001" WHEN (sel = X"0") ELSE "0000_0010" WHEN (sel = X"1") ELSE "0000_0100" WHEN (sel = X"2") ELSE "0000_1000" WHEN (sel = X"3") ELSE "0001_0000" WHEN (sel = X"4") ELSE "0010_0000" WHEN (sel = X"5") ELSE "0100_0000" WHEN (sel = X"6") ELSE "1000_0000"; END rtl;

Moder n h/w development: VHDL

CSA Rob Williams CSA ch 01 - p 4 Pearson Education (c) 2006 2.048Mbps TIC Tr unk Lines to other Switches System Bus Control Computer TDM Voice Bus Line LIC LIC LIC LIC interface Monitor ing cards ter minal

Telephone Switch showing the embedded computer

Windows’ ﬁle browser

The local ATM gives an error message

%cat .cshrc umask 077 limit core 0 setenvTERM vt100 setenvPRINTER lw set prompt = "‘hostname‘ > " set history=25 biff y mesg n alias tt99 ’setenvDISPLAYTT99:0’ set path = ( . /usr/ucb /usr/bin/X11 /bin /usr/bin /usr/local set path = ($path /etc /usr/etc /usr/lang /usr/local $home/bin)

Unix set up script or batch ﬁle

Or iginal sources of the WWW

Domestic Dialup PC modem ISP

Ofﬁce Networ k ISP

National/Inter national Tr unk Line

ISP Sun WWW Ser vice Ser ver Provider

The Internet

100Mbps Ether ATM Ether net Switch Switch Sun

Gateway

Workstations Ser ver

University LAN

8bytes 6bytes 6bytes 46 - 1500 bytes 4bytes Source Preamble Destination Type data payload Error Address Address Check

Ether net packetstr ucture

Williams R, Computer Systems Architecture,Prentice Hall, Tanenbaum A S,"Str uctured Computer Organization", Prentice Hall,

Heur ing &Jordon, "Computer Systems Design and Architecture", Addison Wesley

Hamacher,Vranesic & Zaky,"Computer Organization", McGraw Hill

Patterson & Hennessy,"Computer Organization & Design: The Hardware/Software Interface", Morgan Kaufmann

Buchanan W,"PC Interfacing, Communications & Windows Programming", Addison Wesley

Input Process Output data data

All under programcontrol

0010 0000 0011 1001 Central instr uctions 1101 0000 Processor 0001 0010 Unit 0000 0001 0001 0010 Program 0011 0100 Memor y 1101 0000 1011 1001

Stored programcontrol

Computer Application

Smar t Card Telephone/credit card Microcontroller Washing machine controller Games Console Interactiveenter tainment Home PC Webinfor mation browsing Workstation Design layouts for circuit boards Ofﬁce ServerCentral ﬁling on local networ k Mainframe Corporate Database Supercomputer Flight simulation studies

Common applications of computers

CSA Rob Williams CSA ch 02 - p 10 Pearson Education (c) 2006 from HLL: i=j+k; to assembler mnemonics: mov EAX,[12011234] add EAX,[12011238] mov [1201123C],EAX to machine binary: 0010 0000 0011 1001 Semantic 0001 0010 0000 0001 Gap 0001 0010 0011 0100 1101 0000 1011 1001 0001 0010 0000 0001 0001 0010 0011 1000 0010 0011 1100 0000 0001 0010 0000 0001 0001 0010 0011 1100

HLL, assembler & machine code

1. Data Transfer and Manipulation 2. Input / Output 3. Transfer of ProgramControl 4. Machine Control

Categor ies of machine instructions

Phases of a HLL compiler

Source ﬁles Object Dynamic Macros librar ies librar ies

edit Compile Link Build

RUN

Code sharing at different phases

Mod. 4

Call to Linking code modules Mod. 2 Subroutine

Mod. 3

Command Routines HLL source ﬁle Edit Decode Analysis Select &Execute Tokenised Errors instr uction

Javasource Java ﬁle bytecodes

javac java Edit compiler inter preter

java applet

Netscape browser

HTML text page

Javalanguage interpreters

4096 + 2048 + 1024 + 512 + 128 + 32 + 16 + 8 + 1 = 7865

1111101000 0001100100 0000001010 0000000001 weighting

2 3 9 7

0010 x 1111101000 + 0011 x 0001100100 + 1001 x 0000001010 + 0111 x 0000000001 = 100101011101 Binar y to decimal & decimal to binaryconversion

remainders written from right to left

00000 10001

11111101 wn 20010 ------30011 2)2397 40100 1198 itten do 50101 599 60110 299 70111 81000 results wr 149 91001 74 A1010 37 B1011 18 C1100 9 D1101 4 E1110 2 F1111 1 0 Hex&binar y

CSA Rob Williams CSA ch 02 - p 14 Pearson Education (c) 2006 \bits765 | 000 001 010 011 100 101 110 111 \| bi ts\ de c |0 163248648096112 4321 \ hex|010203040506070 ------| ------0000 0 0 |NUL DLESP0 @ P‘ p 0001 1 1 |SOH DC1 ! 1AQa q 0010 2 2 |STX DC2 " 2BRb r 0011 3 3 |ETX DC3 # 3CSc s 0100 4 4 |EOT DC4 $ 4DTd t 0101 5 5 |ENQ NAK % 5EUe u 0110 6 6 |ACK SYN & 6FVf v 0111 7 7 |BEL ETB ’ 7GWg w 1000 8 8 |BSCAN ( 8HXh x 1001 9 9 |TAB EM) 9 IY iy 1010 10 A| LFSUB * :JZj z 1011 11 B|VTESC + ;K[ k{ 1100 12 C| FFFS, < L\ l | 1101 13 D|CRGS- = M]m} 1110 14 E|SOHOM E .>Nˆ n ˜ 1111 15 F|SI NL/ ? O_ oDE L

NUL Null DLE Data Link Escape SOH StartofHeading DC1 Device Control 1 STX StartofTextDC2 Device Control 2 ETX End of TextDC3 Device Control 3 EOTEnd of transmission DC4 Device Control 4 ENQ EnquiryNAK NegativeAcknowledge ACKAcknowledge SYN Synchronization character BEL Bell ETB End of Transmitted Block BS BackSpace CAN Cancel HT Horizontal Tab EM End of Medium LF Line Feed SUB Substitute VT Ver tical TabESC Escape FF For m Feed FS File Separator CR Carriage ReturnGSGroup Separator SO Shift Out RS Record Separator SI Shift In US Unit Separator SP Space DEL Delete http://www.unicode.org

ASCII code table

char letter;

short count; unsigned int uk_population; long world_population;

float body_weight; double building_weight; long double world_weight; Data types

AIX OS/2 CDOS PICK CICS PRIMOS CMS RSTOS CP/M RSX/11 MSDOS RTL/11 George TDS IDRIS THE ISIS UNIX LY NXOS Ultrix MINIX VERSADOS MOP VM MSDOS VMS MVS MS WINDOWS Multics XENIX OS-9 Linux Operating Systems

1. Command line interpreter (CLI), shell script or desktop selections 2. Function calls from within user programs (API)

Access to O/S facilities

Unix unbuffered, nonblockedkeyboard

#include #include #include #include #define TIMEOUT -1

extern int errno; int sys_nerr; extern char * sys_errlist[];

void setterm(void) { struct termios tty; int status; status = ioctl(0,TCGETS, &tty); tty.c_lflag &= ˜ICANON; tty.c_cc[VTIME] = 0; tty.c_cc[VMIN] = 1; status = ioctl(0,TCSETS, &tty); if ( status == -1 ) { printf("ioctl error \n"); perror(sys_errlist[errno]); exit(); } }

hardware

dr ivers

Onion layered model for Operating Systems

sh -the original Bourne shell, still popular with administrators for scripts csh -the C shell, more C-likesyntax, and is better for interactivesessions tcsh -Tenexshell, perhaps the most used interactiveshell, emacs keying ksh -Kor n shell, normal issue with Hewlett Packard wor kstations bash -bour ne-again-shell, afree-ware rework ofsev eralshells

Unix command shells

Pr int Ser ver File Server

Client-ser ver computing

Client

Request Request Request Message Reply Replies

Ser ver time

Xter m

atar i@pong [50] xterm & atar i@pong [51] rlogin milly-lrwilliam Last login: Tue Jul 1 09:22:21 sister rwilliam@milly >

Computer Computer subsystems

Main I/O CPU Memor y Units

Mouse USB socket MODEM sockets socket LAN Ke yboard Pr inter socket socket Connector

Slots for Sound I/O I/O Expansion Cards ATXPow er Connector

Hard Disk IDE VGA Connectors

Floppydisk Connector

PCI Slots Slots for ChipSet ChipSet Memor y AGPSlot ISA Slot Modules Lithium Batter y + Socket462 BIOS

Cr ystal

Fig 3.2 CPU Fan PC ATX Motherboard, Connector showing the locations of the CPU,memor y and I/O card sockets Pentium CPU Motherboard from a PC and Heatsink

Interr upt Request

System Bus

I/O Subsystem Main Memory

Subsystems joined byabus highway

Bus

Point-to-point vs.bus interconnect schemes

CPU

Control ALU Unit

CPU has twomain component parts

fetch-execute light human reaction 10 ns 300 m/µs300 ms

logic gate delaytvline scan tv frame 5ns60µs20ms

SRAM access interr upt hard disk access 15 ns 2-20 µs10ms

engine sparkcar engine (3000 rpm) 10 µs20ms Comparativespeeds

AX IR System Clock IP

System Bus

MAR

10111000 00000000 00000001

Main Memory

CPU CPU

AX IR AX IR

IP IP ++

Instr uction Instr uction Address Code

Address Data bus bus

MAR MAR

10111000 10111000

00000000 00000000

00000001 00000001

Main Memory Main Memory

The Fetch partofthe Fetch-Execute Cycle

AX IR AX IR

IP IP ++

Data Operand Address Data: 256

MAR MAR

10111000 10111000 00000000 00000000 00000001 00000001

Main Memory Main Memory

The execute partofthe Fetch-Execute Cycle

CPU activity for a Sun wor kstation

CSA Rob Williams CSA ch 03 - p 25 Pearson Education (c) 2006 Data bus -typically 32 bits wide,but will be increased to 64 bits, Address bus -32bits wide,but will require more ver y soon, Control bus -about 15 lines for starting and stopping activities.

System bus has three parts

A B C

System Clock

Addr1 Addr2 Addr3 Address

R/W Read Read Wr ite

Instr Data Result Data

Fetch Execute 10 ns time-base

Timing of synchronous bus activity

R/W Fetch Read Wr ite

Instr Data Result Data

ok ok DTA ok B 10 ns time-base

Timing of asynchronous bus activity

Read Decode Read Execute Wr ite instr uction instr uction operand op result

ASingle Instr uction Cycle

Timing of multi-phase instructions cycle

Rober t

Musical interference on FM receivers

ideal pulse real pulse Clockspeed limitation

Prefetching instructions

fetch 1 execute 1 fetch 2 execute 2 fetch 3 execute 3 fetch 4 execute 4

Winning margin

fetch 1 fetch 2 fetch 3 fetch 4 fetch 5 fetch 6 fetch 7 fetch 8 fetch 9

execute 1 execute 2 execute 3 execute 4 execute 5 execute 6

Time

Over lapped operations gives greater throughput

Address Width

1111 1111 1111 1111 1111 1111 Top

16 memor y MByte length

0000 0000 0000 0000 0000 0000 Bottom

memor y width Address width determines memorylength CSA Rob Williams CSA ch 03 - p 29 Pearson Education (c) 2006 16 bit addresses can access 216,65536, 64K locations 20 bit addresses can access 220,1048576, 1M locations 24 bit addresses can access 224,16777216, 16M locations 32 bit addresses can access 232,4294967296, 4G locations 64 bit addresses can access 264,4398046511104, 4E locations dec 0 12345678910 11 12 13 14 15 bin 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 hex0 1 2 3 4 5 6 7 8 9 ABCD E F

b1[0] Address MemoryContents In Hex b2[0] 0FE032 0102 0304 0506 0708 090A FBFC FDFE FF00 b4[0] 0FE042 0001 0002 0003 0004 0005 00FE 00FF 0100 0FE052 0101 FFFC FFFD FFFE FFFF 0000 0001 0000 0FE062 0002 0000 0003 0000 0004 0000 0005 0000 0FE072 00FE 0000 00FF 0000 0100 0000 0FFF 0000 0FE082 1000 0000 1001 FFFF FFFF 0000 0A00 0000 0FE092 0000 0020 0000 0000 0000 0000 000F E0C0

Intel Pentium

Compare these

Byte ordering: big endian, little endian

unsigned char b1[ ] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 251, 252, 253, 254, 255}; unsigned short b2[ ] = {1, 2, 3, 4, 5, 254, 255, 256, 257, 65532, 65533, 65534, 65535}; unsigned int b4[ ] = {1, 2, 3, 4, 5, 254, 255, 256, 4095, 4096, 4097, 4294967295};

R/W

Address Address bus Decoder Chip Select

Data Bus

R/W

Address Address Decoder bus Chip Select

Parallel data input & output ports

5v 14 13 12 11 10 9 8

1 2 3 4 5 6 7 0v

Inputs C Inputs Inputs Input AB AAND B AB AORB AB AXOR B ANOT A 00 0 00 0 00 0 01 01 0 01 1 01 1 10 10 0 10 1 10 1 11 1 11 1 11 0

A C B AND OR XOR NOT Basic logic gates with truth tables

1 1 1 1 0 1 1 0 1 1 1 0 Detect: 111 Detect: 101 Detect: 010 Using AND for patternrecognition

DX Out D 00 0 Data in 01 0 10 0 11 1 X Off/On control line Data Out

DX Out d0 0 Using AND as a data valve d1 d

X Output Control Y lines Z

O = (AAND Z ) OR (BAND Y ) OR (CAND X ) OR (DAND W )

Data selector,1from 4

Selector Line YX dcba 00 0001 01 0010 10 0100 11 1000

O = (AAND (XAND Y ))OR (BAND (XAND Y ))OR (CAND (XAND Y ))OR (DAND (XAND Y )) 2-to-4 line decoder,1-out-of-4 line selector

A1 a

A2 b Data

Output A3 c

A4 d

a b c d

A B C D

Output A B C D

O1 = (i 3 AND i 2 AND i 1) OR (i 4 AND i 3 AND i 2) OR (i 4 AND i 3 AND i 2 AND i 1) Data multiplexor,1from 4

CSA Rob Williams CSA ch 04 - p 36 Pearson Education (c) 2006 inputs O 1234 i i i i 0000 0 1 2 3 4 0001 0 0010 1 0011 0 0100 0 0101 1 O 0110 0 1 0111 0 1000 0 1001 0 1010 1 1011 0 1100 1 1101 1 1110 0 1111 0

O1 = (i 3•i2•i1) + (i 4•i3•i 2) + (i 4•i 3•i2•i 1) Sum of Products solution

XY NAND 00 1 01 1 10 1 11 0

The 2 input NAND gate

i 2

i 3

i 4

O 1

O 2

O 3

O 4

O 5

O 6

O 7

O 8

Programmable Logic Array (PLA)

CSA Rob Williams CSA ch 04 - p 38 Pearson Education (c) 2006 LevelCrossing Cross Roads Inputs Lights Inputs Lights XYZ RAG rag XY RAG N W-EN-S 000 100 100 00 100 W E W E 01 110 001 110 100 10 001 S 010 001 100 11 010 011 010 100 100 100 100 101 100 110 110 100 001 111 100 010

XY XYZ

R R  A  A   W-E  G G   r  a   R = X  N-S g  A = Y   G = XAND Y

R = (XAND Y ) r = (XAND Y ) A = (XAND Z ) a = (XAND Z ) G = (XAND Y AND Z ) g = (XAND Y AND Z )

Tr afﬁc light controllers

CSA Rob Williams CSA ch 04 - p 39 Pearson Education (c) 2006 Inputs Outputs Enable Select Y G G CBA 01234567 1 2 Y0 Y1 X1 XXX 11111111 3to8 Y2 0X XXX 11111111 A Y3 B line 10 000 01111111 C Y4 10 001 10111111 decoder Y5 10 010 11011111 Y6 10 011 11101111 Y7 10 100 11110111 10 101 11111011 G1 G2 G3 10 110 11111101 10 111 11111110

Y4 A Y5 B Y6

C Y7

3to8line decoder

CSA Rob Williams CSA ch 04 - p 40 Pearson Education (c) 2006 a Inputs LEDs WXYZ abcdefg 0000 1111110 f b 0001 0110000 g 0010 1101101 0011 1111001 0100 0110011 e c 0101 1011011 d 0110 0011111 0111 1110000 1000 1111111 1001 1111011

a = (WAND XAND YAND Z ) OR (WAND X AND YAND Z ) OR (WAND X AND Y AND Z ) b = (WAND X AND YAND Z ) OR (WAND X AND Y AND Z )

c = WAND XAND Y AND Z

d = (WAND XAND YAND Z ) OR (WAND X AND YAND Z ) OR (WAND X AND Y AND Z ) e = (WAND XAND YAND Z ) OR (WAND XAND Y AND Z ) OR (WAND X AND Y AND Z ) OR (WAND XAND YAND Z ) f = (WAND XAND YAND Z ) OR (WAND XAND Y AND Z ) OR (WAND XAND Y AND Z ) OR (WAND X AND Y AND Z ) g = (WAND XAND YAND Z ) OR (WAND XAND YAND Z ) OR (WAND X AND Y AND Z )

ZYXW

SPIN FILL

DRAIN HEAT

RINSE WASH

DRAIN

1 2 1 1000 1 rev per hr → 2rph → rps → Hz → mHz → 0. 55mHz 2 3600 1800 1800

Washing machine Finite State Diagram(FSD)

micro-switch 1 micro-switch 2

Micro Control Lines Valve Heat Motor Pump switch 0 1 1 0 Open On FS On 000 READY 00000 0 1 001 FILL 10000 1 0 010 HEAT 01000 0.55 mHz 011 WASH 00010 100 DRAIN 00001 101 RINSE 10010 110 DRAIN 00001 111 SPIN 00101

Washing machine sequence controller (FSM)

CSA Rob Williams CSA ch 04 - p 43 Pearson Education (c) 2006 Control Store 111 00101 110 00001 101 10010 5bit 100 00001 control word 011 00010 ProgramCounter 010 01000 001 10000 Valve Heat FSPump 3bit code 000 00000 Open On Motor On from micro-switches Control Lines

Control JMP ﬂag Store addr select 111 00101 000 00 110 00001 000 00 101 10010 000 00 100 00001 000 00 011 00010 000 00 010 01000 000 00 001 10000 000 00 Counter 000 00000 000 00 Clock

Reset decoder JMP addr

JMP load temperature

water levelhigh

water levellow

Washing machine controller with conditional branching

Instr uction Register

Addr Gen Pre-Decode

Status Control Bits Binar y Decoder Logic Counter Gate Array Condn System Clock 000 00001 Flags 001 00010 00100 reset 010 011 01000 10000

dedicated control signals

Hardware logic Control Unit (RISC)

Condn Address Binar y Flags Generator System Clock Counter Logic 000 001 010 011 Microaddr Reg

reset Control Store PROM

Micro IR

dedicated control signals

Microcoded Control Unit (CISC)

(XAND Y ) ≡ (XORY ) ≡

(XORY)≡(XAND Y ) ≡

while ( ! dog && ! cat ) {plant_flowers( ) ;}

while (! (dog || cat )) {plant_flowers( ) ;} De Morgan’sequivalences

ADD Carr y XY CS 00 00 01 01 Sum 10 01 11 10

Carr y

Sum

Alter nativeHalf Adder (2 inputs) circuits

Carr y

Sum

X Y

Carr y

Sum

More Half Adder circuits

XYZ CS 000 00 X 001 01 1/2 C Carr y Y Adder 1 010 01 1/2 C 011 10 Z Adder 2 Sum 100 01 Full-adder 101 10 110 10 111 11

Full Adder (3 inputs) circuit

3210 3210

C in Add0

Add1

Add2

C=A+B Add3

C out S3 S2 S1 S0

4bit parallel adder circuit

0011 +3 e Negativeintegers using 0010 +2 Tw osCompliment for mat

0001 +1 positiv 0000 0 1111 -1 negativ 1110 -2 To for m atwo’s compliment negative: 1101 -3 Take the positivenumber, e 1100 -4 invert all the bits, 1011 -5 add 1. 1010 -6 1001 -7 1000 -8

31 0 31 0 A B

1-subtract 0-add 31 • • •••0

Carr y in IR 32 bit ALU control lines (Parallel CU Adder) C

31 0

ALU with positiveand negativecapability

x ...... x 7 0 Output Input, x Input, x Input, x x ..... x x ...... x x ..... x 7 0 7 0 7 0

x .....x 0 x ...x 00 000x ..x 6 0 5 0 7 3 Output, x <<= 1 Output, x <<= 2 Output, x >>= 3

Input, x Input, x x ..... x x ..... x 7 0 7 0

x x x x 2107654 3 4321076 5 Output, ROL x,5 Output, ROR x,5

Barrel Shifter circuit for Shifts & Rotates

CSA Rob Williams CSA ch 05 - p 52 Pearson Education (c) 2006 173 10101101 57x 00111001x ------1211 10101101 8650 00000000 ------0 0000000 9861 10101101 10101101 10101101 00000000 00000000 ------1001101000001

Integer multiplication byShift and Add

/* function to multiply two 16 bit positive integers returning a 32 bit result, using only integer addition and shift operators */

int multiply(int a, int c) { int i;

c=c<<16;

for (i=0; i<16; i++) { if (a & 1) { a += c }; a=a>>1; } return a;

00010110 10011100 00010110 10011100 00001011 01001110

00101101 Test LS bit 00101101 00101101 0 shift right

00001011 01001110 00001011 01001110 00000101 10100111

00101101 Test LS bit 00101101 00101101 0 shift right

00000101 10100111 00110010 10100111 00011001 01010011 A+=C 00101101 if (A & 1) 00101101 00101101 1 A=A>>1

00011001 01010011 01000 110 01010011 00100011 00101001 + 00101101 Test LS bit 00101101 00101101 1 shift right

00100011 00101001 01010000 00101001 00101000 00010100 + 00101101 Test LS bit 00101101 00101101 1 shift right

00010100 00001010 00001011 01001110 00000101 10100111

00101101 Test LS bit 00101101 00101101 0 shift right Result 00010100 00001010 00010100 00001010 00001010 00000101

00101101 Test LS bit 00101101 00101101 0 shift right

8x8multiply using two16bit registers

Inter nal CPU Data Bus

A B

Carr y in

control lines ALU CU

CPU Flags C

ALU with data registers

S3 - S0 M=1 M=0

Logic Arithmetic

Cin =0 Cin =1

0000 F =AF=AF=A+1

0001 F =AORB F=AORB F=(AORB)+1

0010 F =AAND B F = BORA F=(AORA)+1

0011 F =0 F =−1 F=0

0100 F =AAND B F = A + (BAND A) F = A + (BAND A) + 1

0101 F =BF=(AORB)+(BAND A) F = (AORB)+(BAND A) + 1

0110 F =AXOR B F = A − B − 1 F = A − B

0111 F =BAND A F = BAND A − 1 F = (B + A)

1000 F =AORB F=A+(BAND B) F = A + (AAND B) + 1

1001 F =AXOR B F = A + BF=A+B+1

1010 F =BF=(BORA)+(AAND B) F = (BORA)+(AAND B) + 1 1011 F =AAND B F = (AAND B) − 1 F = (AAND B) 1100 F =1 F =A<< 1 F = ( A << 1 ) + 1

1101 F =BORA F=(AORB)+AF=(AORB)+A+1

1110 F =AORB F=A+(BORA)+AF=(BORA)+A+1 1111 F =AF=A−1 F=A

Data in Data out

A0 F0 A1 F1 A2 F2 A3 F3 74xx181 B0 C B1 out B2 B3 A=B C in

S3S2S1S0 M Control

Example integer ALU component

Floats & integers in HLL programming

1234.5625 10011010010.1001 1.00110100101001 x 21010 unnor malized normalized for mat

-3.3125 -11.0101 -1.10101 x 21

0.065625 0.00011 1.1 x 2-4

Floating-point numbers,inIEEE 754 32 bit for mat, appear in memoryas:

31 30 23 22 0

S exponent mantissa

0 10001001 00110100101001000000000

1 10000000 10101000000000000000000

0 01111011 10000000000000000000000

To manually converting a decimal ﬂoat into a IEEE binaryﬂoat:

1. Convert the integer partinto binary. 2. Convert the fractional partinto binary, noting the 1/2, 1/4, 1/8, 1/16 pattern!

... 128 64 32 16 8 4 2 1 • 0.5 0.25 0.125 0.0625 0.03125 ...

3. Normalizebymoving the binarypoint to produce the for mat: 1.something with apositiveornegativeshift number. 4. Delete the leading 1, and extend the left bits with 0s to givea23bit mantissa. 5. Add 127 to the shift number to givethe 8 bit exponent. CSA Rob Williams CSA ch 05 - p 58 Pearson Education (c) 2006 /* floatit.c - to write a real number into a file for viewing */

#include

int main( ) { FILE *fp; float f = 231.125; if (fp = fopen ("float_data", "w")) { fwrite(&f, 4, 1, fp); }; return 0; }

rob@olveston [78] cc floatit.c -o floatit rob@olveston [79] floatit rob@olveston [80] od -x float_data 0000000 4367 2000 0000004 rob@olveston [129] od -f float_data 0000000 2.3112500e+02 0000004 rob@olveston [130]

0100 0011 0110 0111 0010 0000 0000 0000 || | sign 8 bit 23 bits of the 24bit bit exponent mantissa in 127 offset format

The range and precision of the var ious ﬂoating-point for mats are as follows:

Range Precision 32 bit 8bit 24 bit, (1 in 16 x 106)

64 bit 11 bit 53 bit, (1 in 8 x 1015)

128 bit 15 bit 64 bit, (1 in 16 x 1018)

1bit data in 1 0 Stored data out 1 1bit data out 0 Wr ite-once,Read-manymemor y cell

Q S R Q Q S _ t t t t+1 t+1 Q 000 1 0 001 1 0 010 0 1 Q 011 illegal R 100 0 1 101 1 0 110 0 1 111 illegal

_ S Q S S-R Latch R Q R

Q _ Q

S-R Latch, 1 bit static memory

10 kOhm 200 Ohm Cat ﬂap swipe switch LED

OUT IN

Cat IN-OUT indicator using an S-R latch

RAM 10ns DRAM, Dynamic Random Access Memory-read & write,random access 1ns SRAM, Static Random Access Memory ROMRead Only Memory, factor y wr itten -random access PROM Programmable ROM, writable,but only once. EPROM 150ns UV erasable PROM, with a windowinthe package to admit the UV photons EEPROM electrically erasable PROM, useful for semi-permanent programming FLASH similar to EEPROM, reprogrammable,non-volatile ROM

3v D0 3v D1 0 D2 3v D3 0 3v WE CAS RAS CS B0 B1 A10 A0 A1 A2 A3 3v 5v A14 A13 A0 A9 A1 OE A10 CS D7 D6 D5 D4 D3

MT46V128M8TG-6T M5L27512K-2

A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 Gnd D7 0 D6 3v D5 0 D4 3v 0DQClk CkeA11 A9 A8 A7 A6 A5 A4 0

Mitsubishi, M5L27512K-2 Micron, MT46V128M8TG-6T 64 kbytes EPROM 128 Mbyte Dynamic RAM 200 nsec access time 167 MHz operation, 6 ns access Different types of memory

Clock f

f/2

f/4

f/8

Flip-ﬂops used for frequency division

Tr ansistor switch

1bit storage capacitor ~20fF Bit line

CAS RAS Wr ite Enable Bit line drivers

Row Address Address latch 64Mbit w Memor y Cell Ro array decoder

Multiplexor

Column decoder

31 0 Address

15 015 0 Rownumber Column number

RAS cycle CAS cycle

RowAccess RAS Column Access CAS Row C0 C1 C2 C3 Addr

D0 D1 D2 D3 Data

64 MByte,100 MHz clock, 64 bit, 168 pin DIMM card

72 pin SIMM and 168 pin DIMM, DRAM Modules

22 Remember : 220 =1M, so: 2 =4M

CSA Rob Williams CSA ch 06 - p 66 Pearson Education (c) 2006 1Vss 43 Vss 85 Vss 127 Vss 2DQO 44 NC 86 DQ32 128 CKEO 3DQ1 45 CS287DQ33 129 NC 4D02 46 DQM2 88 DQ34 130 DQM6 5DQ3 47 DQM3 89 DQ35 131 DQM7 6Vcc 48 NC 90 Vcc 132 NC 7DQ4 49 Vcc 91 DQ36 133 Vcc 8DQ5 50 NC 92 DQ37 134 NC 9DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 NC 94 DQ39 136 NC 11 DQ8 53 NC 95 DQ40 137 NC 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 D012 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 Vcc 101 DQ45 143 Vcc 18 VCC 60 DQ20 102 Vcc 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 NC 104 DQ47 146 NC 21 NC 63 NC 105 NC 147 NC 22 NC 64 Vss 106 NC 148 Vss 23 Vss 65 DQ21 107 VSS 149 DQ53 24 NC 66 DQ22 108 NC 150 D054 25 NC 67 D023 109 NC 151 DQ55 26 Vcc 68 Vss 110 VCC 152 Vss 27 WE 69 DQ24 111CAS 153 DQ56 28 DQM0 70 DQ25 112 DQM4 154 DQ57 29 DQM1 71 DQ26 113 DQM5 155 DQ58 30 CSO 72 DQ27 114 NC 156 D059 31 NC 73 Vcc 115RAS 157 Vcc 32 Vss 74 DQ28 116 VSS 158 DQ60 33 AO75DQ29 117 Al 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 Vss 120 A7 162 Vss 37 A8 79 CLK2 121 A9 163 CLK3 38 A10/AP 80 NC 122 BAO164 NC 39 BA1 81 NC 123 All 165 SAO 40 Vcc 82 SDA124 VCC 166 SA1 41 Vcc 83 SCL 125 CLK1 167 SA2 42 CLKO84Vcc 126 NC 168 Vcc

Pin assignments for a 168 pin SDRAM DIMM

A0-31

A0-31 Ideal memoryconﬁguration

4GB SRAM

Device SizePins 32 bit address bus Address range

PROM1 1MB 20 0000 0000 xxxx ++++ ++++ ++++ ++++ ++++ 0000 0000 - 000F FFFF RAM1 16MB 24 0000 0001 ++++ ++++ ++++ ++++ ++++ ++++ 0100 0000 - 01FF FFFF RAM2 16MB 24 0000 0010 ++++ ++++ ++++ ++++ ++++ ++++ 0200 0000 - 02FF FFFF RAM3 16MB 24 0000 0011 ++++ ++++ ++++ ++++ ++++ ++++ 0300 0000 - 03FF FFFF RAM4 16MB 24 0000 0100 ++++ ++++ ++++ ++++ ++++ ++++ 0400 0000 - 04FF FFFF

+address line used directly for internal selection xline ignored, indicates partial (degenerate) addressimg 0must be 0 for chip selection 1must be 1 for chip selection Memor y map for a small computer system

CPU

A0-31 System Bus A0 - A31, D0 - D7

A24 A0-23 A0-23 A0-23 A0-23 A0-19 A25 A26 RAM4 RAM3 RAM2 RAM1 PROM1 16MB 16MB 16MB 16MB 1MB c/s c/s c/s c/s c/s A27 100 A28 011 A29 010 A30 001 A31 000 3line Decoder (1 out of 8 selector) Memor y Schematic showing the Decoding Circuit

A31 - A24 address lines formemor y decoder

RAM4 0000 0100 1111 1111 1111 1111 1111 1111 04 FF FF FF 16MB 0000 0100 0000 0000 0000 0000 0000 0000 04 00 00 00 RAM3 0000 0011 1111 1111 1111 1111 1111 1111 03 FF FF FF 16MB 0000 0011 0000 0000 0000 0000 0000 0000 03 00 00 00 RAM2 0000 0010 1111 1111 1111 1111 1111 1111 02 FF FF FF 16MB 0000 0010 0000 0000 0000 0000 0000 0000 02 00 00 00 RAM1 0000 0001 1111 1111 1111 1111 1111 1111 01 FF FF FF 16MB 0000 0001 0000 0000 0000 0000 0000 0000 01 00 00 00 PROM1 0000 0000 0000 1111 1111 1111 1111 1111 00 0F FF FF 1MB 0000 0000 0000 0000 0000 0000 0000 0000 00 00 00 00 Binar y Hexadecimal

4Gbyte MemoryOrganisation

CPU I/O Dev2

I/O Dev3

80 0000 - RAM2 80 002F

RAM1

ROM 10 0000 - Motherboard 2F FFFF

00 0000 - 01 FFFF MEMORYMAP Memor y layout for a Memory-mapped I/O Scheme

or i.b #bmask,OP_reg ; logical OR a mask to set a portbit andi.b #$f7,OP_reg ;logical AND a mask to clear a portbit asl.b (a5) ;shift portbits left for displaypur poses not.b OP_reg ;shift portbits right for displaypur poses bclr #1,OP_reg ;test a portbit and leave it0 bset #2, (a2) ;test a portbit and leave it1

I/O Dev2

I/O Dev3

RAM2

RAM1

ROM 10 0000 - 2F FFFF

380 - 400 00 0000 - 01 FFFF MEMORYMAP I/O PORTMAP

Memor y and I/O layout for an I/O-mapped scheme

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 FG13054 18 19 USA HF 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

ABCDEFGHIJKLMNOPQRSTUVWXYZAA BB CC DD EE FF GG HH II JJ KK

Socket478 for the Pentium 4

Slot A processor card with a Pentium II

LevelI LevelI Dcache TLB Code cache TLB 8kBytes 8kbytes MMU MMU Addr Trans Addr Trans BTB

BPL Prefetch buffers Control Unit

vpipe upipe Floating decode decode point Microcode pipeline ROM

CPU Registers

Pentium subsystems schematic

CSA Rob Williams CSA ch 07 - p 74 Pearson Education (c) 2006 Name Processor P24T 486 Pentium OverDr ive, 63or83MHz, Socket3 P54C Clossic Pentium 75-200MHz, Socket517, 3.3v P55C Pentium NWX 166-266MHz, Socket7,2.8v P54CTB Pentium MMX OverDr ive125+, Socket517, 3.3v Tillomook Mobile Pentium MMX 0.25 µm, 166-266MHz, 1.8v P6 Pentium Pro,Socket8 Klamath Original Pentium II, 0.35 µm, Slot-I Deschutes Pentium 11, 0.25 µm, Slot 1, 256 Kbyte LII cache Covington Celeron PII, Slot-I, with no L2 cache Mendocino Celeron, PII with 28 Kbyte L2 cache on die Dixon Mobile Pentium IIPE, 256 Kbyte on-die L2 cache Katmai Pentium III, PII with SSE instructions Willamette Pentium III, on-die L2 Tanner Pentium 111 Xeon Cascades PIll, 0.18 µm, on-die L2 Merced P7, First IA-64 processor,on-die 12, 0.18 µm McKinley1GHz, ImprovedMerced, IA-64, 0.18 µm, copper interconnects Foster ImprovedPIII, IA-32 Madison ImprovedMcKinley, IA-64, 0.13 µm

IP EIP SP ESP

Flags EFlags

CS Access Base Address Limit CSDCR SS SSDCR DS DSDCR ES ESDCR FS FSDCR GS GSDCR 63 52 51 20 19 0 15 0 31 019 0 TSS selector TSS base address TSS limit TR LDT selector LDT base address LDT limit LDTR IDT base address IDT limit IDTR GDT base address GDT limit GDTR

CR0 CR1 Page Fault Service Routine CR2 Page Dir Base Reg CR3 31 12 0

i80x86/Pentium CPU Register Set

CSA Rob Williams CSA ch 07 - p 76 Pearson Education (c) 2006 MOVEAX,1234H ; load constant value 4660 into 32 bit accumulator INC EAX ;add 1 to accumulator value CMP AL,’Q’ ; compare the ASCII Q with the LS byte value in EAX MOVmaxval,EAX ; store accumulator value to memoryvar iable "maxval" DIV DX ;divide accumulator byvalue in 16 bit D register

EBX: Base registers hold addresses pointing to data structures,such as arraysin memor y.

LEA EBX,marks ; initializeEBX with address of the var iable "marks" MOVAL,[EBX] ; get byte value into AL using EBX as a memorypointer ADD EAX,EBX ;add 32 bits from EBX into accumulator MOVEAX,table[BX] ; take32bit value from the "table" array using the value in BX as the array index

ECX: The Count register has a special role as a counter in loops or bit shifting operations.

MOVECX,100 ; initializeECX as the FOR loop index ..... for1: ;symbolic address label ..... LOOP for1 ; decrement ECX, test for zero,JMP backifnon-zero

EDX: The Data register can be involved during input/output data transfers or when executing integer multiplication and division. Otherwise it is generally available for holding var iables.

IN AL,DX ;input byte value from port, with 16 bit portaddress in DX MUL DX ;multiply A byvalue in D

ESI: Source Indexregister is a pointer for string or array operations within the Data Segment.

LEA ESI,dtable ; initializeSIwith memoryaddress of var iable "dtable" MOVAX,[EBX+ESI] ; get word using Base address and Indexregister

EDI: Destination Indexregister is a pointer for string or array operations within the Data Segment.

MOV[EDI],[ESI] ; movesa32bit word from source to destination locations in memory

CSA Rob Williams CSA ch 07 - p 77 Pearson Education (c) 2006 EBP: The StackBase Pointer register is used as the stackframe pointer to support HLL procedure operations.Itistaken as an offset within the StackSegment.

ENTER 16 ;saves EBP on stack, copies ESP into EBP,and subtracts 16 from ESP

EIP: The Instruction Pointer (ProgramCounter) holds the offset address of the next instr uction within the current Code Segment.

JMP errors ;forces a newaddress into EIP

ESP: The StackPointer holds the offset address of the next item available on the stackwithin the current StackSegment.

CALL subdo ;call a subroutine (subdo), storing returnaddress on stack PUSH EAX ;save32bit value in accumulator on stack

EFLAG: Flag Register contains CPU status ﬂags,implicated in all conditional instr uctions.

JGE back1 ; tests sign ﬂag for conditional jump LOOP backagin ; tests zero ﬂag for loop exit condition

CS - GS: These 16 bit Segment Selector registers were originally introduced to expand the addressing range of the i8086 processor while maintaining a 16 bit IP. The Segment Register is added to the EIP register to for m a32bit address.

CSDCR - GSDCR: 64 bit Code Segment Descriptor Cache Register holds the current Code Segment Descriptor,which includes: Base address,sizeLimit and Access permissions.The Segment Descriptor is obtained from either the Global or Local Descriptor Tables.

TR: The Task Register holds the 16 bit segment selector,the 32 bit base address, the 16 bit sizelimit and the descriptor attributes for the current task. It references a TSS descriptor in the Global Descriptor Table (GDT). When a task switch occurs, the Task Register is automatically reloaded.

IDTR: The 48bit Interrupt Descriptor Table Register holds the base address and sizelimit of the current Interrupt Vector Table (IVT).

GDTR: The Global Descriptor Table Register holds the segment descriptors which point to universally available segments and to the tables holding the Local Descr iptors.

LDTR: Each task can use a Local Descriptor Table in addition to the Global CSA Rob Williams CSA ch 07 - p 78 Pearson Education (c) 2006 Descr iptor Table. This register indicates which entryinthe Local Segment Descr iptor Tabletouse.

CR3: This Control Register points to the directorytable for the Paging Unit.

CR2: This Control Register points to the routine which handles page faults which occur when the CPU attempts to access an item at an address which is located on anon-resident memorypage.The service routine will instigate the disk operation to br ing the page backinto main memoryfrom disk.

1. data movement (copying) 2. data input/output operations 3. data manipulation 4. transfer of control 5. machine supervision

Classes of CPU instructions

MOVcopies data from location to location, register or memory LEA load effectiveaddress CALL calls to a subroutine RET returnfrom a subroutine PUSH push an item onto the stack, possibly as a subroutine parameter POP pop an item off the stack

INC/DEC increment or decrement ADD arithmetic integer addition SUB arithmetic subtraction for 2s complement integers CMP compare 2values,asubtract with no result, only setting ﬂags AND/OR/XOR logical operators TEST bit testing

JZ conditional jump LOOP implements aFOR loop bydecrementing the CX register ENTER sets up a subroutine (procedure) stackframe LEAVE cleans up a stackframe on exit from a subroutine

JMP a dreaded jump instruction INT software interrupt to get into an operating system routine

0-3bytes 1-2bytes 0-1bytes 0-1bytes 0, 1, 2 or 8 bytes Operand Displacement / Preﬁx Opcode D W SIB MOD REG R/M Immediate Data

EAX ECX EDX EBX ESP ESI EDI 2EH CSEG 00 Memor y [EAX] 00 01 02 03 04 05 06 07 3EH DSEG 01 Memor y+d8 [ECX] 08 09 0A 0B 0C 0D 0E 0F 36H SSEG 10 Mem+d32/d16 [EDX] 10 11 12 13 14 15 16 17 26H ESEG 11 Register [EBX] 18 19 1A 1B 1C 1D 1E 1F 64H FSEG 20 21 22 23 24 25 26 27 65H GSEG [EBP] 28 29 2A 2B 2C 2D 2E 2F 66H 32bit mode [ESI] 30 31 32 33 34 35 36 37 B8H 16bit mode [EDI] 38 39 3A 3B 3C 3D 3E 3F F0H Lock F3H REP W=0 W=1 R/M MOD=00 MOD=01 MOD=10 000 AL AX 000 (BX+SI) (BX+SI+d8) (BX+SI+d16) 0REG is source 001 CL CX 001 (BX+DI) (BX+DI+d8) (BX+DI+d16) 1REG is destination 010 DL DX 010 (BP+SI) (BP+SI+d8) (BP+SI+d16) 011 BL BX 011 (BP+DI) (BP+DI+d8) (BP+DI+d16) 100 AH SP 101 CH BP 100 (SI) (SI+d8) (SI+d16) 110 DH SI 101 (DI) (DI+d8) (DI+d16) 111 BH DI 110 direct (BP+d8) (BP+d16) 111 (BX) (BX+d8) (BX+d16)

d8 - a byte of data

d16 - a2byte word Pentium instruction code ﬁelds

66 B80000000000001200 MOVEAX,12H ______01100110 1011 1 000 0000 0000 0000 0000 0000 0000 0001 0010 ------|------32b i tpreﬁx MOV o pWord AXimm e diate data

3C 71 CMP AL,’q’ ______0011110 0 0111 0001 ------| ------CM P AopByteImm e diate data

31 0

ID VIP VI AC VM R N IOP O D I T S Z A P C

ID identification flag for CPUID availability VIP vir tual interr upt pending VI vir tual interr upt active AC alignment check VM vir tual 8086 mode active RFR resume task after breakpoint interrupt NT nested task IOPL i/o privilege level O ar ithmetic overflowerror D direction of accessing string arrays IE exter nal interr upt enable T trap,single step debugging, generates an INT #1 after each instruction S sign, MS bit value Z zero,result being zero A auxiliar y carr y,used byBCD arithmetic on 4 LS bits P par ity,operand status C carr y,indicates an arithmetic carryorborrowresult CPU status flag register

Data Register Direct

MOV EAX,EBX +++ +++

Immediate Operand (IP indirect)

MOV EAX,1234 ++++

Memor y Direct

MOV EAX,[var1] The assembler distinguishes 1234 from [1234] ++++++

Address Register Direct

LEA EBX,var1 ++++

MOV EAX,[EBX] +++++

IndexedRegister Indirect with displacement

MOV EAX,[table+EBP+ESI] +++++++++++++++

MOV EAX,table[ESI] ++++++++++ CSA Rob Williams CSA ch 07 - p 83 Pearson Education (c) 2006 prefetch decoderoperand store execute buffer stage 1 read result Pre fetcher unit Control PC Instr uctions Branch Detector Decoder logic

Integer ALU Data

Fetch Decode1 Readin Execute Wr iteback Cycle 1 JMP ADD - - -

Cycle 2 NOP JMP ADD - -

Cycle 3 NOP NOP JMP ADD -

Cycle 4 NOP NOP NOP JMP ADD

Cycle 5 NOP NOP NOP NOP JMP

Cycle 6 AND NOP NOP NOP NOP

System Clock

Parallelization bypipelined operation

8kB 8kB LI Data Cache Code Cache

F/Point V-pipe U-pipe decoder

Output Window Editor Window CPU Registers Memor y Window with source code with hexdump breakpoint mark of memory and IP indexmar k

MS VC++ Developer Studio debugger screen

int main (void) { char format[] = "Hello World\n" //declare variables in C

__asm { ;switch to inline assembler mov ecx,10 ;initialize loop counter Lj: push ecx ;loop count index saved on stack lea eax,format push eax ;address of string, stack parameter call printf ;use library code subroutine add esp,4 ;clean 4 byte parameter off stack pop ecx ;restore loop counter ready for test loop Lj ;dec ECX, jmp back IF NZ };back to C return 0; }

[F1] HELP [F4] go to next error [ˆ F5] runthe program [F7] build executable code [ˆ F7] compile only [F9] set breakpoint [F10] single step (overfuntions) [F11] single step into functions [ALT][TAB] toggled windows backwards/forwards

CSA Rob Williams CSA ch 07 - p 87 Pearson Education (c) 2006 1. CPU registers 2. Programmemor y with labels and disassembled mnemonics 3. Data memorywith ASCII decode table 4. Output screen for your programunder test 5. Stack, but only for the returnaddresses.

Debug x            

Restar t debugger Disassembly Stop Display debugger Stack Break Display execution Memor y Show Display instr uction Registers Display Step into Variables

Step over Watch

Step out of QuickWatch Run to cursor Debug Toolbar in VC++ DevStudio

CSA Rob Williams CSA ch 07 - p 88 Pearson Education (c) 2006 ˆ[ESC] open the StartMenuonthe Taskbar.You can the nopen applications [Tab] on the desktop,this switches between desktop,Taskbar and Startmenu If you already have the Startmenu, [Tab] switches between Applications. Alt [F4] ter minate current application This can also terminate Windows if you are on the desktop! Alt [Tab] switch to next window Shift Alt [Tab]switch to preceding window [ESC] this sometimes cancels the previous action [F1] displaythe On-line Help for applicatioons Shift [F1] context sensitivehelp [F2] If an icon is highlighted you can change its name [F3] get Find

Ke yboard Shortcuts for Windows

. . 1 average(. ) { . . 2 . average(&maths);. retur n 1 . } . retur n 2? average(&english); Subroutine . . .

Main Program

. . . 1 average(. ) { 3 . . . . average(&maths);. 2 . 4 average(&ages);. . retur n 1 } retur n 3 . . . average(&english); ? average(&taxes); retur n 2 retur n 4 . . . . . DLL . Subroutine

ProgramA ProgramB The "where to returnto?" problem

. . average( ) { call . . Stackarea . average(&m);. . . . ret addr . call . . ret . . retur n EIP . } Main Program Subroutine The Stacksolution

System Bus

Stack

Main Memor y

System stackinmain memory, SPregister in CPU

ﬂoat average(int x, int * y) { int i; ﬂoat av; for(i=0; itechnology = %3.1f\n", average( NCLASS,tech_scores)); ...... }

PUSH EAX ;push 32bit word in A onto stack Stackgrowing Stack CALL printf ;do something downwards POP EBX ;pop the 32bit word from stack in memory

ESP

PUSH POP EAX EBX

Stackoperation

1. to save the return address dur ing PROCEDURE calls 2. to pass parameters into PROCEDURES 3. to allocate Local Variable storage space (stackframe) 4. as temporar y scratch-pad storage for register values

Uses of the system stack

<-- clear ing down the stackframe

Disassembled C programwith stackoperations

73 10 40 00 retur n address 0A 00 00 00 NCLASS StackGrowing 30 5A 41 00 maths_scores

ret add 1 ret add 1 me 1 ret add 1 ret add 1 ESP EBP 1 ra EBP 1 EBP 1 EBP EBP kf Stack loc vars loc vars loc vars stac grows ESP ESP params 2

ret add 2 me 2

EBP 2 ra EBP kf loc vars stac ESP

0000 0000 Main subr tn 1 Main program subr tn 2 subr tn 1 program sets up calls installs calls retur ns retur ns parameters local and return variables address

02 00 00 00 space for av-current Head of Stack 80 31 41 00 space for i StackGrowing 80 FF 12 00 old EBP value

Subroutine calls with stackframe data

CSA Rob Williams CSA ch 8 - p 97 Pearson Education (c) 2006 #include char* getname(void) { char nstring[25]; printf("Please type your name: "); gets( nstring); putchar(’\n’); return nstring; //SERIOUS ERROR IN THIS PROGRAM } int main(void) { char* myname; myname = getname(); printf("%s\n", myname); return 0; } Spot the error here!

Interr upt arr ives . . ser ial_isr. : . . . add EAX,3);. retur n . IRET . moveax,10; . Interr upt . Ser vice . Routine

Main Program

Interr upt Ser vice Routines (ISR) as h/w triggered subroutines

System Clock CPU

Interr upt Request

System Bus

I/O Subsystem Main Memory

I/O subsystem

1. Dedicated and Per iodic polling 2. Interrupt dr iven 3. Direct MemoryAccess (DMA)

Different Input/Output Techniques

HLL librar y

O/S Routines

HAL

Hardware

Software Access to Hardware

1. Command Registers 2. Status Registers 3. Data Registers

Categor ies of Per ipheral chip register

Functional Description I/O PA7- Data Bus Buffer POWER +5V GROUP A PA0 SUPPLIES GND GROUP A PORT A CONTROL (8) This three-state bi-directional 8-bit buffer is used to interface I/O the 82C55A to the system data bus. Data is transmitted or PC7- received by the buffer upon execution of input or output GROUP A PC4 BI-DIRECTIONAL PORT C instructions by the CPU. Control words and status informa- DATA BUS UPPER (4) I/O tion are also transferred through the data bus buffer. DATA PC3- D7-D0 BUS GROUP B PC0 BUFFER 8-BIT PORT C Read/Write and Control Logic INTERNAL LOWER DATA BUS (4) The function of this block is to manage all of the internal and I/O external transfers of both Data and Control or Status words. RD READ PB7- GROUP B It accepts inputs from the CPU Address and Control busses WR WRITE PB0 A1 CONTROL GROUP B CONTROL PORT B and in turn, issues commands to both of the Control Groups. A0 LOGIC (8) RESET (CS) Chip Select. A “low” on this input pin enables the communcation between the 82C55A and the CPU. (RD) Read. A “low” on this input pin enables 82C55A to send CS the data or status information to the CPU on the data bus. In FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER, essence, it allows the CPU to “read from” the 82C55A. READ/WRITE, GROUP A & B CONTROL LOGIC FUNCTIONS (WR) Write. A “low” on this input pin enables the CPU to write data or control words into the 82C55A. (RESET) Reset. A “high” on this input initializes the control (A0 and A1) Port Select 0 and Port Select 1. These input register to 9Bh and all ports (A, B, C) are set to the input signals, in conjunction with the RD and WR inputs, control mode. “Bus hold” devices internal to the 82C55A will hold the selection of one of the three ports or the control word the I/O port inputs to a logic “1” state with a maximum hold register. They are normally connected to the least significant current of 400µA. bits of the address bus (A0 and A1). Group A and Group B Controls 82C55A BASIC OPERATION The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a con- INPUT OPERATION trol word to the 82C55A. The control word contains A1 A0 RD WR CS (READ) information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 82C55A. 00010Port A → Data Bus Each of the Control blocks (Group A and Group B) accepts 01010Port B → Data Bus “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the 10010Port C → Data Bus proper commands to its associated ports. Control Group A - Port A and Port C upper (C7 - C4) 11010Control Word → Data Bus Control Group B - Port B and Port C lower (C3 - C0) OUTPUT OPERATION The control word register can be both written and read as (WRITE) shown in the “Basic Operation” table. Figure 4 shows the control word format for both Read and Write operations. 00100Data Bus → Port A When the control word is read, bit D7 will always be a logic “1”, as this implies control word mode information. 01100Data Bus → Port B

10100Data Bus → Port C

11100Data Bus → Control

DISABLE FUNCTION

XXXX1Data Bus → Three-State

X X 1 1 0 Data Bus → Three-State

Data Sheet (page 3) for a Harris 82C55A Parallel Por t I/O Chip

D7 D6 D5 D4 D3 D2 D1 D0 Control Register

C0 -C3:1-input, 0 - output

B0 -B7:1-input, 0 - output

Mode: 0 -basic,1-strobed

C4 -C7:1-input, 0 - output

A0 -A7:1-input, 0 - output

Mode: 00 - basic,01-strobed, 10 - bus

1-set portmodes

Control Register for the 8255 PIO

Alter nativeI/O or Memorymapping

// Win-98. Initializes 8255 at 0x1f3: Port A IN; B OUT; C OUT outp((short)0x1F3, 0x90); // init 8255 cmnd reg

Initialization using C

Interr upt Request

System Bus

A0-A19 D0-D7 A21- A0-A1 A23 status reg PROM Memory I/O command reg Subsystem 0 C/S RAM data regs I/O C/S

Memor y decoder Accessing Registers in Memory-mapped I/O

Address Device SizePins Address busAddress range

PROM1 1MB 20 000x ++++ ++++ ++++ ++++ ++++ 00 0000 - 0F FFFF RAM1 2MB 21 001+ ++++ ++++ ++++ ++++ ++++ 20 0000 - 3F FFFF RAM2 2MB 21 010+ ++++ ++++ ++++ ++++ ++++ 40 0000 - 5F FFFF RAM3 2MB 21 011+ ++++ ++++ ++++ ++++ ++++ 60 0000 - 7F FFFF I/O 4B 2111x xxxx xxxx xxxx xxxx xx++ E0 0000 - E0 0003 E0 0004 - E0 0007  aliases  E0 0008 - E0 000B  E0 000C - E0 000F ...

DATIN: IN AX,RXDATA ;get Rx data & clear RXRDY flag OR AL,AL ;test for end marker JZ COMPLETE ;jmp out if finished MOV [DI],AL ;save character in data buffer INC DI JMP LOOP ;back for more input COMPLETE: .... ;character string input complete

do { while (!(*(BYTE*)RXSTATUS & RXRDY)) { } ;/* wait for data */ }while (*pch++ = *(BYTE*)RXDATA) ; /* check for a NULL */

Polled I/O in ASM & C

Inter mittant Dedicated timed polling spin polling

CSA Rob Williams CSA ch 09 - p 105 Pearson Education (c) 2006 System buses operate at 500 Mbyte/sec Blocks of characters can be movedat100 Mbyte/sec Ether net transfers data at 10 Mbytes/sec Telephone call needs 8Kbyte/sec Ser ial lines frequently run at 1Kbyte/sec Epson printers operate at 100 byte/sec Ke yboards send at 4byte/sec

Relativedevice speeds

/* messages */ #define PAPER_OUT -1 #define DE_SELECT -2 #define YES 0 #define NO -1 #define OK 0

/* address, offsets and setting for M68681 DUART */ #define DUART 0XFFFF80 /*base address*/ #define ACR 9/*aux control reg */ #define CRA 5/*command reg A */ #define MRA 1/*mode reg A */ #define CSRA 3/*clock select A */ #define SRA 3/*status reg A */ #define RBA 7/*rx reg A*/ #define TBA 7/*tx reg A */ #define RXRDY 1/*bit mask for rx ready bit */ #define TXRDY 4/*bit mask for tx ready bit */

/*Settings for the Motorola M68230 Parallel Interface Timer These only deal with mode 0.0, and for ports B and C No details about the timer. */

/* PI/T offsets and adresses, PIT registers are all on odd addresses */ #define PIT 0Xffff40 /*address of PI/T */ #define BCR 0Xf /*offset for port B cntrl Reg*/ #define BDDR 7/*offset for B data direction*/ #define BDR 0X13 /*offset port B data reg */ #define CDR 0X19 /*offset port C data reg */

/* Parallel port settings masks and modes */ #define MODE0 0X20 /* mode 0.0, 2X buff i/p, single buff o/p */ #define MODE01X 0X80 /* mode 0.1X, unlatch i/p, 1X buff o/p */ #define OUT 0XFF /* all bits output: 0 - i/p, 1 - o/p*/ #define STROBE_MINUS 0X28 /* strobe printer -ve */ #define STROBE_PLUS 0x20 /* strobe printer +ve */ #define PRINT_ST 1/*paper out pin 00000001 */ #define PAPER_ST 2/*paper out pin 00000010 */ #define SELECT_ST 4/*selected pin 00000100 */

#include "io.h"

/* set up Mc68681 DUART serial port A only */ void dinit() { register char *p; register int i;

p=(char *)DUART; *(p+ACR) = 128; /* set baud rate */ *(p+CRA) = 16; /* reset Rx */ *(p+MRA) = 19; /* no modem, no PARITY, 8bits */ *(p+MRA) = 7; /* no ECHO, no modem cntrl, 1 STOP */ *(p+CRA) = 5; /* enable Rx & Tx */ *(p+CSRA)= 187; /* Rx & Tx at 9600 */

p=(char *) PIT; /* set to base address of PI/T */ *(p + BCR ) = MODE0; /* mode 0.0 */ *(p + BDDR ) = OUT;

for(i=0; i != 1000;i++) ;/* init delay*/ }

/* set up 68230 PIT for print out on port B */ void pinit() { char *p; p=(char *) PIT; /* set to base address of PI/T */ *(p + BCR ) = MODE0; /* mode 0.0 */ *(p + BDDR ) = OUT; }

/* get char from serial port A returns character */ char get() { register char *p;

p=(char *)DUART; while ( !( *(p+SRA) & RXRDY )) { }; /* block here */ return *(p+RBA); }

/* put character c to serial port A */ void put( char c) { register char *p;

p=(char *)DUART; while ( !( *(p+SRA) & TXRDY )) { }; /* block here */ *(p+TBA) = c; }

/* put string to serial port A using put routine */ void puts(char* p) { while( *p ) put(*p++); put(’\n’); } Continues

p=(char *) PIT; while ( *(p + CDR) & PRINT_ST ) { if ( !( *(p + CDR) & PAPER_ST) ) return (PAPER_OUT) ; if ( !( *(p + CDR) & SELECT_ST) ) return ( DE_SELECT); } *(p + BDR) = c; /*send data */ *(p + BCR) = STROBE_MINUS;/* strobe positive */ *(p + BCR) = STROBE_PLUS;/* strobe negative */ return OK ; }

Telephonic Interr uptions

CPU Interr upt Request

System Bus

Main Memory I/O A I/O B I/O C

PIC Interr upt Request CPU

System Bus

Main Memory I/O A I/O B I/O C

Alter nativeinterr upt arrangements

CSA Rob Williams CSA ch 09 - p 110 Pearson Education (c) 2006 Int Function Source IRQ0 Number IRQ1 77 Hard Disk2 IRQ15 76 Hard Disk1 IRQ14 IRQ3 PIC 1 75 8087 IRQ13 IRQ4 74 PS/2 Mouse IRQ12 to CPU 73 Soundcard IRQ11 interr upt IRQ5 72 Networ k IRQ10 IRQ6 71 Redirected IRQ2 IRQ7 70 RTC IRQ8 ...... IRQ8 18 BIOS/TOD INT IRQ9 17 BIOS/softboot INT IRQ10 16 BIOS/print INT IRQ11 15 BIOS/KBD INT PIC 2 14 BIOS/comms INT IRQ12 13 BIOS/disk INT IRQ13 12 BIOS/msizeINT IRQ14 11 BIOS/checkINT IRQ15 10 BIOS/Video INT 0F LPT1: IRQ7 0E FDC IRQ6 0D SoundCard IRQ5 0C COM1: IRQ4 0B COM2: IRQ3 0A ---- IRQ2 09 KBD: IRQ1 08 System Timer IRQ0 07 06 05 Screen dump to printer 04 Numeric Overﬂow 03 Breakpoint 02 NMI, Po wer fail 01 Single Step Trace 00 Integer Divide Error

Part ofthe PC Interrupt Vector Table (IVT)

CPU Interr upt request

IVR main() I/O chip

isr

IVT Memor y Locating the Interrupt Service Routine

1. I/O data transfer request 2. Software TRAP (SVC) 3. Machine Failure 4. Real-time Tick 5. Run-time Software Error 6. System Reset or Watchdog

Possible Sources of Interrupts

Imposing access controls using interrupts

mouse activity

Interr upts per second

? secs 59 Displaymins msecs=0 mins 59 secs++ hrs 01 Displayhrs ?

secs = 0 mins++

mins = 0 Hours Mins Secs hrs++

hrs = 0 Shared data corruption problem

rte

1.disable interrupts 2. serialise the access 3. use a semaphore

Cr itical region protection

CSA Rob Williams CSA ch 09 - p 115 Pearson Education (c) 2006 TickFlag Interr upt No tick request ? tickF++ tickF=0 msecs++ ISR Data Var iables in Memory ? N msecs 990 msecs=0 secs++ secs 59 ? N mins 59 secs = 0 hrs 01 mins++

? N

mins = 0 hrs++

N ?

hrs = 0 N

Displaysecs

Displaymins

Displayhrs

Ser ialized access to shared data

Tx Tx Interrupt putc( ) Dev request Dr iver Tx ISR Tx data

User Receive UART Application Data Buffer Rx Rx ISR getc( ) Dev Rx Interrupt Rx data Dr iver request

Operating system managed I/O

CPU

System Bus

data

source I/O Subsystem destination Main Memory count

DMA Controller Using DMA to Transfer Data

Channel Function Width 0DRAM refresh 8bits 1SoundBlaster 8 bits 2FloppyDrive 3 4cascaded to second DMA controller 5SoundBlaster 16 bits 6 7

Input 1 2 3

Process 1 2 3

Output 1 2 3

Input 1 2 3

Process 1 2 3

Output 1 2 3

time The importance of overlapping operations

#include

int main(void) { int answer; do { printf("please enter a single letter: "); answer = getchar(); putchar(’\n’); printf("%c\n",answer); }while (answer != ’E’);

return 0; }

Problems with keyboard input

please enter a single letter: ?

please enter a single letter: B B

please enter a single letter: ?

please enter a single letter:

Ke y codes in hex please enter a single letter: A A 41 please enter a single letter: CR 0a please enter a single letter: B

B 42 please enter a single letter: CR 0a please enter a single letter:

#include int main(void) { int answer; do { printf("please enter a single letter: "); answer = getchar(); getchar( ); putchar(’\n’); printf("%c\n",answer); }while (answer != ’E’); return 0; }

data -compression and coding schemes,quantity timing -synchronization of rx with tx: frequency and phase signaling-error handling, ﬂowcontrol, and routing

Three key issues for communication

100µs 50µs

Tx Rx

Receiver must sample near the middle of an incoming bit

wr ite data bit to line

Data sample data now

Rx Clock

Clockdrift problems for asynchronous receivers

SYN - special ﬂag Byte to assist receiver with Byte-levelsynching. only used when the channel is operating in Synchronous mode SOH - Startofamessage header STX - Startofmessage text block ETX - End of message text block. Messages can be split into multiple blocks. EOT-End of message transmission

Parity Bits -simple to apply,not ver y secure BlockChecksums-simple to apply,not ver y helpful Polynomial Division-more complex, better security

Error Detection and Correction Techiques

Data w 0 00000111 1 00001000 1 1 00001001 0 0 00001010 0 00001011 1 1 00001100 0 etc

Parity bit

Using XOR gates to compute parity

Data Par ity is Computed NewPar ity to be and appended Tr ansmit value sent to makeEVEN computed fortransmission and compared

0110_0111 0110_0111 1Noerrors 0110_0111 1 no error detected Error ↓ 0111_0110 0111_0110 10111_1110 1 0111_1110 0 error detected Errors↓↓ 0111_0100 0111_0100 00111_1101 0 0110_0101 0 no error detected !

Error detection using single appended parity bit

Tr iple Par ity Bit Assignment

87654321 p4 p3 p2 p1 Pd4d3d2Pd1PP

Assigning Par ity Bits to Longer Words

Parity bits p123 4 56 7 8 2p248163264128 256 Data bits d014112657120 247

d = 2p − (p + 1) 4d-3p Data and parity bits to achieve single error correction

[1010100] x 1 1 1 = [001] 7654321 1 1 0 So p3 = 0, p2 = 0, and p1 = 1 dddpdpp 1 0 1 1 0 0 giving [1010101]for transmission 0 1 1 0 1 0 0 0 1 Calculating a 4d-3p Syndrome (Transmitter)

The 4d-3p syndrome (receiver) with 1 bit error

No Single Double error error error p0 agrees error agrees

Syndrome 0 nonzero nonzero -> error confused

Single error correction, double error detection by multiple parity

CSA Rob Williams CSA ch 10 - p 125

Type Length Address Data Checksum

Motorola S-Record for mat with trailing checksum

S0 03 0000 FC

S2 24 010400 46FC26002E7C000808006100005E610000826100033C46FC270023FC00010678 6B

S2 24 010420 000C011023FC00010678000C011423FC00010678000C011823FC00010678000C 6D

S2 24 010440 011C610003A4303C271053406600FFFC46FC21006100057A4E4B000000004E75 3B ......

S2 24 012200 0968584F4878004C4EB900010928584F206EFFFC524810BC0004602248790001 7D

S2 24 012220 21CA4EB900010968584F487800484EB900010928584F206EFFFC524842104E5E 84

S2 08 012240 4E750000 D1

S8 04 000000 FB

Example Fragment of a Motorola S Record For mat File

08 + 01 + 22 + 40 + 4E + 75 + 00 + 00 = 12E forget the 1 as overﬂow, leaving 2E (0010 1110 ) invert the bits 1101 0001 ( D1 )THE CHECKSUM !

CSA Rob Williams CSA ch 10 - p 126 Pearson Education (c) 2006 11100 11110 ______101|1100100 101|1100110 101 101 ------110 110 101 101 ------111 111 101 101 ------100 101 101 101 ------000->indicates 10=Remainder no errors to send

Sender Receiver Calc. of a CRC at sender and receiver for data item 11001 1. All error bursts of 16 bits or less, 2. All odd numbers of bits in error, 3. 99.998% of all error bursts of anylength.

CRC Generation using Shift Registers and XOR gates

Rx and Tx data Rx and Tx data

Xon / Xoff CTS RTS control RTSCTS hardware handshake software handshake RS232 ﬂowcontrol techniques

Ser ial links dedicated route,noaddressing needed LAN broadcast transmission, receiver does the identiﬁcation WANselectiverouting can be dynamically changed

Data routing methods for serial communications

space / logic 0 +9v Star t lsb msbParity Idle / mark Stop logic 1 / -9v

RS232 voltages representing ASCII ’1’ (31H)

→ 2RxData 5 1 9 6 ← 3TxData ← 4DTR Data Terminal Ready SocketNumber ing --- 5 Ear th

← 7RTS Ready to Send → 8CTS Clear to Send RS232 9-way D-type Pin Functions (COM1 & COM2)

Setting COM1 portParameters with Hyperter minal

CSA Rob Williams CSA ch 10 - p 129 Pearson Education (c) 2006 /* Transmitter.c */ #include int main(void) { FILE *dp; int c; if ((dp = fopen("COM2", "w"))==NULL) { printf("fail to open COM port\n"); return 1; } while ((c=getch()) != EOF) { fputc( c, dp); fflush(dp); } return 0; ======/* Receiver.c */ #include int main(void) { FILE *dp; int c; if ((dp = fopen("COM2", "r"))==NULL) { printf("fail to open COM port\n"); return 1; } while ((c= fgetc(dp)) != EOF) { putch( c); } return 0;

Exchanging messages across an RS232 link on a PC

Receive 16550 Tr ansmit UART

RS232 Serial link Attaching a UART, ser ial line interface

CSA Rob Williams CSA ch 10 - p 131 Pearson Education (c) 2006 /* Filetrans.c */ #include #include #define CNTRLZ 0x1A int main(void) { FILE * fp FILE * dp; int c; if ((fp=fopen("C:\TEMP\text.dat", "rt"))==NULL) { printf("fail to open data file\n"); return 1; } if ((dp = fopen("COM2", "wt")) == NULL) { printf("fail to open COM port\n"); return 1; } while ((c = fgetc(fp )) != EOF) { fputc( c, dp); } fputc(CNTRLZ, dp); fflush(dp);} fclose(fp);

/* Filereceive.c */ #include #include #define CNTRLZ 0x1A int main(void) { FILE *fp; FILE *dp; int c; if ((fp=fopen("C:\TEMP\text.dat", "w"))==NULL) { printf("fail to open data file\n"); return 1; } if ((dp = fopen("COM2", "r")) == NULL) { printf("fail to open COM port\n"); return 1; } while ((c= fgetc(dp)) != CNTRLZ) { fputc( c, fp); } fflush(fp); fclose(fp); return 0; } Slowinter-PC ﬁle transfers vis COM2

CSA Rob Williams CSA ch 10 - p 132 Pearson Education (c) 2006 #include #include #include #include HANDLE hCom; char inpacket[16], outpacket[16]; BOOL fSuccess; //////////////////////////////////////////////////// // Initializes PC COM2 port to non-blocking mode // void initcomm(void) { COMMTIMEOUTS noblock; DCB dcb; hCom=CreateFile("COM2", GENERIC_READ | GENERIC_WRITE, 0, NULL, OPEN_EXISTING, 0, NULL ); if (hCom == INVALID_HANDLE_VALUE) { dwError = GetLastError(); printf("INVALID_HANDLE_VALUE()"); } fSuccess = GetCommTimeouts(hCom, &noblock); noblock.ReadTotalTimeoutConstant = 1; noblock.ReadTotalTimeoutMultiplier = MAXDWORD; noblock.ReadIntervalTimeout = MAXDWORD; fSuccess = SetCommTimeouts(hCom, &noblock); fSuccess = GetCommState(hCom, &dcb); if(!fSuccess) printf("GetCommState Error!"); dcb.BaudRate = 9600; dcb.ByteSize = 7; dcb.fParity = TRUE; dcb.Parity = EVENPARITY; dcb.StopBits = TWOSTOPBITS; dcb.fRtsControl = RTS_CONTROL_HANDSHAKE; dcb.fOutxCtsFlow = TRUE; fSuccess = SetCommState(hCom, &dcb); if(!fSuccess) printf("SetCommState Error!"); else printf("Comm port set OK!0); } Continues

CSA Rob Williams CSA ch 10 - p 133 Pearson Education (c) 2006 ////////////////////////////////////////////////// // Reads COM2, single character // IF !char on COM2 return 0, ELSE return ASCII char // char readcomm() { char item; int ni; fSuccess = ReadFile( hCom, &item, 1, &ni, NULL ); if (ni >0 ) return item; else return 0; } ////////////////////////////////////////////////// // tests and reads keyboard // IF !char on kbd return 0, ELSE return ASCII char // char readkbd() { if (kbhit() ) return _getch(); else return 0; }

Using COM2 in Non-blocking Mode

Xroller IR emitter and sensor Mouse ball Optical disk sensors

Optical disk direction and speed sensing

-6v,Txdata +6v,RTS Rxdata

Mouse UART 1200kHz Crystal X Y

Mouse Buttons X&Ywheels

Arrangement for a PC Serial Mouse with UART

Sdio Ser ial por t Oscillator Sclk Sensor array XA Po wer on &DSP LED light source reset

XB ature YA output YB Sensor Quadr &DSP

LED ltage regulator dr ive Vo Desk top Optical mouse image sensor DSP

CSA Rob Williams CSA ch 10 - p 135 Pearson Education (c) 2006 hardware issues plugs & sockets don’t fit: 25/9 pin, sockets/pins Tx and Rx pins confused - crossed vs uncrossed lead different plug configurations incorrect wiring of h/w flowcontrols (CTS/RTS) reversed internal IDC ribbon cables incorrectly assembled IDC ribbon cables incorrectly installed interface card (IRQ, dma, portno.) ser ial por t hardware not initialized

incompatible transmission for mats ASCII vs EBCDIC or Unicode line speed setting: 1200, 2400, 9600 bps error checks: odd/even/none parity ASCII char length: 7 vs 8 bits number of stop bits user deﬁned packetlengths CR-LF line terminator differences in ﬁles tab vs multiple SP differences Word Processor control characters (Word) EOF problems

ﬂowcontrol failure CTS input uncontrolled byreceiver RTS/CTS talking to XON/XOFF inter mediate buffers on end-to-end ﬂowcontrol unread echo characters on serial lines RAM buffer threshold problems

software problems sending/receiving data through wrong channel incorrect device driver installed uninstalled device driver

Tips and hints on serial connection failure

CSA Rob Williams CSA ch 10 - p 136 Pearson Education (c) 2006 Control - used bythe root hub to pass on conﬁguration instructions and data to the devices,especially used during the initialization period. Isochronous - timed data transfers for devices with real-time data streams. Bulk - simple non-time sensitive Interr upt -USB is not an interrupt system, it depends on timed polling from the hub to pickupdata, such as keyboard input.

upstream downstream Hub 1 Hub 5 Hub 3 host Hub 4 USB devices Hub 6 Hub 2

Universal Serial Bus Connectivity

RAM ROM IP upstream port

USB interface

CU ALU SP downstream ports

Periphs

Intel 8x931 USB Per ipheral Microcontroller

Local Local Inter nal Exter nal analogue analogue modem modem line line Digital trunk lines

Using modems to transfer data on the telephone networ k

1 1 1 1 1 0 0 0 0 0 Data

...... ON / OFF ...... Carr ier ......

...... FSK ...... Frequency ...... Shift Keying ......

Frequency Modulation Technique

ITU Cat Capacity Type V.21 300/600 bps Frequency shift V.22 1200 bps Phase shift V.22bis 2400 bps Amplitude &Phase shift V.29 9600 bps Phase shift V.32 9600 bps Amplitude &Phase shift V.32bis 14.4 kbps Amplitude &Phase shift V.17 14.4 bps Fax V.34 28.8 kbps Amplitude &Phase shift

Modem Standards and Coding Schemes

CSA Rob Williams CSA ch 10 - p 138 Pearson Education (c) 2006 Command Function ATA Answerincoming call ATDnnn-nnnn Tone dials the phone number nnn-nnnn ATLRedials last number dialed ATPDnnn-nnnn Pulse dial nnn-nnnn ATWWait for dial tone ATH0 Hang up ATM0 Speaker off ATM1 Speaker is on until a carrier is detected ATM2 Speaker is alwayson AT O0Puts modem in data mode AT O1Takes modem out of data mode ATY0 Disable disconnection on pause ATY1 Enable disconnection on pause

Some of the HayesModem ATCommand Set

1 1 1 1 1 0 0 0 0 0 Data

...... 1B1B ......

...... 2B1Q ...... 00 01 10 11

...... 3B1O ...... 000 011 011 010

Phase Modulation Increases the Bit Signalling Rate

Quad Phase,Single Amplitude π/4, -π/4, 3π/4, -3π/4 4lev elQAM, 2B1Q

Oct Phase,Dual Amplitude 0, π/4, π/2, -π/4, -π/2, 3π/4, -3π/4, π 8lev elQAM, 3B1O

Oct Phase,Quad Amplitude, 32 levelQAM V32 modems

Amplitude Phase Diagrams Illustrating some Modulation Schemes

SPP Standard Parallel Por t 100 kbytes/sec Output software operated EPP Enhanced Parallel Por t 1Mbytes/sec Input/Ouput h/w handshakecircuits ECP Extended Capability Por t 5MBytes/sec Input/Ouput DMA with FIFO

PC Parallel Por t (Centronics) Standards

Pin SPP Host Printer D-25 1 Strobe → Pr inter Busy 2data bit 0 → 3data bit 1 → 4data bit 2 → Data lines 5data bit 3 → 6data bit 4 → Strobe 7data bit 5 → >0.1µs 8data bit 6 → 9data bit 7 → >4µs ACK 10 ACK ← 11 BUSY ← 12 PE Paper Out ← 13 SLCT ← 1 14 auto LF → 14 15 Error ← 16 INIT → 17 SLCT IN → 18-25 GRND

The Centronics Standard Interface (SPP)

Computer Pr inter Ready set

Data byte Strobe Busy set

Acknowledge Ready set

Sequence of Events within a Centronics Data Transfer

Sequence of Phases within a SCSI Transfer

Pin EPP Computer Printer D-25 1Write → 2data bit 0 ←→ 3data bit 1 ←→ 4data bit 2 ←→ 5data bit 3 ←→ 6data bit 4 ←→ 7data bit 5 ←→ 8data bit 6 ←→ 9data bit 7 ←→ 10 Interrupt ← 11 Wait ← 12 user def ← 13 user def ← 14 Strobe ← 15 user def ← 16 Reset → 17 Addr Strobe ←→ 18-25 GRND

The Centronics Enhanced Interface (EPP / ECP)

1. ﬁtting a large memorybuffer inside the printer 2. run a background print spooler 3. use a full multi-tasking system

Howtoprevent delays caused byaslowprinter

CSA Rob Williams CSA ch 11 - p 143 Pearson Education (c) 2006 Pin Master Slave 2data bit 0 ←→ 7 Byte 0 Group Command 4data bit 1 ←→ 0 6data bit 2 ←→ 8data bit 3 ←→ Byte 1 LUN (MSB) 10 data bit 4 ←→ Byte 2 12 data bit 5 ←→ Disk Logical blockaddr 14 data bit 6 ←→ Byte 3 (LSB) 16 data bit 7 ←→ 18 PARITY ←→ Byte 4 No of blocks 32 ATN → 36 BSY ← Byte 5 Vendor reser ved FlagLnk 38 ACK → 40 RST → 42 MSG ← 44 SEL → 46 C/D ← 48 REQ ← 50 I /O ← 1 50

Small Computer Systems Interface (SCSI) and Command Packet

BSY -Busy indicates that someone is currently using the bus.

SEL -Select allows the initiator to select a target and bythe target to resume an interrupted session.

C/D - Control / Data is controlled bythe target to indicate whether control or data items are being transferrred on the data bus.

I /O - Input / Output allows the target to deﬁnethe direction of the data transfer.

ATN -Attention is used bythe master to tell the slave that data is available on the bus.

MSG -Message,activated bythe target during the message phase of transfer.

REQ -Request, used bythe target device,signals to the master that data can be transmitted. It is partofthe REQ / ACK handshakepair.

ACK -Acknowledge,controlled bythe initiator to conﬁrmatransfer.

RST -Reset bus,forces all attached devices to stop activity and reset the hardware.

CSA Rob Williams CSA ch 11 - p 144 Pearson Education (c) 2006 Group 1 00 Test unit ready 13 Ver ify 01 Rezero unit 14 Recoverbuffer 03 Request sense 15 Mode select 04 For mat unit 16 Reser ved unit 05 Read blocklimits 17 Release unit 07 Reassign blocks 18 Copy 08 Read 19 Erase 0A Write 1A Mode sense 0B Seek 1B Start/stop 0F Read reverse 1C Receivediagnostic 10 Write ﬁle mark1DSend diagnostic 11 Space 1E Lockmedia 12 Inquiry

Group2 25 Read capacity 30 Search data high 26 Extend addr rd 31 Search data equal 2A Extend addr wr 32 Search data low 2E Write 7 ver ify 33 Set limits 2F Ver ify 39 Compare 3A Copy&ver ify SCSI Message Codes

7400

7400 HM82C11 7400

PC 8 bit Bus Edge Connector

Manual Port address ISA 16 bit Bus Edge Connector set up switches An extended 16 bit PC/ISA-bus Parallel I/O Card AB GND I/OCHCK Reset DRVD7 GND I/OCHCK +5V D6 RESET SD7 IRQ2 D5 +5V SD6 -5v D4 IRQ2 SD5 DQQ2 D3 -5v SD4 -12v D2 DQQ2 SD3 OWS D1 -12v SD2 +12v D0 SRDY SD1 GND I/O Ch Rdy +12v SD0 SMEMW AEN KEY IOCHRDY SMEMR A19 SMEMW AEN IOW A18 SMEMR SA19 IOR A17 IOW SA18 DAK 3A16 IOR SA17 DRQ3 A15 DAK 3SA16 DAK 1A14 DRQ3 SA15 DRQ1 A13 DAK 1SA14 DAK 0A12 DRQ1 SA13 CLK A11 REFRESH SA12 IRQ7 A10 BCLK SA11 IRQ6 A9 IRQ7 SA10 IRQ5 A8 IRQ6 SA9 IRQ4 A7 IRQ5 SA8 IRQ3 A6 IRQ4 SA7 DAK 2A5 IRQ3 SA6 T/C A4 DAK 2SA5 ALE A3 TC SA4 +5v A2 BALE SA3 14.3MHz A1 +5v SA2 GND A0 OSC SA1 GND SA0 MEMCS16 SBHE GND GND IOCS16 LA23 IRQ10 LA22 DC IRQ11 LA21 IRQ12 LA20 GND GND IRQ15 LA19 MEMCS16 SBHE IRQ14 LA18 IOCS16 LA23 DAK 0LA17 D CA B IRQ10 LA22 DRQ0 MEMR IRQ11 LA21 DAK 5 MEMW IRQ12 LA20 DRQ5 SD08 IRQ15 LA19 DAK 6SD09 IRQ14 LA18 DRQ6 SD10 DAK 0LA17 DAK 7SD11 DRQ0 MEMR DRQ7 SD12 DAK 5 MEMW +5v SD13 DRQ5 SD08 MASTER SD14 DAK 6SD09 GND SD15 DRQ6 SD10 DAK 7SD11 Stacking three 96x90mm PC/104 cards DRQ7 SD12 EISA +5v SD13 MASTER SD14 GND SD15 GND KEY Acompar ison of ISA Bus and PC/104 connectors The PCI bus can operate in twomodes:

MultiplexedMode Asingle 32 bit bus is shared byaddress and data infor mation. This increases the effectivebus width, but reduces the data rate.

Burst Mode This is the same trickthat EDO DRAM employs.After an address has been sent, severaldata items will followinquick succession. The bridge is capable of assembling "packets" of data and bursting it through to the PCI bus when ready.

Pentium CPU

System bus,66MHz, 64bits

PCI Nor th Br idge

PCI Bus,33MHz, 32bits

Disk ISA Graphics Controller South Bridge

ISA bus,8.33MHz, 16bits

Relationship of the PCI Bridge to Main Bus

Prefetch buffer

Prefetch System Posting PCI CPU buffer Bus buffer Bus Posting buffer

The PCI Bridge

CSA Rob Williams CSA ch 11 - p 147 Pearson Education (c) 2006 12V TRST TCK +12v GND TMS TDO TDI +5v +5v +5V INTA INTB INTC INTD +5v PRSTN1res res +5v I/O PRSTN2res GND GND GND GNO res res GND 1 RST CLK +5v I/O GND GNT REQ GND 5v I/O res AD31 AD30 AD29 +3.3V GND AD28 AD27 AD26 AD25 GND +3.3v AD24 C/BE 3IDSEL AD23 +3.3v GND AD22 AD21 AD20 AD19 GND +3.3v AD18 AD17 AD16 C/BE 2+3.3v GND FRAME IRDY GND +3.3V TRDY DEVSEL GND GND STOP LOCK +3.3v PERR SDONE +3.3v SBO SERR GND +3.3v PAR C/BE 1AD15 AD14 +3.3v GND AD13 AD12 AD11 ADIO GND GND AD9

AD8 C/BE 0 A07 +3.3V +3.3v AD6 AD5 AD4 AD3 GND GND AD2 AD1 ADO +5v I/O PCI Socket +5v I/O ACK 64 REQ64 +5V +5v +5v +5v

CSA Rob Williams CSA ch 11 - p 148 Pearson Education (c) 2006 Card Serial Number ABCDEFGH 100000001 200000010 300000011 400000100 500000101 600000110 700000111 800001000 900001001 10 0 0001010 11 0 0001011 12 0 0001100 13 0 0001101 14 0 0001011 15 0 0001111

Plug ’n PlaySequence

Manufacturer MID PID Adaptec 9004 36868 Compaq 1032 4146 Creative10F6 4342 Cyr ix 1078 4216 Epson 1008 4104 HP 103C 4156 Intel 8086 32902 Matsushita 10F7 4343 Mitsubishi 1067 4199 Motorola 1057 4183 NCR 1000 4096 Toshiba 102F 4143 Tseng Labs 100C 4108 Example Plug and PlayIdentity Numbers

CSA Rob Williams CSA ch 11 - p 149 Pearson Education (c) 2006 GND GND D3 CD DET 1 D4 D11 D5 D12 D6 D13 D7 D14 CD EN 1D15 A10 CD EN 2 OUT EN REFRESH A11 IOR A9 IOW A8 A17 A13 A18 A14 A19 WE /PRG A20 READY /BUSY A21 +5v +5v V 1V2 pp pp A16 A22 A15 A23 A12 A24 A7 A25 A6 RFU A5 RESET A4 WAIT A3 INPACK A2 REG SEL A1 SPKR A0 STSCHG D0 D8 D1 D9 D2 D10 IOIS16 CD DET 2 GND PCMCIA Interface GND

CPU

A0-A31

4Gbyte Memor y

Fully populated main memory

256 bytes CPU registers - 0.5 ns

CPU Control Unit words - 2 / 4 bytes 16 Kbytes LI Cache Memory-1ns

Pr imaryCache Controller lines - 32 bytes 256 Kbytes LII Cache Memory-2.5 ns

Secondar y Cache Controller lines - 32 bytes 512 Mbytes Main Memory-10ns

Memor y Management Unit pages - 4 Kbytes 16 Mbyte Disk Cache - 10 ns

Device Controller blocks - 4 Kbytes 80 Gbytes Disk Storage - 10 ms

Administrativestaff ﬁles - Mbytes 20 Tbytes Tape Backup - 10 min

Memor y Perfor mance Hierarchy

CSA Rob Williams CSA ch 12 - p 152 Pearson Education (c) 2006 Facility Sizedevice Unit cost, ££/Mbyte DRAM 64 MB SDRAM 168 pin DIMM 40 0.6 32 MB EDO 72 pin SIMM 50 1.6 SRAM 256 KB/10ns SRAM chip 2 64 SCSI PCI card 180 Hard Disk 10GB IDE 110 0.01 10GB SCSI 250 0.025 CD-ROM 650 MB 32x IDE 60 0.12 R CD-RW650 MB 2x IDE 200 0.3 R WORM disk 0.75 RW disk 2.50 Jazz 1 GB drive200 1GBdisk 65 0.25 R Zip 100 MB drive60 100 MB disk 15 0.75 R DAT4GB SCSI dr ive350 4GBtape 2.5 0.09 R Floppy1.4 MB dr ive15 1.4 MB disk 0.5 11 R

Memor y costs

Memor y location

CPU time Memor y access plot, showing locality effects

x 4 5

nde 6 7 wi 8

Ro 9 10 . . .

row0 row1 row2 row3 row4

Array indexing with memorylay out of array data

CSA Rob Williams CSA ch 12 - p 154 Pearson Education (c) 2006 #include #include #include #define MAX 1000 clock_t times(struct tms* b); main () { int i, j; int big[MAX][MAX]; int sum, start, middle, end; struct tms tbuff; times( &tbuff); start = tbuff.tms_utime; for(i=0; i

rob [80] cc cache .c -o cache rob [81] cache First run time is 150 Second run time is 310 rob [82]

Results from the Cache Test

Estimate:21x5ns x 106 + 13 x 5ns x 103 = 105ms

Alter nativeaccess patterns (strides) for a 2-D array

256 Kbyte Cache Control Unit 2ns SRAM Cache

System Bus

I/O Subsystem 512Mbyte 15ns DRAM Main Memory

Cache Memoryand Controller Unit

1. Folded address space,also known as Direct Mapping 2. Associative(content addressable) memory 3. Hashed mapping

Mapping Addresses from Main to Cache Memory

CSA Rob Williams CSA ch 12 - p 158 Pearson Education (c) 2006 Main Memory 11111 111 11 11111 111 10 11111 111 01 11111 111 00 11111 110 11 11111 110 10 11111 110 01 TA G Memor y Cache Memory 11111 110 00 111 110 101 100 011 10100 101 11 010 10100 101 10 001 10100 101 01 000 10100 101 00 10100 100 11 4 0 11 10 01 00 10100 100 10 10100 100 01 10100 100 00

00000 111 00 00000 001 11 00000 001 10 00000 001 01 00000 001 00 00000 000 11 00000 000 10 00000 000 01 00000 000 00 Address

Address Folding for Direct Mapped Cache

CSA Rob Williams CSA ch 12 - p 159 Pearson Education (c) 2006 Main Memory 11111 111 11 11111 111 10 11111 111 01 11111 111 00 11111 110 11 11111 110 10 11111 110 01 Status TA G Memor y Cache Memory 11111 110 00

10100 111 11 10100 110 10 10100 101 01 10100 100 00 10100 011 11 7 0 11 10 01 00 10100 010 10 10100 001 01 10100 000 00

00000 111 00 00000 001 11 00000 001 10 00000 001 01 00000 001 00 00000 000 11 00000 000 10 00000 000 01 00000 000 00 Address

AssociativeCache

A31-A24

TA G 01

Checking the Address in AssociativeMemor y

CSA Rob Williams CSA ch 12 - p 160 Pearson Education (c) 2006 1. on start-up of a newprogram 2. when the cache is too small to hold the activeexecution set 3. cache line conﬂict in a direct mapped cache. Causes of Cache Misses

Fr ames Swap Area

Retr ieval

Main of pages Disk Memor y

Vir tual memor y scheme for main memoryoverﬂow

User Code

Page# Offset logical addr

Page Table

31 0

Page Table Register

User Data 31 0

Fr ame# Offset Memor y physical addr

Vir tual memor y logical page into physical frame address translation

vir tual address SRAM MMU vir tual address Cache physical address SRAM Cache MMU physical address

System Bus System Bus

I/O Subsystem I/O Subsystem DRAM DRAM Main Memory Main Memory

Physical addressing cache (Pentium) Vir tual addressing cache (ARM)

Alter nativepositions for the memorymanagement unit

FFFF FFFF FFF FFFF 4Gbyte Code Data Segment Segment Stack Segment

SS Base

Data Segment Stack Segment DS Base

Code frame Segment

Logical Addressing page 000 0000 Programmers’ View CS Base 0000 0000 Physical Addressing Vir tual Addressing Hardware View O/S View The relation between different address designations

Human Hair about 50µm 100km/hr

SmokePar ticle Finger print Smear 5µm 3µm Oxide Layer2.5µm

Environmental obstacles with R/W disk heads

Data sectors along a track Voice Coil actuator

Read/wr ite head

Schematic DiagramofHard Disk Unit

dr ive_capacity = no_of_surfaces x no_of_tracks x no_of_sectors x size_of_sector

CSA Rob Williams CSA ch 12 - p 164 Pearson Education (c) 2006 Acomputer system having 2 Mbytes of RAM has hard disks with the following character istics: Rotational speed: 3600 rpm Tr ack capacity: 16384 bytes Heads/cylinder : 10 Head movement time,track totrack:20 ms Av erage seek time: 50 ms Howlong does it taketodump memoryonto disk? Assume the disk is empty. 3600r pm =60rps rotational period = 1/60 secs = 1000/60 msec = 16.66 msec = 17 msec latency = 8.5 msec data rate = 16 Kbytes / 17 msec = 1 Mbyte/sec ﬂowtime for 2 Mbyte = 2000 msec = 2 sec 2Mbyte needs 128 tracks or 12.8 cylinders ie 13 head movements tot time = head movement (seeks) + rotnl delays (latencies) + data ﬂowtime =1x50+12X20+13 X 8.5 +2000 =2314 msec Estimating Hard Disk Data RetrievalTime

Disk Perfor mance Speciﬁcation Tr ack toTrack Seek 1 ms Av erage Seek <9ms Maximum Seek 20 ms

Av erage Latency 5.77 ms Rotation 5400 rpm

Controller overhead < 0.3 ms Star t time 7.3 sec

Computer interface rate < 66.7 Mbytes/sec Media read/write rate < 27.8 Mbytes/sec

Sectors per track266 - 462 Cylinders (tracks per surface) 17549 Bytes per sector 512 Data zones per surface 16

Integrated buffer size2Mbytes Memor y type SDRAM

Model 90650U2 90845U 91020U3 91360U4 92040U6 92040U8 Capacity (Gbytes) 6.5 8.45 10.21 13.61 20.42 27.23 Heads 2 33 4 6 8 Disks 1 22 2 3 4

ASpeciﬁcation Table for Maxtor Hard Disks CSA Rob Williams CSA ch 12 - p 165 Pearson Education (c) 2006 200 Queue SCAN 180 97 160 179 140 35 Tr ack FCFS 80 120 12 Number100 190 80 50 60 51 40 121 SSTF 122 20

Time Disk Access Scheduling Techniques

81 Av erage inter-track seek distances

34 29

FCFS SSTF SCAN Compar ison of Disk Scheduling Techniques

...... CD data Spiral and Magnetic Disk Concentric Tracks

Polycarbonate rotating disk (1.2mm) beam light (1000r pm) splitter detector

Laser focusing emitter Optical disk read head

tracking

Paper Label 1.6 µm Lacquer Reﬂectivecoating Upper dielectric Recording layer

Lowerdielectr ic 1.2 mm

Polycarbonate Tr ack Disk grooves

Hard Coating

Laser beam CD-RWdisk structure

Application User

Systems Admin

HLL Programmer

Systems Programmer Different jobs,different viewpoints

H/W Engineer

the switch is closed can the valve open

FABWrite(num, B_8255); printf("switch

move EAX, 04H lea EBX,string call pr

92 E6 EA 0F C2 66 3F A1 92 E6 EA 0F C2

1001 0010 1110 0110 1110 1010 0000 1111

......

Same device,manydifferent viewpoints

rob@milly [80] ls -alt total 6702 drwx--x--x 76 rob csstaff 7168 Aug 717:57 .. drwx--x--x 3 rob csstaff 3072 Aug 715:55 . -rwx------1 rob csstaff 42544 Aug 614:57 #testparam.c# -rwx------1 rob csstaff 42545 Aug 514:55 sort.c -rwx------1 rob csstaff 9503 Aug 514:35 jeffsm.c -rwx------1 rob csstaff 9525 Aug 514:31 jeffsm.c˜ -rwx------1 rob csstaff 5144 Aug 314:31 a.out -rwx------1 rob csstaff 17851 Aug 314:31 ch_9c.txt -rwx------1 rob csstaff 17890 Aug 314:30 ch_9c.asc -rwx------1 rob csstaff 21180 Aug 217:28 ntime.c rob@milly [81]

Tr aditional text-only Unix directorylisting using ls

Header cat header ch_13c|geqn|gpic|groff -fH|lp -dps -oduplex

AUnix process pipeline to for mat and print text used bysystems administrators

rob@milly [80] /etc/mknod pipe1 p rob@milly [80] /etc/mknod pipe2 p rob@milly [80] /etc/mknod pipe3 p rob@milly [81] ls -al pipe*

prw------1 rob csstaff 0 Oct 14 18:39 pipe1 prw------1 rob csstaff 0 Oct 14 18:39 pipe2 prw------1 rob csstaff 0 Oct 14 18:39 pipe3

rob@milly [82] cat letter.tmp >! pipe1 & rob@milly [82] cat pipe1 >! pipe2 & rob@milly [82] cat pipe2 >! pipe3 &

Demonstrating Unix named pipes

CSA Rob Williams CSA ch 13 - p 172 Pearson Education (c) 2006 #!/bin/sh # #Script converts sar data into graphs - PJN 20/10/1998 # #Extend the PATH to include gnuplot PATH=${PATH}:/usr/local/bin ; export PATH #Procedure to remove non-data lines from log file. remclutter() { grep : |grep -v free |grep -v % |grep -v / |grep -v restarts } #Procedure to pad numbers with zeroes to 2 digits. padnum() { NUM=$1 while [ `/bin/echo "${NUM}\c" | wc -c` -lt 2 ]; do NUM="0${NUM}" done echo $NUM } #Procedure to convert time of day timestamps to decimal days. parsetimes() { DAY=0 OLDHOUR=23 while read TIME DATA; do if [ "$DATA" = "" ]; then DATA="0 0 0 0 0 0 0 0 0 0 0 0" fi HOUR=ècho $TIME | cut -f1 -d:` MIN=ècho $TIME | cut -f2 -d:` if [ $HOUR -lt $OLDHOUR -a "$MIN" = "00" ]; then DAY=èxpr $DAY + 1` fi PTIME=èxpr $ \( \( $HOUR \* 60 $ + $MIN \) \* 100 \)/1440` PTIME=${DAY}.`padnum $PTIME` echo "$PTIME $DATA" OLDHOUR=$HOUR done } #Procedure to get data from a named column. getcol() { tr -s ’ ’ ’ˆ’ | cut -f1,${1} -d\ˆ | tr ’ˆ’ ’ ’ } Continues

CSA Rob Williams CSA ch 13 - p 173 Pearson Education (c) 2006 #Determine the i/p and o/p files (for last week’s data). WEEK=`date +%W` WEEK=`expr $WEEK - 1` if [ $WEEK -eq -1 ]; then WEEK=52 fi WEEK=`padnum $WEEK` DATAFILE=/var/adm/sa/sa$WEEK OUTFILE=/tmp/$$.graphs #Process virtual memory data from sar log. echo "VM usage" sar -f $DATAFILE -r > /tmp/$$.sar cat /tmp/$$.sar | remclutter | parsetimes > /tmp/$$.sar-f rm /tmp/$$.sar cat /tmp/$$.sar-f | getcol 2 > /tmp/$$.freemem cat /tmp/$$.sar-f | getcol 3 > /tmp/$$.freeswap (cat << EOF set term postscript set time set xtic 0,0.5 set title "`hostname` virtual memory usage" f(x) = (x * 512 ) / 1048576 g(x) = (x * `pagesize` ) / 1048576 plot [0:7] []\ "/tmp/$$.freemem" thru g(x) title "Free RAM MB" with lines,\ "/tmp/$$.freeswap" thru f(x) title "Free Swap MB" with lines EOF )|gnuplot > $OUTFILE rm /tmp/$$.freemem /tmp/$$.freeswap /tmp/$$.sar-f lp -d ps $OUTFILE sleep 60; rm $OUTFILE exit AUnix administration script for perfor mance statistics

CSA Rob Williams CSA ch 13 - p 174 Pearson Education (c) 2006 #include int bsort(char* pc[ ], int n ) { int gap, i, j; char* pctemp; for (gap = n/2; gap > 0; gap /= 2) for (i = gap; i < n; i++) for(j = i-gap; j>= 0; j -= gap) { if (strcmp(pc[j], pc[j+gap]) <= 0) break; pctemp = pc[j]; pc[j] = pc[j+gap]; pc[j+gap] = pctemp; } } void main(void) { int i; char* names[ ] = { "Monday", "Tuesday", "Wednesday", "Thursday", "Friday", "Saturday","Sunday"}; i=bsort(names, 7); for(i=0; i<7; i++) { printf("%s0, names[i] ); }; }

Example HLL algorithm - BubbleSor t forthe software engineer

for( i=0; i<10; i++ ) { IT doD( ); }

10 x=0; * while (x < 10) { do D doD( ); x++; }

SEL if (x > 0) { doE( ); X>0 }else { doF( ); do F do E }

Str ucture Char t representations of SEQ, IT & SEL

BOOL unsigned 1bit value char unsigned 8bit value WCHAR unsigned 16 bit value BYTE unsigned 8bit integer shor t signed 16 bit integer WORD unsigned 16 bit integer int signed 32 bit integer LONG signed 32 bit integer unsigned unsigned 32bit integer DW ORD unsigned 32 bit integer ﬂoat IEEE 32 bit real double IEEE 64 bit real Data types for C/C++, popular languages with systems programmers

do C L1: JZ L2

....

CALL doD JMP L1 L2: y IT ? ------MOVCX,10 n L3: .... do D CALL doD LOOP L3

------

y n CMP EAX,12 SEL ? JGE L4 CALL doE JMP L5 do E do F L4 CALL doF L5

FlowChar t representation of SEQ, IT & SEL

User Program

HLL Librar y Routines

Operating System Procedures

Microcode Interpreter Co-processor Units

Digital Logic Circuits

Electronic Devices

Amulti-levelcomputer functional interaction

CSA Rob Williams CSA ch 13 - p 178 Pearson Education (c) 2006 1. instruction mnemonics into binarycodes 2. user deﬁned symbols into constant numbers 3. numbers from base to base,nor mally decimal to binary 4. symbolic position labels into physical addresses

Tr anslation activities of an assembler

Symbol Type Value

ADD opcode $FF

ADDAopcode

SUB opcode

MOVE opcode

star t deﬁned

exit undeﬁn

loop1 deﬁned

spx deﬁned

spr ite deﬁned

Symbol Table Entries

Pre- processor Error repor t

Source Lexical Token ﬁle analysis list

Error repor t Symbol Syntactic Inter mediate table analysis code

Error repor t Code Machine Gen code

Stages of Compilation

Code Optim

Better Machine code

IBM DEC Cold Water Front-end processor

Mainframe Mini computer computer

Local Personal Area Networ k computer Evolution of computing provision

ﬁle transfer email using ftp Displaying LAN trafﬁc using Sun’sperfmeter CSA Rob Williams CSA ch 14 - p 182 Pearson Education (c) 2006 802.3 CSMA/CD 802.4 Token Bus 802.5 Token Ring 802.6 MAN 802.11 Wireless LAN 802.12 100 Mbps LAN

Some of the IEEE 802 standards committees

Ser ver

Packetsignal 70Ω 70Ω Terminator //////// \\\\\\\\ Terminator 10Mbps Ethernet

Workstations Tr aditional ofﬁce bus LAN facility

Ser ver workstation

Switching Hub

Star topology,switched hub,ether net

Central Hub

Switching Switching Hub Hub

workstations Star topology with hierarchical hubs

12345678 1 2 3 6 4 5 7 8 Connections to an RJ45 LAN Plug

RJ45 socket 10BaseT Thin Ether net 10Base2 cable SMC 10Base5 UltraChip socket

BNC BNC 10Base2 Teepiece socket connector

70 Ω stub ter minator

Anetwor k interface card with 10Base2 & 10BaseT connectors

TCP/IP Software

Device Driver

Networ k Controller Hardware Ser ial Networ k interface

H/w and s/w layers to manage the LAN Interface

Data 0 1 0 0 1 1 0 1

XOR Data +0.7v Out 10Mbps -0.7v

Manchester Encoding for Data and Clock

rising edge - 0, dropping edge - 1 10101010 10101010 10101010 101010100 101010100 101010100 10101010 Flag Bytes ↓ 10101010 10101010 10101010 10101010 10101011 [Ethernet_packet_body....]

CSA Rob Williams CSA ch 14 - p 186 Pearson Education (c) 2006 10Base5 10Mbps,ThickEther net 500m segment length, minimum tap separation 2.5m, maximum of 4 repeaters, 50 Ω coax cable vampire tap (Media Access Unit) 10Base2 10 Mbps,Thin Ethernet 200m (165m) segment length, minimum tap separation 0.5m, maximum of 4 repeaters, 70 Ω coax cable BNC T-piece bayonet connection 10BaseT 10 Mbps,Switched Ethernet 100m segment length, end-to-end, simplex 100 Ω AWG24 twisted pairs cable RJ45 telecom jack 100BaseT 100 Mbps, 205m segment length, end-to-end, simplex 100 Ω AWG24 twisted pairs cable 100BaseF 100 Mbps Fibre Ether net 2000m segment length end-to-end, simplex optic ﬁbres

Various ethernet media standards

tbit = 0. 1µs 50 N = = 500 bits packet 0. 1 500 N = = 62. 5 ~ = 64 Bytes Bytes 8 Tr ansit Time Star t End S2 LAN Received Length metres Collision

Collision warning

S1 Tr ansmitted Time, µsec Star t End

Collision Detection and Transit Times for Ethernet

CSA Rob Williams CSA ch 14 - p 188 Pearson Education (c) 2006 Binar y Tr inar y 0000_0000 +-00+-T 0000_0001 0+-+-+T 0000_0010 +-0+-0T 0000_0011 -0++-0T 0000_0100 -0+0+-T 0000_0101 0+--0+T 0000_0110 +-0-0+T 0000_0111 -0+-0+T 0000_1000 -+00+-T 0000_1001 0-++-0T 0000_1010 -+0+-0T 0000_1011 +0-+-0T 0000_1100 +0-0+-T 8B6T Coding 0000_1101 0-+-0+T 0000_1110 -+0-0+T 0000_1111 +0--0+T ...... 1111_1111 +0-+00T

Destination

Address

(48 bits)

Source

Address

(48 bits) Length of Data Field

Data 0-1500

Padding 0-46

CRC error detection

Inter nal Str ucture of an Ethernet Data Packet

CSA Rob Williams CSA ch 14 - p 190 Pearson Education (c) 2006 31 23 0 Class A Networ k Subnet Host 1•0•0•0 - 0 127•255•255•255 15 Class B Networ k Subnet Host 128•0•0•0 - 1 0 191•255•255•255 7 Class C Networ k Host 192•0•0•0 - 1 1 0 223•255•255•255

Class D 224•0•0•0 - 1 1 1 0 Multicast Address 239•255•255•255

Class E 240•0•0•0 - 1 1 1 1 Reser ved 247•255•255•255

Local 127•0•0•0 loopback 0 1 1 1 1 1 1 1

The 5 For ms of IP v4 numbers and their ranges

rob@milly [20]/usr/sbin/arp -a Net to Media Table Device IP Addr Mask Flags Phys Addr ------hme0 lentil 255.255.255.255 00:00:8e:06:07:cf hme1 pb4 255.255.255.255 00:80:5f:cc:5c:20 hme0 rice 255.255.255.255 00:00:8e:06:07:e9 hme0 beans 255.255.255.255 00:00:8e:06:07:c4 hme1 ivor 255.255.255.255 08:00:20:1a:9d:16 hme0 carrot 255.255.255.255 00:00:8e:06:07:e6 hme1 router8 255.255.255.255 08:00:20:19:1c:9a hme0 hops 255.255.255.255 00:00:8e:06:07:e3 rob@milly [21]

ARP table,translating IP addresses into MACnumbers

#Internet host table # 127.0.0.1 localhost 164.11.10.206 olveston loghost 164.11.8.16 egg ns0 164.11.253.2 sister ns1 164.11.8.99 ada ns2 164.11.10.5 riff ns3

rob@olveston [21]

Host table,translating acronym into IP addresses

user data Appln

Appln user data TCP header

TCP Appln data IP header

IP TCP Ether Appln data header header dr iver

Ether IP TCP Ether Ether net Appln data header header header trailer

ALay ered description of networ king software

CSA Rob Williams CSA ch 14 - p 192 Pearson Education (c) 2006 rob@olveston [20]df /(/dev/dsk/c0t0d0s0 ): 751760 blocks 216981 files /usr (/dev/dsk/c0t0d0s3 ): 292766 blocks 177111 files /proc (/proc ): 0 blocks 915 files /dev/fd (fd ): 0 blocks 0 files /var (/dev/dsk/c0t0d0s4 ): 264238 blocks 97421 files /tmp (/dev/dsk/c0t0d0s5 ): 165454 blocks 100191 files /cache (/dev/dsk/c0t0d0s6 ): 53882 blocks 48381 files /local (/dev/dsk/c0t0d0s7 ): 4730618 blocks 1264846 files

/usr/misc (thalia:/usr/misc ): 938032 blocks 273054 files /tutorials (milly:/tutorials ): 282752 blocks 93369 files /home/staff/cs (sister:/home/staff/csm/csstaff): 4942096 blocks 513071 /var/mail (mailhub:/var/spool/mail): 3582944 blocks 974994 files /projects/staff (ada:/projects/staff): 1408240 blocks 729518 files /projects/rob (ada:/projects/rob ): 218704 blocks 95166 files /WWW/Documents (www:/var/htdocs ): 2032720 blocks 582750 files /WWW/Servlets (www:/opt/local/JSDK/servlets): 3539408 blocks 344000 files

rob@olveston [21] remote hosts local disk drive

Inspecting the state of a Unix ﬁle systems using df

Installing a virtual driveusing Windows XP

Ser ver

LAN 1

Gateway Workstations LAN 2

Interconnecting LANs using a gateway

sockettosocket communication

Socketcommunication between remote processes

socket( ) create a socket socket( ) create a socket

bind( ) name the socket connect( ) connect to server

listen( ) specify queue

accept( ) wait for call accept connection spawn newsocket

send( )/recv( ) send( )/recv( ) transfer data transfer data

closesocket( ) closesocket( ) close socket close socket

Communication with Client-Serverconnection-based (STREAM) sockets

CSA Rob Williams CSA ch 14 - p 196 Pearson Education (c) 2006 SOCKET socket(int af, int typesock, int protocol) int bind(SOCKET mysock, const struct sockaddr "psock, int nlength) int listen(SOCKET mysock, int qmax) int connect(SOCKET yoursock, const struct sockaddr *sname, int nlength) SOCKET accept(SOCKET mysock, struct sockaddr *psock, int *addrlen) int send(SOCKET yoursock, const char *pdbuff, int dblen, int flags) int recv(SOCKET mysock, char *pdbuff, int dblen) int closesocket(SOCKET mysock)

Win32 SocketFunction Calls

socket( ) socket( ) create a socket create a socket

bind( ) bind( ) name the socket name the server

recvfrom( ) sendto( ) waiting transfer data accept data

recvfrom( ) sendto( ) waiting retur n data accept data

closesocket( ) closesocket( ) close socket close socket

Communication with Client - Serverconnection-less (DGRAM) sockets

3 LAN

6 WAN 1 WAN LAN

2 LAN

WANs givelong distance interconnection for LANs

TCP/IP - are the essential protocols for the Internet

20/21 por t Port map UDP TCP (cat /etc/services)

06 ICMP 02

17 protocol IP Routing Table /usr/sbin/netstat -rn payload type 0800 ARP

0806 Ether ARP Table Dr iver (/usr/sbin/ar p -a)

Networ k Interface

The TCP/IP StackatWor k

Number Protocol 02 ICMP 06 TCP 17 UDP

IP Protocol Field Values

CSA Rob Williams CSA ch 15 - p 201 Pearson Education (c) 2006 > cat /etc/services tcpmux 1/tcp echo 7/tcp echo 7/udp discard 9/tcp sink null discard 9/udp sink null systat 11/tcp users ftp-data 20/tcp ftp 21/tcp telnet 23/tcp smtp 25/tcp mail time 37/udp timserver name 42/udp nameserver whois 43/tcp nicname # usually to sri-nic gopher 70/tcp #Internet Gopher finger 79/tcp www 80/tcp http # World Wide Web www 80/udp hostnames 101/tcp hostname # usually to sri-nic sunrpc 111/udp rpcbind sunrpc 111/tcp rpcbind TCP portnumbers and their services from /etc/services

Sync Preamble 15 7 0 Source port Header Version SFD length TOS Destination Por t Destination Length (Bytes) Tr ansmitted Sequence count Address (Identity) Sequence number

(48 bits) Flags Acknowledged TTL Source max hops Protocol Sequence number Header Address Header checksum length Flags (48 bits) IP Source Tx window size Length of Data Field address (32 bits) TCP checksum IP Destination Urgent pointer Optional address (32 bits) facilities

Pa yload Type TCP Frame User (Data Payload) Pa yload

IP Frame (Data Payload) IP Header Structure TCP Header Structure

CRC Ether net header IP header TCP header User Data error detection

Ether net Packet

Ether net, IP,TCP encapsulation

multiple data packets sent all ACKed Flowcontrol using a data sent no ACKs four packetbuffer so Tx pauses

ACKs received so Tx resumes

Tr ansmitter Receiver

Router

Networ k 1 Networ k 5 Differentiating Repeaters,

Br idge Br idges,and Routers

Networ k 1 Networ k 2

Repeater Networ k 1 Networ k 2

CSA Rob Williams CSA ch 15 - p 204 Pearson Education (c) 2006 rob@olveston [20] cat /etc/hosts #Internet host table # 127.0.0.1 localhost 164.11.253.47 olveston loghost 164.11.8.16 egg ns0 164.11.253.2 sister ns1 164.11.8.99 ada ns2 164.11.10.5 riff ns3 rob@olveston [21] rob@olveston [21] netstat -rn Routing Table:

Destination Gateway Flags Ref Use Interf ------127.0.0.1 127.0.0.1 UH 0 503 lo0 164.11.253.0 164.11.253.47 U 3228 hme0 224.0.0.0 164.11.253.47 U30hme0 default 164.11.253.1 UG 0 14297 rob@olveston [22]

Destination Status Flags Local Recommended host or U-upand OK Ether net ﬁrst hop networ k G-gateway/direct connection por t H-host / networ k address

Unix netstat utility showing the routing table

RIP IP #router #ticks IP #router #ticks Operation Number hops (56ms) Number hops

1st hop 2nd hop RIP packetﬁelds

Region IP Numbers Reserved Europe 194•000•000•000 -195•255•255•255 NAmer ica 198•000•000•000 - 199•255•255•255 SAmer ica 200•000•000•000 - 201•255•255•255 Paciﬁc Asia 202•000•000•000 - 203•255•255•255

CIDR IP number allocations

address ar p DNS User book user table IP number MACnumber name host id

Rober t Williams rob.williams 164.11.253.47 08:00:20:8E:86:5F UWE, Bristol, UK olveston.uwe.ac.uk

Identiﬁer translation required for transmitters

CSA Rob Williams CSA ch 15 - p 206 Pearson Education (c) 2006 rob@milly [10] ypcat hosts | more 164.11.13.5 gecko 164.11.9.89 TT89 164.11.235.52 saar 164.11.243.225 valdoonican 164.11.10.56 StaffPC56 164.11.11.73 blackwell 164.11.253.47 olveston 164.11.8.203 dialin63 164.11.8.200 dialin60 164.11.13.15 wallaby 164.11.235.87 shannon 164.11.253.158 new_pb2 164.11.243.249 naqqara 164.11.194.4 linux04 164.11.10.45 drjones 164.11.11.71 wesley 164.11.235.122 siphon --more-- Inspecting the local hosts ﬁle

•org •net •com •edu •gov •mil •fr •de •uk •us

•gov •ac •co

•uwe

•csm

Hierarchical Domain Naming Structure (DNS)

CSA Rob Williams CSA ch 15 - p 207 Pearson Education (c) 2006 rob@milly [33] cat /etc/resolv.conf domain csm.uwe.ac.uk search csm.uwe.ac.uk uwe.ac.uk nameserver 164.11.8.16 nameserver 164.11.253.2 nameserver 164.11.253.11 nameserver 164.11.8.99

rob@milly [34] /usr/sbin/nslookup Default Server: egg.csm.uwe.ac.uk Address: 164.11.8.16

>smilodon.cs.wisc.edu Server: egg.csm.uwe.ac.uk Address: 164.11.8.16

Non-authoritative answer: Name: smilodon.cs.wisc.edu Address: 128.105.11.80 > ˆD rob@milly [35]

Using the DNS name look-up facility

URL = Protocol identifier/Machine name/file path

Tags Functions . . . Page delimiters . . . Page heading . . . http title (invis) . . . Main text delimiters Body text font selection . . Font type,size&colour . . . Subheading at levelx . . . Embolden font . . . Italicizefont

. . . Unordered list

. . . Ordered list . . . Menu

List star t
Break text, \n

Newparagraph

Horizontal line

 . . .

Noﬁll, prefor matted

Inser t image file here [Press] set up a Hyperlink Star ter set of HTML tags CSA Rob Williams CSA ch 15 - p 210 Pearson Education (c) 2006 http proxy [URL] - The proxy command allows a proxy HTTP servertobedefined which will be used in subsequent client commands.Providing a URL argument sets the proxy server. Setting the proxy to an empty string turns the proxy feature off. http head url-The head command retrievesthe HTTP header for the document located at URL. http get urlfile - The get command retrievesthe document located at URL. The body of the document is written to file.The command returns the HTTP header as descr ibed forthe http head command above . http post urlfilename_1 filename_2 - The post command posts the document in filename_1 to the location URL. The body of the returned document is written to filename_2. The command returns the HTTP header as described for the http head command above . http put URL file - The put command copies the file into the URL. The command returns the HTTP header as described for the http head command above . http delete URL - The delete command deletes the document at the URL. The command returns HTTP status infor mation. The %X variables are substituted before a script is evaluated: %A - The networ k address of the client. %P - The URL path requested bythe requestor. %S - The search path contained in the URL path. Examples from Hypertext Transmission Protocol (http)

Connection closed by foreign host.

Attaching to a web serverbytelnet for an on-line session

rob@localhost> telnet www.cems.uwe.ac.uk 80 Trying 164.11.8.19... Connected to www.cems.uwe.ac.uk (164.11.8.19). Escape character is ’ˆ]’. GET /˜rwilliam/http_spook

Hello, and welcome to the target file in this telnet/http file GET exercise.

Connection closed by foreign host. rob@localhost>

Using http/GET in place of ftp/get

Multiple Google ser vers

Client broswer

Indexser vers each with 80 dual Pentium cards with 2 GB DRAM & 80 GB IDE disks in cooled racking Schematic of Google search engine

Fetched pages Quer ies

Crawlers Parser

URL Repositor y of web pages ser ver (compressed byzlib)

Anchors Lexicon wordID Indexer converter Document Word indexstore indexstore inverted ﬁle Index URL resolver sor ter

Links Quer y Searchers allocate

hits

Filter and PageRank sor ter

results list

Google data-ﬂowactivity diagram

transfor mation Presentation layer 6 data for matting

5 computer dialogue Session layer control

Tr anspor t layer 4 message <=> packets

Vir tual circuit Networ k layer 3 routing control packetsequencing

2 Flowcontrol Link layer error/lost blockdetection

1 Voltage levels Physical layer plug pinouts

Communication sub-net layers

ISO SevenLay erOSI Model

Application Application 7

Presention 6

Session 5

TCP or UDP Tr anspor t 4

IP Networ k 3

Link 2 Networ k Physical 1

Compar ison of TCP/IP with ISO sevenlay ers

IXC

Tr unk lines IXC IXC Tr unk Exch BrrBrr BrrBrr! LXC LXC Local Exch

POTS,the traditional telephone networ k

1209 1336 1477 Hz

1 2 3 697

4 5 6 770

7 8 9 825

∗ 0 # 941

DTMF,touch-tone signalling key pad

...... 8bits ...... ev ery 125 µs ...... 01100101 00111100 11100101 00111101 ...... Analogue Digital .. ... signal signal Line ...... Interface ...... Card

Digitization of telephone speech signals

alue 80

64 AVin V = out 1 + log A 48 Output v where A = 87.6 32 16

V/16V/8 V/4 V/2 VV/1 Input Speech Signal

Non-linear voice compression for transmission

2. 048M 2 x 106 103 = = = 32 channels 64k 64 x 103 32

discrete voice 0 0 1 channels 1 2 2 3 3

30 channel TDM trunk line Multiplexor Demultplx

28 28 29 29 30 30 31 1frame 125 µs 31

30 conversations C1 1 2 3 4 5 6 7 C2 24 25 26 27 28 29 30 C1 2 3 4 5 6

1slot 10110110 8bit speech sample,3.9 µs

Time Divison Multiplexing (TDM) for trunk line sharing

CSA Rob Williams CSA ch 16 - p 218 Pearson Education (c) 2006 0 Înput 1 2 Voice 3 Control Channels 4 5 Computer 6 Signal 7 8 Channel 9 0 1 2 3 4 5 6 7 Ouput 8 Voice 9 Channels Space division circuit switching with control processor

125 µs time frame 1 frame 2 frame 3 frame 4 frame 5 5 2 8 5 2 8 5 2 8 5 2 8 5 2 8 8 0 4 8 0 4 8 0 4 8 0 4 8 0 4

TDM Bus

0 0 1 1 2 2 3 Input TDM Output 3 4 4 5 Voice Controller Voice 5 6 6 7 channels channels 7 8 8 9 9

Time Division Circuit Switching

CSA Rob Williams CSA ch 16 - p 219 Pearson Education (c) 2006 300 Hz 30 KHz 3MHz 300 MHz 30 GHz 3THz 300 THz VLF LF MF HF VHF UHF SHF EHF IR Vis UV coax gsm optic cable ﬁbre twisted pair Bands within the electromagnetic spectrum

...... Carr ier ...... frequency ...... Amplitude ...... Modulated ...... Frequency ...... Modulated ...... Phase ...... Modulated ...... 100111100011110001111110000

Radio wavemodulation using amplitude,frequency and phase techniques

Switch Switch Switch

Radio cell equipment and interconnection

0.1 - 0.3 GHz VHF Terrestr ial television & radio 0.3 - 1.0 GHz UHF Television, GSM mobile (0.9 GHz), packetradio,pagers 1.0 - 2.0 GHz Navigation aids,GSM mobile (1.8 GHz) 2.4 - 2.5 GHz Shor t range radio control (Bluetooth) 3.4 - 3.5 GHz Neighbourhood antennae Utilization of radio frequency bands

Cells with a repeat 7 patternofradio frequencies

2 3

3 2

Acell arrangement with only repeat 4 pattern

CSA Rob Williams CSA ch 16 - p 222 Pearson Education (c) 2006 Sound Class 1 CRC switch Convl Coding Re-order ing Speech Inter leaving PA Encoder Cipher ing ADC Burst assem DA C MXR Listener GMSK_mod Filter Noise

Speech Equalizer Encoder Burst Disass LNA DA C De-cipher ADC MXR Extra De-inter leave Filter polation Decoding Class 1 CRC Voice Speech Radio Radio Codec Processing Sig Proc Modem Unit

gsm handset signal processing schematic

Control Processor Protocol LCD Voice TDMA timer Stack display Codec User ADC Interface Peripherals DA C Control Memor y : DSP Speech RAM Ke ypad Encoder FLASH ROM Equalizer Radio Burst Disass Modem De-cipher DA C Analog Baseband De-inter leave Decoding SIM card ADC Class 1 CRC PLL

Radio Transceiver Unit

gsm handset functional modules

T Voice C TS C Voice T Gd 577 µstime slot 3 57 1 26 1 57 3 8.25bits

Packetstr ucture forgsm voice transmissions

Vir tual Datagram Circuit Switching Circuit Switching PacketSwitching

Circuit Path Set up Arranged Packets Sent

Voice Packets data Tr ansfer

Message Complete Circuit Closed

Path Closed Switch: 1 2 3 4 1 2 3 4 1 2 3 4

Circuit switched vs.packetswitched message timing

VPI VCI ECC The ATM frame structure

0 0 1 1 2 2 3 3

ATM 155 Mbps ATM trunk line ATM Switch Switch

28 28 29 29 30 30 31 31 Schematic ATM router switch

data payload addr 10101000111000 111

ATMdata cell 111 111 111 0 0 0 0 0 1 1 1 1 4

155 Mbps 155 Mbps

2 1 0 0 0 3 1 1 1 5

4 2 0 0 0 5 1 1 1 6

6 3 0 0 0 7 1 1 1 7

Interconnection inside an ATM Banynan Switch

LAN ATM switch

ATM155 Mbps Tr unk Line ATM switch ATM switch

Ser ver ATMWAN linking together diverse LANs to for m par t of the Internet

1010101010 8frames

Synchronization Batch 1.125 sec 1.0625 sec Next Batch

A/C address func CRC P Digital Paging word for mat

12 : 01

Enter car number ﬁrst Tariff 1hr 40p Press for Sun free ticket Sat free

Coins

Application of packetradio data messaging

customer premises Digital phone

U T ISDN NT1 Local Exchange ISDN i/f card Networ k ter minator maximum Domestic 8devices Control NarrowBand ISDN deﬁned interfaces

Tr ansmission Frame 48 bits in 250 µsecs D D D D

Bchan-1 Bchan-2 Bchan-1 Bchan-2 2B-1D Narrowband ISDN protocol timing

4B3T,Europe

0001 1011 0101 1010

2B1Q, USA

00 01 10 11 01 01 10

Multi-levelbaseband encoding

Binar y 3-levelcodes data 0000 +0- 0001 -+0 0010 0-+ 0011 +-0 0100 ++0 --0 0101 0++ 0-- 0110 +0+ -0- 0111 +++ --- 1000 ++- --+ 1001 -++ +-- 1010 +-+ -+- 1011 +00 -00 1100 0+0 0-0 1101 00+ 00- 1110 0+- 1111 -0+

Three-level4B3T encoding table

Splitter Splitter Subscr iber line DSL Modem ATM DSL Data 2.5 Km Data Switch Modem

Digital Subscriber Line conﬁguration

Guard bands ...... Amplitude ...... Data. . . Voice . . . . Data down-link . . up-link...... band . . . . band . . .band...... 0 4 25 160 240 780 Frequency (kHz)

Subscr iber line bandwidth allocation for ADSL

Kerb Set-top PSTN side box Tr unk Headend Node lines Local Coax / Telephone Optic Fibre Twisted Pair Exchange Video Kerb side Voice & data Twin cable Node

Cable TV and telephone distribution scheme

5 40 54 MHz 575 600 750 59 Analogue TV Channels Digital Outward

Digital Telephones Inward

Bandwidth allocation for a cable TV networ k

IBM On-line Ser ver

Batch Processing

Real-time k

gr aw sed ep

Types of computer operating systems

Pr imaryBootstrap from disk

Secondar y Bootstrap

Unix ker nel loaded

init runs single user

Multi-user mode star ts

getty processes star ted

Interactive user shell

Unix boot sequence

CSA Rob Williams CSA ch 17 - p 233 Pearson Education (c) 2006 Tool Function Example awktextprocessing language cat file | awk ’$0 !˜ /ˆ$/ {print}’ cat opens and concatenates files cat header ch_01 | groff -petfH > /tmp/tmp.ps diff file compar ison diff ch_01.a ch_01.b echo repeats argument to stdout echo $PATH find file search utility find ˜ -name "*rob*" -print grep string (reg expr) search grep "rob" /etc/passwd lpr print demon lpr -Pnts -#25 ˜/Sheets/unix_intro ls directorylisting ls -al more text viewermore book.txt ps process listing ps -af sed stream editor sed ’s/r-williams/rob.williams/g’ <file1 >file2 sor t str ing sor ter cat file | sort+1-2 spell spell checkerspell letter.txt tr transpose strings tr -cs ’A-Za-z’ ’\012’ troff text for matter groff -petfH uniq repeated line detector sor t |uniq -c | sort-n users networ k users list users > checkfile wc file sizer wc -w assignment.txt who local user list who

Some Unix tools

Tools Applications

API GUI or Shell

File Graphic Scheduler manager pr imitives Device Memor y Task dr ivers allocation dispatcher

Computer hardware

Typical operating system layered structure

UID - owner

Process State

Semaphore ID

Signal ID

Memor y needs

CODE SEG pointer

STACKSEG pointer

DATA SEG pointer

Pr ior ity Accounting infor mation File descriptors Current director y Task Queue pointers

Summar y contents of a TCB

Task stack Task area code

Task 2 Task 3 Control Block Control Block

Task Task Task stack code stack area area

Task 4 Control Block

Task stack Task area code

Tasks speciﬁed bytheir control blocks

Task Task stack code area

TCB 2

Task stack Task area code

TCB 3

Task stack Task area code

TCB 4

Task stack Task area code

Task Control Blockqueue

Timed out Exit

Process Ready Executing i/o wait I/O Blocked Forked

Terminated Dispatched

Waiting Condition Zombie Freed wait

State Diagramshowing the task lifecycle

rob@olveston [100] rlogin milly Last login: Wed Mar 29 19:22:33 from rob@milly [41] rob@milly [41] ps -A | wc -l 450 rob@milly [42] rob@milly [42] logout Connection closed. rob@olveston [101] rob@olveston [101] ps -A | wc -l 55 rob@olveston [102]

Using ps & wc to count running tasks

CSA Rob Williams CSA ch 17 - p 238 Pearson Education (c) 2006 UID (f,l) The effectiveuser ID number of the process (the login name is printed under the -f option). PID (all) The process ID of the process (this number is used when killing a process). PPID (f,l) The process ID of the parent process. STIME (f) The star ting time of the process,given in hours,minutes,and seconds. (A process begun more than 24 hours before the ps inquir y is displayedindaysand months) TTY (all) The controlling terminal for the process ("?" is shown when there is no controlling terminal as for background or daemon processes) TIME (all) The cumulativeexecution time for the process. CMD (all) The command name. (the full command name and its arguments,uptoa limit of 80 chars,are printed with the -f option). S (l) The state of the process,(use the -f option): OProcess is running on a processor. SSleeping: process is waiting for an ev ent to complete. RRunnable: process is on run queue. ZZombie state: process terminated and parent is not waiting. TProcess is stopped, either byajob control signal or because it is being traced. C (f,l) Processor utilization for scheduling. Not printed when the -c option is used.

Infor mation in the ps display, from the man page

Time-slicing Demand preemption Cooperative Interr upt dr iven

Process scheduling techniques

CSA Rob Williams CSA ch 17 - p 239 Pearson Education (c) 2006 rob@olveston [141] ps -Af UID PID PPID C STIME TTY TIME CMD root 0 0 0Mar 16 ? 0:01 sched root 1 0 0Mar 16 ? 0:02 /etc/init - root 2 0 0Mar 16 ? 0:00 pageout root 3 0 0Mar 16 ? 3:39 fsflush root 322 297 0Mar 16 ? 145:37 /usr/openwin/bin/Xsun :0 -noban root 122 10 Mar 16 ? 0:00 /usr/sbin/inetd -s root 318 10 Mar 16 ? 0:00 /usr/lib/saf/sac -t 300 root 102 10 Mar 16 ? 0:00 /usr/sbin/rpcbind root 112 10 Mar 16 ? 0:00 /usr/sbin/kerbd root 110 10 Mar 16 ? 0:00 /usr/lib/netsvc/yp/ypbind root 284 10 Mar 16 ? 0:02 /usr/sbin/vold root 226 10 Mar 16 ? 0:00 /usr/lib/autofs/automountd root 240 10 Mar 16 ? 0:01 /usr/sbin/cron root 230 10 Mar 16 ? 0:00 /usr/sbin/syslogd root 249 10 Mar 16 ? 0:01 /usr/sbin/nscd root 259 10 Mar 16 ? 0:01 /usr/lib/lpsched root 319 10 Mar 16 console 0:00 /usr/lib/saf/ttymon -g -h -p olves root 274 10 Mar 16 ? 0:00 /usr/lib/utmpd root 292 10 Mar 16 ? 0:00 /usr/lib/sendmail -q15m root 321 318 0Mar 16 ? 0:00 /usr/lib/saf/ttymon rwilliam 340 323 0Mar 16 ? 0:00 /bin/ksh /usr/dt/config/Xsession root 325 10 Mar 16 ? 0:00 /usr/openwin/bin/fbconsole -d :0 rwilliam 408 407 0Mar 16 ? 0:00 olwmslave rwilliam 342 340 0Mar 16 ? 0:00 /bin/ksh /usr/dt/bin/Xsession rwilliam 388 378 0Mar 16 ? 0:00 /bin/ksh /usr/dt/config/Xsession rwilliam 412 10 Mar 16 ?? 0:00 /usr/openwin/bin/cmdtool -Wp 0 0 rwilliam 378 342 0Mar 16 ? 0:00 /bin/tcsh -c unsetenv _ PWD; rwilliam 389 388 0Mar 16 ? 0:00 /bin/ksh /home/staff/csm/csstaff/ rwilliam 407 389 0Mar 16 ? 0:18 olwm -syncpid 406 rwilliam 19576 407 0 10:07:01 ?? 0:02 /usr/openwin/bin/xterm rwilliam 415 412 0Mar 16 pts/3 0:00 /bin/tcsh rwilliam 19949 19577 014:04:16 pts/5 0:05 ghostview /tmp/tmp.ps rwilliam 469 407 0Mar 16 ? 10:35 /usr/local/bin/emacs rwilliam 1061 1050 0 Mar 16 ? 0:00 (dns helper) rwilliam 553 407 0Mar 16 ? 0:21 /usr/openwin/bin/filemgr rwilliam 11510 10 Mar 22 ? 4:08 /opt/simeon/bin/simeon.orig -u root 20818 19577 118:01:46 pts/5 0:00 ps -Af rwilliam 20304 19949 015:31:45 pts/5 0:06 gs -sDEVICE=x11 -dNOPAUSE -dQUIET rwilliam 1050 407 0 Mar 16 ? 14:39 /usr/local/netscape/netscape rwilliam 12251 10 Mar 22 ? 0:17 /usr/local/Acrobat4/Reader/sparcs rwilliam 19577 19576 010:07:02 pts/5 0:01 tcsh

Displaying Unix task list using ps

CSA Rob Williams CSA ch 17 - p 240 Pearson Education (c) 2006 sched: the O/S scheduler,notice the PID value,animpor tant process,following boot init: startup process from boot time,gets all the other Unix processes started pageout: virtual memorypage handler fsflush: updates the super blockand flushes data to disk Xsun: X-windowser ver inetd: Internet serverdaemon, provides remote services such as ftp,telnet, rlogin, talk sac: portser vices access controller rpcbind: address mapper for remote procedure calls kerbd: source of kerberos unique keys, used for networ k user authentication ypbind: NIS distr ibuted password system vold: file system (volume) management for CDROMs and floppydisk drives automountd: daemon to handle remote file system mount/unmout requests cron: schedules tasks to run at particular times syslogd: system message handler and router nscd: name ser vice cache daemon lpsched: printer service scheduler ttymon: monitors ter minal por ts foractivity utmpd: user accounting daemon sendmail: Internet mail server ttymon: monitors ter minal por ts foractivity ksh: Kor n shell user interface fbconsole: console window olmslave:Open Look X-windowmanager ksh: second korn shell user interface ksh: third Korn shell user interface cmdtool: command-tool windowhandler tcsh: a tenexshell user interface ksh: four th Korn shell olwm: Open Look WindowManager xter m: Xter minal window tcsh: a tenexshell user interface ghostview; PostScr ipt screen viewer emacs: the best editor! dns: domain naming service for Internet name to IP number conversions filemgr: drag’ndrop file manager,useful for floppydisks simeon: mail client ps: this produced the process listing! gs: ghostscript translator netscape: Netscape Navigator Web browser acroread: Adobe Acrobat reader for viewing pdf documents tcsh: another user interface shell

Common Unix processes

Piping data between tasks in Unix

rob> world > hello.txt

rob> echo "Hello world!" > world.txt

rob> tr "\r" < ch_10.asc > ch_10

rob> cat header ch_* > book

rob> cat > letter << +++ ? Dear Craig, ? Here is the book that I promised to send ? Rob ? +++ rob>

Redirecting data from tasks and ﬁles in Unix

Stdin Stdout Unix process 0 1

Stderr 2 Standard I/O for Unix processes

WAIT(sem_buff) .... //critical region code .... SIGNAL(sem_buff);

Semaphore operators,WAIT and SIGNAL

CSA Rob Williams CSA ch 17 - p 242 Pearson Education (c) 2006 WRITER Task produce a newitem for Consumer Task WAIT(sem_space) WAIT(sem_free) place item on buffer queue SIGNAL(sem_free) SIGNAL(sem_data) END_WRITER

READER Task WAIT(sem_data) WAIT(sem_free) takeitem from buffer queue SIGNAL(sem_free) SIGNAL(sem_space) process the item END_READER Semaphores protecting a cyclic data buffer

#include #include #define MYSIG 44

/* Signal handler function, evoked by sig 44 reinstalls after each sig hit, prints number of hits */ void getsig(int s) { static int count = 0; printf("signal %d again, %dth time \n", s, ++count); signal(MYSIG, getsig); }

/* Process to demonstrate signals, sets up a sig handler to count the number of sig hits received. Loops forever. Start using "kbdcnt &" and make note of pid value returned Recommend to use "kill -44 pid" to send signals Remove using "kill -9 pid" */ int main(void) { signal(MYSIG, getsig); printf("start counting kbd kills\n"); while(1) {}; return 0; }

Unix signal handler to count and displaysignal hits

CSA Rob Williams CSA ch 17 - p 243 Pearson Education (c) 2006 compile the code rob [262] rob [263] gcc kbdcnt.c rob [264] a.out & runkbdcnt process [1] 9539 rob [265] start counting kbd kills kill -44 9539 rob [266] signal 44 again, 1th time kill -44 9539 rob [267] signal 44 again, 2th time send signal 44 kill -44 9539 rob [268] signal 44 again, 3th time kill -44 9539 rob [269] signal 44 again, 4th time

signal 44 Kill kbdcnt

Using a signal to notify a Unix process

CSA Rob Williams CSA ch 17 - p 244 Pearson Education (c) 2006 #include #include #include #define PSIG 43 /* check the value of NSIG in */ /* /usr/include/sys/signal.h */ #define CSIG 42 /* before choosing the signal values */ int ccount = 0; int pcount = 0; char str[] = "error message "; void psigfunc(int s) { pcount++; signal(CSIG, psigfunc); } void csigfunc(int s) { ccount++; signal(PSIG, csigfunc); } main() { int ke, tpid, ppid, cpid; ppid = getpid(); cpid = fork(); /* spawn child process */ if ( cpid == -1) { printf("failed to fork\n"); exit(1); } Continues

CSA Rob Williams CSA ch 17 - p 245 Pearson Education (c) 2006 if (cpid == 0 ) { /* Child process executes here */ signal(PSIG, csigfunc); printf("Child started\n"); while (1) { pause(); printf("Child hit! count = %d\n",ccount); sleep(rand()%10); if( (kill(ppid, CSIG)) ) perror(str); } } else { /* Parent process continues execution from here */ signal(CSIG, psigfunc); printf("Parent started\n"); while (1) { sleep(rand()%10); if( (kill(cpid, PSIG)) ) perror(str); pause(); printf("Parent hit! count = %d\n",pcount); } } }

PSIG 43

Parent Child

CSIG 42 Demonstrating the use of Signals byUnix Processes

rob@olveston [52] a.out Child started Parent started Child hit! count = 1 Parent hit! count = 1 Child hit! count = 2 Parent hit! count = 2 Child hit! count = 3 Parent hit! count = 3 Child hit! count = 4 Parent hit! count = 4 Child hit! count = 5 ˆC rob@olveston [53] Signal demonstrator programrunning on Unix CSA Rob Williams CSA ch 17 - p 246 Pearson Education (c) 2006 pid 469 Parent rob@olveston [40] trial & rob@olveston [41] ps main() { PID TTY TIME CMD cpid = for k(); 451 pts/4 0:00 tcsh 469 pts/4 0:02 trial rob@olveston [42]

fork pid 469 pid 472 Parent Child rob@olveston [43] ps PID TTY TIME CMD main() { main() { 451 pts/4 0:00 tcsh ...... 469 pts/4 0:02 trial ...... if (cpid == 0 ) { 472 pts/4 0:02 trial else { Child process rob@olveston [44] Parent continues star t executing ......

Unix process creation using fork( )

Vir tual Address

Segment Page Displacement number number

Seg Table Reg Segment table Page table

Vir tual to physical address translation

sh Original shell from Steve Bour ne csh C shell from Bill Joy bash borne again shell tcsh Tenexshell, myfavour ite ksh Kor n shell, ver y popular InteractiveUnix Shells

CSA Rob Williams CSA ch 17 - p 247 Pearson Education (c) 2006 rob [52] grep "ofthe" ‘ls | egrep "ch_.." ‘ ch_01: symbiosis established ofthe hardware and soft ch_11:as little as it is, the start ofthe applicatio rob [53] rob [53] mail ‘cat mail_list‘ < message rob [54] rob[54] echo "There are ‘who | wc -l‘ users logged in at ‘date‘" There are 12 users logged in at Tue June 20 20:23:55 BST 2000 rob [55]

Examples of shell command substitution

echo "hello other window" > /dev/pts/0

value speciﬁes which x-window to send to 0, 1, 2...

arp icmp ptmajor ptyq5 ptyrd syscon ttypc ttyr4 audio ie ptmx ptyq6 ptyre systty ttypd ttyr5 audioctl ip pts ptyq7 ptyrf tcp ttype ttyr6 bdoff ipd ptyp0 ptyq8 qe term ttypf ttyr7 be ipdcm ptyp1 ptyq9 rawip ticlts ttyq0 ttyr8 conslog ipdptp ptyp2 ptyqa rdiskette ticots ttyq1 ttyr9 console isdn ptyp3 ptyqb rdiskette0 ticotsord ttyq2 ttyra cua kbd ptyp4 ptyqc rdsk tnfctl ttyq3 ttyrb diskette kmem ptyp5 ptyqd rfd0 tnfmap ttyq4 ttyrc diskette0 kstat ptyp6 ptyqe rfd0a tty ttyq5 ttyrd dsk ksyms ptyp7 ptyqf rfd0b ttya ttyq6 ttyre dtremote le ptyp8 ptyr0 rfd0c ttyb ttyq7 ttyrf dump llc1 ptyp9 ptyr1 rmt ttyp0 ttyq8 udp ecpp0 log ptypa ptyr2 sad ttyp1 ttyq9 volctl es logindmux ptypb ptyr3 sehdlc ttyp2 ttyqa winlock fb m640 ptypc ptyr4 sehdlc0 ttyp3 ttyqb wscons fb0 md ptypd ptyr5 sehdlc1 ttyp4 ttyqc zero fbs mem ptype ptyr6 sound ttyp5 ttyqd fd mouse ptypf ptyr7 sp ttyp6 ttyqe fd0 null ptyq0 ptyr8 spcic ttyp7 ttyqf fd0a openprom ptyq1 ptyr9 stderr ttyp8 ttyr0 fd0b partn ptyq2 ptyra stdin ttyp9 ttyr1 fd0c printers ptyq3 ptyrb stdout ttypa ttyr2 hme profile ptyq4 ptyrc swap ttypb ttyr3 rob@olveston [155]

Unix device drivers in directory/dev

CSA Rob Williams CSA ch 17 - p 249 Pearson Education (c) 2006 rob@olveston [101] more /etc/termcap ..... xterm|vs100|xterm terminal emulator (X Window System):\ :AL=\E[%dL:DC=\E[%dP:DL=\E[%dM:DO=\E[%dB:IC=\E[%d@:U :al=\E[L:am:\ :bs:cd=\E[J:ce=\E[K:cl=\E[H\E[2J:cm=\E[%i%d;%dH:co#8 :cs=\E[%i%d;%dr:ct=\E[3k:\ :dc=\E[P:dl=\E[M:\ :im=\E[4h:ei=\E[4l:mi:\ :ho=\E[H:\ :is=\E[r\E[m\E[2J\E[H\E[?7h\E[?1;3;4;6l\E[4l:\ :rs=\E[r\E[m\E[2J\E[H\E[?7h\E[?1;3;4;6l\E[4l\E<:\ :k1=\EOP:k2=\EOQ:k3=\EOR:k4=\EOS:kb=ˆH:kd=\EOB:ke=\E :kl=\EOD:km:kn#4:kr=\EOC:ks=\E[?1h\E=:ku=\EOA:\ :li#65:md=\E[1m:me=\E[m:mr=\E[7m:ms:nd=\E[C:pt:\ :sc=\E7:rc=\E8:sf=\n:so=\E[7m:se=\E[m:sr=\EM:\ :te=\E[2J\E[?47l\E8:ti=\E7\E[?47h:\ :up=\E[A:us=\E[4m:ue=\E[m:xn:

Unix termcap entryfor an Xterm

CSA Rob Williams CSA ch 17 - p 250 Pearson Education (c) 2006 Code Arg Padding Function al str (P*) add newblank line am bool ter minal has automatic margins bs bool (o) terminal can backspace with ˆH cd str (P*) clear to end of display ce str (P) clear to end of line cl str (P*) clear screen and home cursor cm str (NP) cursor move torow m,column n cs str (NP) change scroll region to lines m thro n ct str (P) clear all tab stops dc str (P*) delete character dl str (P*) delete line im str enter insertmode ho str (P) home cursor

%d decimal number starting at 0 %2 same as %2d %3 same as %3d %. ASCII equiv %+v adds xthen taken as % %>xy if value is >x; then add y.notransmission %r reverse order of rows/columns %i origin is at 1,1 not 0,0 %% gives a single % %n XOR rowand column (??) %B BCD format %D reverse coding

Some Unix termcap metacodes

User Applications

User Mode Win NT Subsystems

NativeAPI

NT Executive Kernel Mode NT Kernel

HAL Hardware Abstraction Layer

Hardware

Windows-NT/XP structure

Applications

Winr32 OS/2 Posix DOS Subsys Subsys Subsys Subsys

NativeAPI

NT Kernel

Win32 and the Ker nel

HKEY_LOCAL_MACHINE holds the hardware configuration, installed device drivers, networ k protocols,software classes. Configconfiguration parameters for local computer Enum device configuration Hardwareser ial por t configuration Networ kuser login infor mation Secur ityremote administration permissions Softwareinstalled software Systembooting infor mation

HKEY_CURRENT_CONFIG holds the current hardware conﬁguration, where options exist

HKEY_CLASSES_ROOTholds document types,ﬁle associations,shell interface

HKEY_USERS holds login users’ software preferences and desktop conﬁguration

HKEY_CURRENT_USER holds copies of the preferences of the curent user. Registr y top levelkeys

User name 20 char Passwords 14 char Machine name 15 char Workgroup names 15 char Share names 12 char

Discrepency in effectivestr ing lengths

Data Application Advantages Disadvantages organization type Sequential batch Simple,efficient Maintenance processing difficult data needs sorting Indexed- batch Sequential and Indextakes up sequential processing direct access space no data sorting less efficient Direct on-line No data sorting Space inefficient fast access inconvenient to use Database on-line flexible Perfor mance poor access maintenance costs Data filing and databases

Pr imaryPar tition

Secondar y Partitions

Master Par tition Boot Record

Hard Disk with Four Par titions

0 6 5 7 3 1 4 2 Platter 0 5 7 Platter 1 3 2 Platter 2 1 4 Platter 3

Dr ivespindle

Alter nativelay outs for blocks 1, 2, 3, 4, 5 & 7 to reduce access times (Head Movement Delays)

CSA Rob Williams CSA ch 19 - p 261 Pearson Education (c) 2006 Signature AA55H Partition 1 Sector SizeContent Head, Cylinder,Sector star t bytes Partition Partition 2 H7 H6 H5 H4 H3 H2 H1 H0 Table Partition 3 00H 1 Boot ﬂag 01H 3 Star t of partition C9 C8 S6 S5 S4 S3 S2 S1 S0 Partition 4 04H 1 System Flag 05H 3 End of Par tition C7 C6 C5 C4 C3 C2 C1 C0 Programtocheck 08H 4 Star t of Sector Partition Table OCH 4 #sectors Code and transfer to Boot Par tition Boot Flag -00H Inactive(nonbootable), 80H Active(bootable) System Flag -01H FAT- 12 04H FAT-16 05H Extended DOS partition 08H AIX Disk Master Par tition Boot Record 0AH OS/2 0BH FAT-32 DBH CP/M (!) 83H Linux

OS boot loader program

#Hidden Sectors 2byte

#Heads 2byte

#Sectors / Track 2byte

#sectors / FAT 2byte

media byte (F8H) 1byte

#logical Sectors 2byte

#Root DIR entries 2byte

#FATS 1byte

#Boot Sectors 2byte

#Sectors / Cluster 1byte

#Bytes / sector 2byte

OEM Name/ID 8byte

jmp to loader 3byte

APar tition Boot Record (non Master)

Essential infor mation fordirector y entr ies

rob@milly [20]/usr/sbin/mount /on/dev/dsk/c0t0d0s0 read/write/setuid on Mon Jul 19 08:12:44 2000 /usr on /dev/dsk/c0t0d0s3 read/write/setuid on Mon Jul 19 08:12:44 2000 /proc on /proc read/write/setuid on Mon Jul 19 08:12:44 2000 /dev/fd on fd read/write/setuid on Mon Jul 19 08:12:44 2000 /var on /dev/dsk/c0t0d0s4 read/write/setuid on Mon Jul 19 08:12:44 2000 /cache/cache1 on /dev/dsk/c0t0d0s7 setuid/read/write on Mon Jul 19 08:13:4 /cache/cache2 on /dev/dsk/c0t1d0s7 setuid/read/write on Mon Jul 19 08:13:4 /cache/cache3 on /dev/dsk/c0t2d0s7 setuid/read/write on Mon Jul 19 08:13:4 /cache/cache4 on /dev/dsk/c0t3d0s7 setuid/read/write on Mon Jul 19 08:13:4 /cache/cache5 on /dev/dsk/c0t10d0s7 setuid/read/write on Mon Jul 19 08:13: /opt on /dev/dsk/c0t0d0s6 setuid/read/write on Mon Jul 19 08:13:45 2000 /tmp on /dev/dsk/c0t0d0s5 setuid/read/write on Mon Jul 19 08:13:45 2000 /tftpboot on /dev/dsk/c0t1d0s0 setuid/read/write on Mon Jul 19 08:13:45 19 /home/student/csm/BSc/CRTS/2 on /dev/dsk/c0t1d0s3 nosuid/read/write/quota /home/student/csm/BSc/other on /dev/dsk/c0t1d0s4 nosuid/read/write/quota on /home/student/csm/BA/other on /dev/dsk/c0t1d0s5 nosuid/read/write/quota on /home/student/csm/PhD on /dev/dsk/c0t1d0s6 nosuid/read/write/quota on Mon /home/student/csm/BSc/CRTS/2p on /dev/dsk/c0t2d0s3 nosuid/read/write/quota

...

Unix mount table

TEST DAT 4 BIOS Disk LBN

10 FFFFH

8 3 1 10 2 2 2 4bytes 7 6 Disk Directory: 32 byte entries 6 10 FAT- 16 Directoryand File Allocation Table 5

4 7

Sector Sectors Cluster Cluster Nax 2 Sizeper SizeIndexVolume Cluster SizeCapacity 1

512B 4 2kB 16bits 128MB 0 512B 16 8kB 16bits 512MB FAT 512B 32 16kB 16bits 1GB 512B 64 32kB 16bits 2GB 512B 16 8kB 32bits 32TB

FATcluster sizeand volume capacity

CSA Rob Williams CSA ch 19 - p 264 Pearson Education (c) 2006 struct stat { dev_t st_dev; /* device holding the relevant directory */ long st_pad1[3]; /* reserve for dev expansion, */ ino_t st_ino; /* inode number */ mode_t st_mode; nlink_t st_nlink; /* number of active links to the file */ uid_t st_uid; /* file owner’s ID */ gid_t st_gid; /* designated group id */ dev_t st_rdev; long st_pad2[2]; off_t st_size; /* file size in bytes */ long st_pad3; /* reserve for future off_t expansion */ timestruc_t st_atime; /* last access time */ timestruc_t st_mtime; /* last write time (modification) */ timestruc_t st_ctime; /* last status change time */ long st_blksize; long st_blocks; char st_fstype[_ST_FSTYPSZ]; long st_pad4[8]; /* expansion area */ }; Unix ﬁle system inode structure

owner uid Boot Block gid of owner file type rwx access modes time of last access time modified time of inode change Super Block file size direct 1 direct 2 direct 3 direct 4 inode Blocks direct 5 direct 6 direct 7 direct 8 direct 9 direct 10 Data Blocks indirect double indirect tr iple indirect

Unix inode ﬁle access records

CSA Rob Williams CSA ch 19 - p 265 Pearson Education (c) 2006 director y pr incipal test.cname inodp ﬁle inode name inodp dir name inodp inode name inodp 0inodp name inodp 1inodp name inodp 2inodp name inodp 3inodp name inodp 4inodp Data Block name inodp 5inodp name inodp 6inodp 7inodp Data Block 8inodp 9inodp 10 inodp Data Block 11 inodp 12 Iinode 13 DIinode index 14 TIinode block 0dp 1dp 2dp 3dp Data Block 4dp 5dp Data Block 994 dp 995 dp 996 dp Data Block 997 dp 998 dp 999 dp

Unix inode pointers indicating a ﬁle’sdata blocks

CSA Rob Williams CSA ch 19 - p 266 Pearson Education (c) 2006 / Conﬁg root dir director y inode namebin inodp 0inodp nameetc inodp /etc 1inodp nameusr inodp dir 2inodp namedev inodp inode uucp 3inodp namelib inodp 0inodp director y 4inodp Data Block nametmp inodp 1inodp name inodp 5inodp namesbin inodp 2inodp name inodp 6inodp localname inodp 3inodp name inodp 7inodp Data Block homename inodp 4inodp name inodp 8inodp namepub inodp 5inodp name inodp 9inodp 6inodp name inodp 10 inodp Data Block 7inodp name inodp 11 inodp 8inodp name inodp 12 Iinode 9inodp name inodp 13 DIinode 10 inodp name inodp 14 TIinode 11 inodp 12 Iinode /stuff 13 DIinode 14 TIinode dir inode rusers 0inodp director y 1inodp name inodp 2inodp name inodp 3inodp name inodp 4inodp name inodp 5inodp name inodp 6inodp name inodp 7inodp name inodp 8inodp name inodp 9inodp name inodp 10 inodp name inodp 11 inodp 12 Iinode 13 DIinode 14 TIinode

Relating Unix directories to the inode blocks

1fp 2fp DOS 3fp Info Name Name Secur ity Cluster Pointers 4fp 5fp Director y 6fp Block 7fp 8fp Data Block 9fp 10 fp Data Block

Windows-NTFS Master File Table

Read Write/ Execute/ delete attach owner groupees anyuser

File and directoryaccess control options

12345

Data Block

RAID 1

Data Block

byte 1 byte 2 byte 3 byte 4 CRC RAID 2/3

Data Block

str ip 1 str ip 2 str ip 3 str ip 4 chksum str ip 5 str ip 6 str ip 7 str ip 8 chksum RAID 4

12345

Data Block

RAID 5

str ip 1 str ip 2 str ip 3 str ip 4 chksum str ip 5 str ip 6 str ip 7 chksum str ip 8 str ip 9 str ip 10 chksum str ip 11 str ip 12 str ip 13 chksum str ip 14 str ip 15 str ip 16 chksum str ip 17 str ip 18 str ip 19 str ip 20

RAID disk conﬁguations

CSA Rob Williams CSA ch 19 - p 269 Pearson Education (c) 2006 rob@olveston [63] ls -al -rwx------1 rob csstaff 280 Sep 51998 timezone -rwx------1 rob csstaff 48 Sep 11 1999 tit -rwx------1 rob csstaff 229 Jan 22 1999 to_arthur -rwx------1 rob csstaff 25007 Apr 11999 unzipit -rwx------1 rob csstaff 251 Sep 51998 vorc -rwx------1 rob csstaff 243 Sep 51998 vorcorn rob@olveston [64] chmod 666 unzip rob@olveston [65] ls -al unzip -rw-rw-rw- 1 rob csstaff 25007 Apr 11999 unzipit rob@olveston [66] chmod 000 unzipit rob@olveston [67] ./unzipit ./unziput: permission denied. rob@olveston [68] ls -al unzip ------1 rob csstaff 25007 Apr 11999 unzipit rob@olveston [69] chmod 100 unzipit rob@olveston [70] ./unzipit rob@olveston [71] rob@olveston [71] chmod 711 unzipit rob@olveston [72] ls -al unzipit -rwx--x--x 1 rob csstaff 25007 Apr 11999 unzipit rob@olveston [73]

Setting File Access Per missions in Unix

DisplayPixel data DisplaysizeImage size pixels Bytes Full colour 24 bits 1024 x 768 2.25MB Reduced-range colour 8bits 0.75MB Grey-scale monochrome 8bits 0.75MB Black-white monochrome 1bit 96kB

Data requirements for different displaytypes

Magniﬁed viewof pixels on the screen

Vertical Fly Back

Hor izontal Fly Back Bitmapped raster display

RGB Glass front electron guns screen with phosphor coating Shadowmask B GR

Shadowmask inside a colour CRT

CSA Rob Williams CSA ch 20 - p 272 Pearson Education (c) 2006 Resolution Ver tical Hor izontal scan rate scan rate Hz kHz 640 x 480 60 31.5 640 x 480 72 37.8 800 x 600 75 46.9 800 x 600 85 53.7 1024 x 768 75 60.0 1024 x 768 85 68.8 1152 x 864 85 77.6 1280 x 1024 75 80.0 1280 x 1024 85 91.2

Nor mal CRThor izontal and ver tical scan rates

The time period for writing a single pixel onto the screen can be estimated:

1 = 21 ns/pixel 60 x 1024 x 768

light 100Hz driver clock polar izing ﬁlter backplane electrode liquid crystal

polar izing ﬁlter 0 in phase OFF

1 out of phase Control signals ON

Liquid crystal panels

CSA Rob Williams CSA ch 20 - p 274 Pearson Education (c) 2006 .PS define Driver {[line right 0.3 down 0.1 line left 0.3 down 0.1; line up 0.2]} Base: box wid 6 ht 2 invis line up 2 from Base.sw line up 2 from Base.sw+0.4,0 line right 0.4 from Base.w+0,0.4 line right 0.4 from Base.w-0,0.4 """""image""data" below circle rad 0.02 at Base.w+0.2,0 line up 0.5 from last circle; arrow right 2 "color#""" above Palet: box wid 1.2 ht 1 ibox wid 1.2 ht 0.2 with .n at Palet.n "RGB Palette" ibox wid 1.2 ht 0.2 with .n at last box.s "table" ibox wid 1.2 ht 0.2 with .n at last box.s "R GB" {move up 0.1; line left 1.2} {move down 0.1 line left 0.4; {line up 0.2}; line left 0.4 {line up 0.2}; line left 0.4} line down 0.7 from Palet.s-0.3,0 arrow right 1.2 "8bits"below; [Driver] line right 0.2 from last [].e then up 0.25 then right 0.2 box wid 0.6 ht 0.3 invis with .n at last [].s "DACs" line down 0.1 from Palet.s+0.3,0 arrow right 0.6 "8bits"below; [Driver] line right 0.2 from last [].e; line down 0.25; line right 0.2 line down 0.4 from Palet.s arrow right 0.9 "8bits"below; [Driver] line right 0.4 from last [].e then up 0.07 then right 0.4 then right 0.5 up 0.2 line down 0.6 "CRT "rjust line left 0.5 up 0.2; line left 0.4; line up 0.07 box wid 0.8 ht 0.2 at Base.w+1.1,0.2 "image base" box wid 0.8 ht 0.2 with .n at last box.s-0,0.1 "Y X" {arrow <- right 0.2 from last box.e move down 0.1 for i=1 to 2 do { line right 0.1 then up 0.2 then right 0.1 then down 0.2 } line right 0.1 } line from last box.n to last box.s arrow -> left 0.2 from last box.w box wid 0.6 ht 0.4 invis with .n at last box.s "image pointer" "23"atPalet.nw+0,0.2;"0"atPalet.ne+0,0.2 box wid 0.5 ht 0.3 invis "Memory" with .nw at Base.sw .PE Example pic script

System Body Init Closedown * An SVGscr ipt, rendered byFirefox

Tw o tiered AGPconnector

An SVGA graphics adapter card with AGP interface

Mono 1981 Te xtonly mode offered byoriginal 8088 PC

Hercules 1983 First mono graphics card 720 x 348 graphics

CGA 1983 ﬁrst colour (4) graphics card from IBM 320 x 200 double horizontal resolution if limited to mono

EGA 1984 16 colour graphics 640 x350

VGA1987 EGA compatible 16 colour high resolution 256 colours 640 x 480 256k colours (18 bit/pixel) 320 x200 (CGA)

SVGA 1990 256 colours (8 bits/pixel) 1024 x768 1995 24 bit true colour (3 bytes/pixel)

XGA 1997 32768 colours (15 bits) 1280 x 1024

Evolving range of standards for screen display

DVI-I dual standard monitor DB-15 SVGA Monitor socket Socket

Pin # Signal Name Pin # Signal Name Pin # Signal Name 1TMDS Data2- 9TMDS Data1- 17 TMDS Data0- 2TMDS Data2+ 10 TMDS Data1+ 18 TMDS Data0+ 3TMDS Data2/4 Shield 11 TMDS Data1/3 Shield 19 TMDS Data0/5 Shield 4TMDS Data4- 12 TMDS Data3- 20 TMDS Data5- 5TMDS Data4+ 13 TMDS Data3+ 21 TMDS Data5+ 6DDC Clock[SCL] 14 +5 V Pow er22TMDS ClockShield 7DDC Data [SDA] 15 Ground 23 TMDS Clock+ 8Analog Ver t Sync 16 Hot Plug Detect 24 TMDS Clock- C1 Analog Red C2 Analog Green C3 Analog Blue C4 Analog Hor iz Sync C5 Analog GND Return 29 pin DVI connector pinout and signal names

Pin SVGA 1RED 2GREEN 3BLUE 4 5ground 6RED rtn 7GREEN rtn 8BLUE rtn 9key-pin 10 SYNC rtn 11 12 Mon id 13 H Sync 14 V Sync 15

15 pin SVGconnector pinout and signal names

Dr iving acolour screen

23 0 RGB Palette 04 table 03 8bit colour # R G B 02 image pointer 01 rowcolumn 00 Y X 8bits image base reg CRT image 8bits

data 8bits DA Cs Display Memor y

Dr iving aPCscreen using a palette table

14.31818 MHz HSync

Cr ystal Pixel Line Field ÷ 1024 ÷ 60 VSync Oscillator Clock Clock Clock 9 0 9 0 Screen Screen 60ms column row Raster control row3 position position

Display row2 19 0 memor y Displaymemor y row1 address

Address to displaymemor y

Synchronization of screen raster with displaymemor y

Erase lamp Cleaner Scanning head Motor Hopper Toner paper feed laser Paper Tray source Motor

IRQ CPU

PostScr ipt I/O Inter preter Memor y

ser ial link from host computer Laser Printer

Forapage represented as a 600 dpi image:

11x 7x 600x 600 single A4 page image = = 3. 5Mbytes 8 The same page mayberepresented byfar less data if it is ASCII coded:

Maximum number of characters on an A4 page = 60x 100 = 6000char The number of characters on a WP page is about 2500, 2.5 Kbytes of ASCII data. Thus,the compressing ratio would be: 2500 compression ratio = = 0. 0007 3500000 Such a sizereduction is certainly wor th achieving but OCR software has only recently been improvedenough to giveacceptably fast and accurate perfor mance.

CSA Rob Williams CSA ch 20 - p 281 Pearson Education (c) 2006 newpath Ghostview, version 1.1 270 360 moveto 072rlineto 72 0 rlineto 0-72 rlineto closepath 4setlinewidth stroke newpath 272 362 moveto 068rlineto 68 0 rlineto 0-68 rlineto closepath hello! .8 setgray ﬁll /Times-Roman ﬁndfont 24 scalefont setfont 280 400 moveto 0setgray (hello!) show showpage

** emacs test1.ps

PostScr ipt development, script edited byemacs, rendered byghostview

CSA Rob Williams CSA ch 20 - p 282 Pearson Education (c) 2006 newpath Ghostview, version 1.1 100setrgbcolor 200 200 moveto 0160 rlineto 160 0 rlineto 0-160 rlineto closepath fill newpath 360 280 moveto -80 0 rlineto 80 -40 rlineto closepath 1setgray fill newpath 380 280 105 180 135 arcn 48 0 rlineto 0-40 rlineto closepath 1setgray fill /Helvetica findfont 68 scalefont setfont

1setgray UWE 255 200 translate 90 rotate BRISTOL 00moveto (UWE) show newpath 80 -130 120 0 180 arc 1setgray 7setlinewidth stroke 00moveto -90 rotate /Helvetica ﬁndfont 42 scalefont setfont 100setrgbcolor -60 -40 rmoveto (BRISTOL) show showpage ** emacs uwe_pacman.ps

More PostScr ipt, butnow incolour! gs -dNOPAUSE -dBATCH -r1200 -sDEVICE=pdfwrite -sOutputFile=ch_16.pdf ch_16.ps

CSA Rob Williams CSA ch 20 - p 283 Pearson Education (c) 2006 rob [57] cat header ch_16 | groff -t -e -p -fH > ch_16.ps rob [58] gs -dNOPAUSE -dBATCH -r1200 -sDEVICE=pdfwrite -sOutputFile=ch_16.pdf ch_16.ps ....

rob [57] ls -al ch_16* -rw------1 rwilliam csstaff 52114 Jul 1 08:42 ch_16 -rwx------1 rwilliam csstaff 42253 Jun 28 13:26 ch_16.asc -rw------1 rwilliam csstaff 840398 Jul 1 08:44 ch_16.pdf -rw------1 rwilliam csstaff 1212385 Jul 1 08:43 ch_16.ps -rw------1 rwilliam csstaff 22093 Feb 24 11:07 ch_16d -rw------1 rwilliam csstaff 16437 Nov51998 ch_16d˜ -rw------1 rwilliam csstaff 23975 Jun 16 16:42 ch_16˜ .... rob [58] acroread ch_l6.pdf & .... rob [59] ghostviewch_16.ps & ....

rob [60]

Compar ing ﬁle sizes: ASCII, ps and pdf

10obj << 60obj /Type /Catalog [/PDF /Text] /Pages 3 0 R endobj /Outlines 2 0 R >> 70obj endobj << /Type /Font 20obj /Subtype /Type1 << /Name /F1 /Type /Outlines /BaseFont /Helvetica Count 0 /Encoding /MacRomanEncoding >> >> endobj endobj xref 30obj 08 << 0000000000 65535 f /Type /Pages 0000000009 00000 n /Count 1 0000000074 00000 n /Kids [4 0 R] 0000000120 00000 n >> 0000000179 00000 n endobj 0000000322 00000 n 0000000415 00000 n 40obj 0000000445 00000 n << trailer /Type /Page << /Parent 3 0 R /Size 8 /Resources <>/ProcSet 6 0 /RootR>> 1 0 R /MediaBox [0 0 612 792] >> /Contents 5 0 R startxref >> 553 endobj %%EOF 50obj << /Lengtb 44 >> stream BT /F1 72 Tf 100 50 Td (Hello World!) Tj ET endstream endobj The "Hello Wor ld!" example in pdf code

Layout of a typical windowscheme

CSA Rob Williams CSA ch 20 - p 287 Pearson Education (c) 2006 Vir tual Device Inferface (GDI) Bitmaps,Icons & Metaﬁles Creating Windows Operating Windows On-screen Menuhandling Dealing with Mouse and Keyboard Events Handling Dialog Boxes Timer Events Threads and Process Scheduling Exception Messages Free MemoryManagement Device handling Pr inting and Textoutput File Management Data interchange through Clipboard OLE / DDE data interchange System Parameter RegistryManagement System Infor mation DLL Management functions Networ k Access Routines Passing and processing Messages Audio data management

Win32 API facilities

Yo ur ﬁrst Windows application

Intr insics

Widgets

X-Lib

X-Windows Programming

80 63 0 127 0 mm7 xmm7 mm6 xmm6 mm5 xmm5 mm4 xmm4 mm3 xmm3 mm2 xmm2 mm1 xmm1 mm0 xmm0 f/p mmx MMX and SSE data registers

Application code

Operating System

CU Microcode

H/w Logic Units

Functional hierarchy

Sun Microsystems’ UltraSparc II

CSA Rob Williams CSA ch 21 - p 292 Pearson Education (c) 2006 1. Single length instruction codes 2. Single clockcycle execution period 3. Limited arithmetical complexity supported 4. Extensivesupply of CPU registers 5. Limited repetoire of machine instructions 6. Only straightforward addressing modes supported 7. Hardware supportfor procedure handling 8. No structured data types recognised 9. Compiler supplied to supportthe architecture 10. Hardware CU,pipelined decoding 11. Simpliﬁed interrupt facilities

Pr incipal features of RISC CPUs

MHz

1000 AMD Athlon

AMD K7 Pentium II Pentium Pro 100 Pentium

i486

i386 10

i8086

i8080 1

1970 1980 1985 1990 1995 2000

Increasing clockspeed of microprocessors

CSA Rob Williams CSA ch 21 - p 293 Pearson Education (c) 2006 Stackpassing Parameters are pushed up onto the stackbefore transferr ing control (jumping) to the subroutine.The subroutine code shares the same system Main stackand can access the parameters through the stack Memor y stackorframe pointer.Copies of VALUE parameters are simply pushed onto the stack, while reference, VAR, parameters are 32 bit addresses pointing back at data. Stackframe setup overheads,and access times to non-local var iables within scope are an issue.

Register passing Using CPU registers to hold the parameters is the fastest method, but limited bythe CPU number and sizeofregisters available.Compilers registers select this technique only if a couple of simple (integer,char) var iables are to be passed IN, and for the single OUT returnvalue from functions.

Register windows This is a specialised stack CPU technique used bySPARC processors to reduce the stack amount of stackPUSHing and POPping. By registers physically overlapping the stackframes for adjacent procedures,some of the local var iables can be visible as parameters with no data copying. Tofur ther speed up the process,SPARC CPUs have fast stackcaches.

Parameter blocks Formachines without stacks,the problem of where to save the returnaddress is solved by the CALL instruction inserting the returnaddress at the top of the procedure code before transferr ing control. The parameters are cunningly inserted in a blockimmediately after the CALL instruction, thus giving the procedure access byusing the return address as a pointer.

Global access Fortranand BASIC would rely on global data blocks visible to all code.This system of memor y parameter blocks has been reinstituted for graphics and Windows programming, where the number of parameters is so great that little else could be suggested.

Variety of parameter passing methods

Cycle 2 NOP JMP ADD - -

Cycle 3 NOP NOP JMP ADD -

Cycle 4 NOP NOP NOP JMP ADD

Cycle 5 NOP NOP NOP NOP JMP

Cycle 6 AND NOP NOP NOP NOP

System Clock

Multi-stage pipeline decoding - parallel processing

LD/ST

IF ID INT RO WB

FP 1 2 4 5

A5stage superscalar achitecture with 3 execution units

WAR, write after read MOVEBX,EAX MOVEAX,10 EAX is read

WAW,write after write MUL 100 sequence ADD EAX,10 correct

Control the outcome of a previous CMP AL,’q’ instr uction is essential for JZ exit Z ﬂag set an instruction to complete

Resource limited availability of ﬂoating-point hardware resources ar ithmetic unit free

Instr uction pipeline dependencies

ALU A Instr uctions from memor y Pipeline A

Pre fetcher unit ALU B PC

Pipeline B

ALU C

Pipeline C

Use of Register File Store with superscalar processors

Valid Flag Index Register File 0 1 r5 2 r6 3 r7 4 r8 5 1 8 r9 6 r10 7 r11 8 1 3 r12 9 r13 r14

Conditional Prediction Branch Target Instr uction Conﬁdence address address Value

Control Unit Branch Prediction Table

CSA Rob Williams CSA ch 21 - p 298 Pearson Education (c) 2006 Version Example Descr iption Pipeline core v1 ARM1 Or iginal processor,26bit address,3 coprocessor for Beeb v2 ARM2 32 bit multiplier,coprocessor included 3 Acor n Archemedies/A3000 v2a ARM3 on-chip cache,semaphore supportwith 3 sw apinstr uction v3 ARM6 &ARM7DI 32 bit address,CPSR/SPSR, MMU 3 ﬁrst macro-cell product. v3M ARM3M enhanced multiply with 64 bit result 3

v4 StrongArmLD/ST for 8/16 bit values,system mode 5 iPAQ PDA, v4T ARM7TDMI Compressed Thumb instruction set, MULA 3 used for manymobile handsets ARM9TDMI 5

v5 XScale 7

v5TE ARM9E &ARM10E better MUL, extraDSP instcns 5

v5TEJ ARM7EJ &ARM926EJ Javaoption 5

v6 ARM11 8

Histor ic revisions of ARM architectures

r10 r10_fiq Interr upt Super visor Undefined Abor t r11 r11_fiq request trap exception error r12 r12_fiq r13_irq r13_svc r13_undef r13_abt r13/sp r13_fiq r14_irq r14_svc r14_undef r14_abt r14 /lr r14_fiq r15/pc

cpsr - spsr_ﬁq spsr_irq spsr_svc spsr_undef spsr_abt

ARM CPU registers,showing the alternate sets

OR 11 0 0 12 bit displacement (unsigned) ldr/str

31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 0 condition 01 # P U B W L Rn Rd offset ﬁeld

source/destination register base register load or store operation Rindexwrite backfor auto indexing word or unsigned byte data backwards/forwards,sign bit for displacement pre/post index, bump pointer before or after data movement offset type,immediate or register predicate execution condition (Z, C,N,V)

Instr uction formats for the ARM ldr & str instr uctions

Condition codes 31 27 24 23 8 4 0 N Z C V Q J i F t SVC

Jazelle Saturated Thumb mode enabled Overﬂow Fast interrupt enabled Carr y out Interr upt enabled Zero value Negativevalue,msb==1

ARM programstatus register

CSA Rob Williams CSA ch 21 - p 301 Pearson Education (c) 2006 Opcode Mnm Meaning Flag [31-28] 0000 EQ equal values Z=1 0001 NE not equal Z=0 0010 CS carr y set C=1 0011 CC carr y clear C=0 0100 MI negativevalue N=1 0101 PL positivevalue N=0 0110 VS overﬂowV=1 0111 VC no overﬂowV=0 1000 HI unsign higher C=1 && Z=0 1001 LS unsign lowerC=0 || Z=1 1010 GE greater or equal N=V 1011 LTless than N!=V 1100 GT greater than Z=0 && N=V 1101 LE less or equal Z=1 || N!=V 1110 AL always 1111 NV neveruse

ARM condition codes

movRn, Rm copydata between registers

ldr Rn, [Rm] get avar iable from memory str Rn, [Rm] put avar iable backinmemor y

add R0, R1, R2 add tworegisters,result in third cmp R0, R1 compare tworegisters

baddr jump to relativelocation (+_32 MB) bl addr call subroutine (+_32MB) movR15, R14 retur n from subroutine

ldmfd R13!, {Rm-Rn} pop registers from stack stmfd R13!, {Rm-Rn} push registers onto stack

ldr Rn, =constant adr Rn, label

Basic "starter" instructions for the ARM processor

OR 11 7 6 5 4 3 0 0 shift-size sh/rot 0 Rindex

OR 11 8 4 6 5 4 3 0 mov 0 and/add/sub/cmp Rshift 0 sh/rot 1 Rindex tst/and/orrrrr/eor/bic 31 28 27 26 25 24 21 20 19 16 15 12 11 0 condition 00 # opcode S Rn Rd operand 2

destination register operand register set condition status ﬂags ar ithmetic/logic function selector operand 2 type predicate execution condition (Z, C,N,V)

opcodeopcode Mnm Meaning Effect sh/rotsh/rot Effect 0000 and logical bit-wise AND Rd = Rn && Op2 00 Rn, LSL #shift-size 0001 eor logical bit-wise XOR Rd = Rn ˆˆ Op2 01 Rn, LSR #shift-size 0010 sub subtract Rd =Rn-Op2 10 Rn, ASR #shift-size 0011 rsb reverse sub Rd = Op2- Rn 11 Rn, ASL #shift-size 0100 add ar ithmetic add Rd =Rn+Op2 0101 adc add with carryinRd=Rn+Op2+C 0110 sbc subtract with carryRd=Rn-Op2+C-1 0111 rsc reverse sbc Rd = Op2-Rn+C-1 1000 tst test Rn && Op2 1001 teq test equal RN ˆˆ Op2 1010 cmp compare Rn -Op2 1011 cmn negated comp Rn + Op2 1100 orr logical bit-wise OR Rd = Rn || Op2 1101 movcopyregister data Rd = Op2 1110 bic bit clear Rd = Rn $$ ˜Op2 1111 mvn negated movRd=˜Op2

Instr uction formats for move , ar ithmetic &logical instructions

HP iPAQ hx2400 PCB.The 420 MHz XScale CPU is shrouded byemission reduction foil

CSA Rob Williams CSA ch 21 - p 304 Pearson Education (c) 2006 Intel® PXA270 624MHz processor 64 MB Mobile SDRAM 128 MB Flash: 2 x 64 Mbyte (Intel RD48F4400L0zb0) Up to 135 Mbyte of memoryisavailable for user applications 100 mm transﬂectiveTFT VGA 64K color display(480x640) Graphics controller (ATI Mobileon W3220) Touch screen (Texas Instruments TSC2046 /SPI) Touchpad (Synaptics NavPoint module /SPI), Removable&rechargeable Lithium-Ion battery(1800 mAh) Secure Digital (SDIO) slot Compact Flash I & II (CF) slot IrDApor t (Exar XR16L580IL 16550-compatible) WiFi LAN 802.11b capability (Texas Instruments TNETW1100B) Bluetooth (Texas Instruments BRF6150USB) RS232 port, 16550 compatible (PXA270) Integrated microphone,speaker and stereo headset jack Audio codec (AK4641) USB (PXA270) Weight: 186.7 g

HP iPAQ hx4700 series PocketPC

CSA Rob Williams CSA ch 21 - p 305 Pearson Education (c) 2006 Bank Sel line MBytes Physical Address 384 Reserved FFFF_FFFFH 3128 zeros 3RAS/CAS3 128 DRAM bank 3 3RAS/CAS2 128 DRAM bank 2 3RAS/CAS1 128 DRAM bank 1 3RAS/CAS0 128 DRAM bank 0 2256 LCD &DMA registers 2256 Expansion &memor y  2256 SCM registers  inter nal to SA1110 2256 PM registers  StrongARM 768 Reserved 1CS5 128 Flash/SRAM bank 5 1CS4 128 Flash/SRAM bank 4 0PSTSEL 256 PCMIA socket1 0!PSTSEL 256 PCMIA socket0 0CS3 128 Flash/SRAM bank 3 0CS2 128 Flash/SRAM bank 2 0CS1 128 Flash/SRAM bank 1 0CS0 128 Flash bank 0 0000_0000H

SA1110 StrongARM 4 GByte memorymap

op code → Stage 0 16 KByte +4 Fetch instr I-cache incr PC from I-cache IR-0

← reg write branch offset Stage 1 R15/PC ↓ decoder Decode,

+disp reg read, branch Register File get branch addr. ←addr immediate ﬁelds ↓ IR-1

+4 shifter Stage 2

decoder Execute ALU & multiply ALU/shift, LD/ST mem addr. mux

IR-2

B-repl

8KByte 0.5 KByte Stage 3 → D-cache Minicache LD/ST address D-cache LD/ST

rotate

IR-3 Stage 4 Wr ite Register Result wr ite-back

Blockdiagramfor the StrongARM core

CSA Rob Williams CSA ch 21 - p 307 Pearson Education (c) 2006 PLL 3.686 MHz IMMU Icache oscil ARM PLL JTAG SA-1 i/f 32.768 KHz DMMU Dcache oscil core Minicache RTC LCD OS timer wr ite buff read buff control GP I/O

Intr Cntrl Pwr Mngt Br idge DMA Memor y Rst Contrl control &PCMCIA control A -A 0 25 D -D 0 31 Ser ial Ser ial Ser ial Ser ial Ser ial channel 0 channel 1 channel 2 channel 3 channel 4 USB UART IrDA UART CODEC

Intel SA1110 StrongARM microcontroller

LOCAL GLOBAL

0 OUT IN cwp 0 LOCAL

OUT IN

LOCAL CPU registers

OUT IN

LOCAL

Save Restore IN

system Main Memory stack

Operation of the Register File during procedure calls

L1 Icache 16 kbyte,64byte line L1 Dcache 16 kbyte,64byte line,write-through L2 256 kbyte,128 byte line,write-back L3 3-9 Mbyte,128 byte line,write-back main memory<1Pbyte (264) Clock1.66 GHz System bus 400 MHz, 128 bits wide CPU power100 watts

Itanium 2 processor parameters

Op Field4 Field3 Field2 Field1 pred code 40 37 36 27 26 20 19 1312 6 5 0

Instr uction Bundle for the IA-64 Architecture

CSA Rob Williams CSA ch 22 - p 312 Pearson Education (c) 2006 General Regs NAT Floating-Point Regs IP Application Regs 63 0 81 0 63 0 63 0 gr0 0 +0.0 KR0 ar0 gr1 +1.0 gr2 Predicate Flags KR7 63 0 RSC BSP Branch Regs BSPstore 63 0 RNAT br0 gr125 br1 FCR gr126 br2 EFLAG gr127 br3 CSD br4 SSD br5 CFM CFLG 37 0 br6 FSR br7 FIR FDR

CCV

UNAT

FPSR ITC

PFS LC EC

ar127

Intel IA-64 / Itanium Register Set

CSA Rob Williams CSA ch 22 - p 313 Pearson Education (c) 2006 Register name title class usage Gr r0 constant reads as zero 0 Gr r1 gp special global data pointer 1 Gr -Gr r2-r3 scratch used with addl 2 3 Gr -Gr r4-r7 preserved 4 7 Gr -Gr r8-r11 ret0-ret3 scratch returnvalues 8 11 Gr r12 sp special stackpointer 12 Gr r13 tp special thread pointer 13 Gr -Gr r14-r31 scratch 14 31 Gr -Gr r32-r39 in0-in7 automatic function params 32 39 Gr -Gr r32-r127 automatic input registers 32 127 loc0-loc95 automatic local registers out0-out95 automatic output registers automatic rotating registers (groups of 8)

Asm programmers’ usage of Itanium registers

CSA Rob Williams CSA ch 22 - p 314 Pearson Education (c) 2006 Type AALU operations,arithmetic on integers and logic Imultimedia, integer shifts,special register ops Mmemor y load/store operations Bbranching, jumping and returning Fﬂoating-point operations Xspecial instructions

Itanium instruction classes

CSA Rob Williams CSA ch 22 - p 315

Pearson Education (c) 2006 Template Slot0 Slot1 Slot2 00 M-unit I-unit I-unit 01 M-unit I-unit I-unit || 02 M-unit I-unit || I-unit 03 M-unit I-unit || I-unit || 04 M-unit L-unit X-unit 05 M-unit L-unit X-unit || 06 07 08 M-unit M-unit I-unit 09 M-unit M-unit I-unit || 0A M-unit || M-unit I-unit 0B M-unit || M-unit I-unit 0C M-unit F-unit I-unit 0D M-unit F-unit I-unit || 0E M-unit M-unit F-unit 0F M-unit M-unit F-unit || 10 M-unit I-unit B-unit 11 M-unit I-unit B-unit || 12 M-unit B-unit B-unit 13 M-unit B-unit B-unit || 14 15 16 B-unit B-unit B-unit 17 B-unit B-unit B-unit || 18 M-unit M-unit B-unit 19 M-unit M-unit B-unit || 1A 1B 1C M-unit F-unit B-unit 1D M-unit F-unit B-unit || 1F M-unit I-unit I-unit

Template ﬁeld encoding for Itanium 2, showing the positions of inter-instruction stops

/* selection_sort.c Agood basic sort routine. Works by scanning up through the array finding the "smallest" item, which it then swaps with the item at the start of the scan. It then scans again, starting at the second position, looking for the next smallest item... and so on. */ int selectionsort(char *pc[ ], int n ) { int min, i, j, k; char *pctemp; for (i = 0; i < n; i++) { min = i; for(j = i+1; j < n; j++) if (strcmp(pc[j], pc[min]) > 0) min = j; pctemp = pc[min]; pc[min] = pc[i]; pc[i] = pctemp; for(k=0; k

for(i=0; i < 7; i++) names[i] = testset[i]; printf("\n\nSelection Sort\n"); i=selectionsort(names, 7); }

CSA Rob Williams CSA ch 22 - p 317 Pearson Education (c) 2006 .file "selection_sort.c" .L6: ;FOR j loop .pred.safe_across_calls p1-p5,p16-p63 adds r14 = -12, r36 .section .rodata adds r15 = -24, r36 .align 8 ;; .LC0: stringz "%s " ld4 r16 = [r14] ;get npntr .align 8 ld4 r14 = [r15] ;get jpntr .LC1: stringz "\n" ;; .text cmp4.gt p6, p7 = r14, r16 .align 16 (p6) br.cond.dptk .L9 .global selectionsort# br .L7 .proc selectionsort# ;; ;Exit j FOR loop selectionsort: .L9: adds r14 = -12, r36 .prologue 14, 34 ;; .save ar.pfs, r35 ld4 r14 = [r14] alloc r35 = ar.pfs, 2, 4, 2, 0 ;; .vframe r36 sxt4 r14 = r14 mov r36 = r12 ;; adds r12 = -48, r12 shladd r15 = r14, 3, r0 mov r37 = r1 adds r16 = -32, r36 .save rp, r34 ;; mov r34 = b0 ld8 r14 = [r16] .body ;; ;; add r16 = r15, r14 adds r14 = -32, r36 adds r14 = -20, r36 ;; ;; st8 [r14] = r32 ld4 r14 = [r14] adds r14 = -24, r36 ;; ;; sxt4 r14 = r14 st4 [r14] = r33 ;; adds r14 = -16, r36 shladd r15 = r14, 3, r0 ;; adds r17 = -32, r36 st4 [r14] = r0 ;; .L2: ;FOR i loop ld8 r14 = [r17] adds r14 = -16, r36 ;; adds r15 = -24, r36 add r14 = r15, r14 ;; ld8 r38 = [r16] ld4 r16 = [r14] ;; ld4 r14 = [r15] ld8 r39 = [r14] ;; br.call.sptk.many b0 = strcmp# cmp4.gt p6, p7 = r14, r16 mov r1 = r37 (p6) br.cond.dptk .L5 mov r14 = r8 br .L3 ;; ;; ;Exit FOR i loop cmp4.ge p6, p7 = 0, r14 .L5: adds r15 = -20, r36 (p6) br.cond.dptk .L8 adds r14 = -16, r36 adds r14 = -20, r36 ;; adds r15 = -12, r36 ld4 r14 = [r14] ;; ;; ld4 r15 = [r15] st4 [r15] = r14 ;; adds r15 = -12, r36 st4 [r14] = r15 adds r14 = -16, r36 ;get ipntr .L8: adds r15 = -12, r36 ;; adds r14 = -12, r36 ld4 r14 = [r14] ; ;;  ;; ld4 r14 = [r14] adds r14 = 1, r14 ;  incr i ;; ;; adds r14 = 1, r14 st4 [r15] = r14 ;  ;; st4 [r15] = r14 br .L6 ;;

CSA Rob Williams CSA ch 22 - p 318 Pearson Education (c) 2006 .L7: mov r16 = r36 ;get temppntr .L11: ;FOR k loop adds r14 = -20, r36 adds r14 = -8, r36 ;get kpntr ;; adds r15 = -24, r36 ld4 r14 = [r14] ;; ;; ld4 r16 = [r14] sxt4 r14 = r14 ld4 r14 = [r15] ;; ;; shladd r15 = r14, 3, r0 cmp4.gt p6, p7 = r14, r16 adds r17 = -32, r36 (p6) br.cond.dptk .L14 ;; br .L12 ld8 r14 = [r17] ;; ;Exit k FOR loop ;; .L14: adds r14 = -8, r36 add r14 = r15, r14 ;; ;; ld4 r14 = [r14] ld8 r14 = [r14] ; ;;  ;; ;  pctemp=pc[min] sxt4 r14 = r14 st8 [r16] = r14 ;  ;; adds r14 = -20, r36 shladd r15 = r14, 3, r0 ;; adds r17 = -32, r36 ld4 r14 = [r14] ;; ;; ld8 r14 = [r17] sxt4 r14 = r14 ;; ;; add r15 = r15, r14 shladd r15 = r14, 3, r0 addl r14 = @ltoffx(.LC0), r1 adds r16 = -32, r36 ;; ;; ld8.mov r38 = [r14], .LC0 ld8 r14 = [r16] ld8 r39 = [r15] ;; br.call.sptk.many b0 = printf# add r16 = r15, r14 mov r1 = r37 adds r14 = -16, r36 ;get ipntr adds r15 = -8, r36 ;get dest kpntr ;; adds r14 = -8, r36 ;get src kpntr ld4 r14 = [r14] ;; ;; ld4 r14 = [r14] ;  sxt4 r14 = r14 ;sign extend i ;; ;; adds r14 = 1, r14 ;  incr k shladd r15 = r14, 3, r0;ix8 ;; adds r17 = -32, r36 st4 [r15] = r14 ;  ;; br .L11 ld8 r14 = [r17] ;; ;; .L12: addl r14 = @ltoffx(.LC1), r1 add r14 = r15, r14 ;build pntr ;; ;; ld8.mov r38 = [r14], .LC1 ld8 r14 = [r14] ; br.call.sptk.many b0 = printf#  ;; ;  pc[min]=pc[i] mov r1 = r37 st8 [r16] = r14 ;  adds r15 = -16, r36 ;get Dest ipntr adds r14 = -16, r36 ;get ipntr adds r14 = -16, r36 ;get Src ipntr ;; ;; ld4 r14 = [r14] ;get i ld4 r14 = [r14] ;  ;; ;; sxt4 r14 = r14 adds r14 = 1, r14 ;  incr i ;; ;; shladd r15 = r14, 3, r0;ix8 st4 [r15] = r14 ;  adds r16 = -32, r36 ;get pc[] base br .L2 ;Bottom of i loop ;; ;; ld8 r14 = [r16] .L3: mov r14 = r0 ;; ;; add r15 = r15, r14 ;build pc[i] pntr mov r8 = r14 mov r14 = r36 ;get pctemppntr mov ar.pfs = r35 ;saveFP ;; mov b0 = r34 ld8 r14 = [r14] ; .restore sp  ;; ;  pc[i]=pctemp mov r12 = r36 st8 [r15] = r14 ;  br.ret.sptk.many b0 adds r14 = -8, r36 ;get kpntr ;; ;; .endp selectionsort# st4 [r14] = r0 ;zero k

CSA Rob Williams CSA ch 22 - p 319 Pearson Education (c) 2006 .text ;Code Section .L16: ;star t of FOR i loop .align 16 adds r15 = -128, r34 .global main# ;; ;names[]=testset[] .proc main# ld4 r14 = [r15] ;get i main: .prologue 14, 32 ;; .save ar.pfs, r33 cmp4.ge p6, p7 = 6, r14 alloc r33 = ar.pfs, 0, 4, 2, 0 (p6) br.cond.dptk .L19 ;test end of FOR loop .vframe r34 br .L17 mov r34 = r12 ;set FP from SP ;; adds r12 = -144, r12 ;open stackframe .L19: adds r15 = -112, r34;get Destpntr mov r35 = r1 adds r16 = -128, r34 ;get ipntr .save rp, r32 ;; ;local var iables mov r32 = b0 ;savebranch reg ld4 r14 = [r16] ;get i .body ;; ;; sxt4 r14 = r14 ;sign extend adds r15 = -48, r34 ;build tablepntr ;; addl r14 = @ltoffx(.LC2), r1;build RAM pntr shladd r14 = r14, 3, r0;ix8 ;; ;using offset+base pntr ;; ld8.mov r14 = [r14], .LC2 add r16 = r14, r15 ;indexDestpntr ;; adds r15 = -48, r34 ;get Srcpntr st8 [r15] = r14 ;savestr npntr in table adds r17 = -128, r34 ;get ipntr adds r16 = 8, r15 :bump pntr ;; addl r14 = @ltoffx(.LC3), r1 ld4 r14 = [r17] ;get i ;; ;"Tuesday" ;; ld8.mov r14 = [r14], .LC3 sxt4 r14 = r14 ;sign extend ;; ;; st8 [r16] = r14 ;savestr npntr in table shladd r14 = r14, 3, r0:ix8 adds r16 = 16, r15 ;; addl r14 = @ltoffx(.LC4), r1 add r14 = r14, r15 ;indexSrcpntr ;; ;"Wednesday" ;; ld8.mov r14 = [r14], .LC4 ld8 r14 = [r14] ;|get next_word ;; ;; :| st8 [r16] = r14 ;savestr npntr in table st8 [r16] = r14 ;|put next_word adds r16 = 24, r15 adds r15 = -128, r34 ;get ipntr addl r14 = @ltoffx(.LC5), r1 ;; ;; ;"Thursday" ld4 r14 = [r15] ;get i ld8.mov r14 = [r14], .LC5 ;; ;; adds r14 = 1, r14 ;incr i st8 [r16] = r14 ;savestr npntr in table adds r16 = -128, r34 ;get ipntr adds r16 = 32, r15 ;; addl r14 = @ltoffx(.LC6), r1 st4 [r16] = r14 ;savei ;; ;"Fr iday" br .L16 ;bottom of FOR ld8.mov r14 = [r14], .LC6 ;; ;; .L17: addl r14 = @ltoffx(.LC9), r1 st8 [r16] = r14 ;savestr npntr in table ;; adds r16 = 40, r15 ld8.mov r36 = [r14],.LC9;print banner addl r14 = @ltoffx(.LC7), r1 br.call.sptk.many b0 = printf# ;; ;"Saturday" mov r1 = r35 ;retur n value ld8.mov r14 = [r14], .LC7 adds r14 = -112, r34 ;get Destpntr ;; ;; st8 [r16] = r14 ;savestr npntr in table mov r36 = r14 ;param1=Destpntr adds r15 = 48, r15 addl r37 = 7, r0 ;param2=7 addl r14 = @ltoffx(.LC8), r1 br.call.sptk.many b0 = selectionsort# ;call sortroutine ;; mov r1 = r35 ;get returnvalue ld8.mov r14 = [r14], .LC8 mov r14 = r8 ;; ;"Sunday" adds r17 = -128, r34 ;get ipntr st8 [r15] = r14 ;savestr npntr in table ;; adds r14 = -128, r34 ;build ipntr st4 [r17] = r14 ;store in i ;; mov ar.pfs = r33 st4 [r14] = r0 ;clear i mov b0 = r32 ;restore branch addr .restore sp mov r12 = r34 ;restore SP br.ret.sptk.many b0 RETURN to shell ;; .endp main# .ident "GCC: (GNU) 3.3.5 (Debian 1:3.3.5-13)"

CSA Rob Williams CSA ch 22 - p 320 Pearson Education (c) 2006 .section .rodata ;Constants Section .align 8 .LC2: stringz "Monday";constant strings store .align 8 .LC3: stringz "Tuesday" .align 8 .LC4: stringz "Wednesday" .align 8 .LC5: stringz "Thursday" .align 8 .LC6: stringz "Friday" .align 8 .LC7: stringz "Saturday" .align 8 .LC8: stringz "Sunday" .align 8 .LC9: stringz "\n\nSelection Sort\n"

Itanium assembler code produced bygcc

Source code window

Disassembler window

gdb window

Linux-64 with gvd/gdb debugger to watch Itanium code

Programhas N instructions Instr uctions take τ secs each to complete Uni-processor run time will be Nxτ IDEALLY, P p rocessors could reduce run time to (Nτ )/P But only a fraction of real application code can be parallelized: Nτ (1 − f ) total _time = serial _part + parallel _part = Nτ f + P While f is the fraction of the problem that must be carried out sequentially due to data or control dependencies,(1−f)isthe fraction which can run in parallel. Note that f + (1 − f )evaluates to 1. P is the number of processors available. The speed-up-ratio is then deﬁned as the uni-processor-time divided bythe (smaller!) multi-processor-time,which is: Nτ 1 speed _up_ratio: S = = Nτ (1 − f ) f + (1 − f )/P Nτ f + P

Parallelizable code,Amdahl’sLaw

0.9 x6

x5 atio x4 0.8 peed-up r

,s x3

S 0.7

x2 0.5

0.3 x1 0.1

2 4 6 8 10 12 14

P,number of CPUs

Amdahl’sLaw plotted for 1-15 processors and 0.1 - 0.9 compliant code

CSA Rob Williams CSA ch 23 - p 325 Pearson Education (c) 2006 Instr uction Data stream stream SISD Single Single Personal PC word processing SIMD Single Multiple Vector processors geological simulation MISD Multiple Single Possibly none. MIMD Multiple Multiple Central serverWWW search engine Flynn’sprocessor taxonomy

local local local memor y memor y memor y

CPU1 CPU2 CPU3 CPU1 CPU2 CPU3 CPU1 CPU2 CPU3

cache cache cache cache cache cache

System bus copies data shared shared memor y memor y memor y

Single bus,shared memorymulti-processing (SMP)

Cache event Action Read Hit cache read Miss main memor y read cache update Wr ite Hit main memor y wr ite cache markedstale Miss main memor y wr ite Cache coherency protocol with write-through

CPU1 CPU2 CPU3 cache cache cache

CPU5 CPU4 CPU6 cache cache cache

local local local memor y memor y memor y

Hardware conﬁguration for an MPI system int MPI_Send( void* sendBuf, int count, MPI_Datatype datatype, int destinationRank, int tag, MPI_Comm comm) int MPI_Recv( void* recvBuf, int count, MPI_Datatype datatype, int sourceRank, int tag, MPI_Comm comm, MPI_Status *status) int MPI_Bcast ( void* buffer, int count, MPI_Datatype datatype, int root, MPI_Comm comm )

I-fetch Front Control end Logic Decode Dispatch

Execution Logic BU SCU L/SU Vper m SPU1 SPU2 Byte FX1 FX2 Vector arithmetic units

R-commit Control unit

The IBM/SonyCell SPE unit

32 kB L1

512 kB L2

SPE 7 SPE 3

SPE 6 SPE 2

SPE 5 SPE 1

SPE 4 SPE 0

MIC BIC 2x XDR FlexIO

Cell schematic architecture

workstations

Switching Hub

Asingle switched hub Cluster with Star topology

Application Inter net or iginator

Gr id computing

Fr i Jan500:09:48 GMT 2007 localhost

CSA Rob Williams CSA ch 23 - p 331