Lianly Rompis. A Random Counter in ... 64 A RANDOM COUNTER IN USING SHIFT REGISTER AND ENCODER Lianly Rompis Program Studi Teknik Elektro; Fakultas Teknik Universitas Katolik De La Salle Manado; Kombos – Kairagi I Manado, No.Telp:(0431) 871957 e-mail: [email protected] AbstractMostly some specific computer circuits and digital circuit applications need a random counter circuit module for handling specific tasks or operations. To design this kind of circuit, it is more common to use the standard format design of synchronous counter, although this will be more complicated to derive its truth table and karnaugh-maps in order to solve the right output equations for flip-flop inputs. This paper will introduce another way of designing a digital random counter, Figure. 1. A 3-bit Synchronous Counter using shift register and encoder, which is easier to applied and the sequence of this counter can be managed randomly. The methodology being used for this research is mainly to understand the basic concept and combine the functions of shift TABLE 1. register and encoder, to derive a new and simple form of THE BIT SEQUENCE OF 3-BIT SYNCHRONOUS COUNTER designing a random counter. Using an Electronics Workbench software, the outputs are shown in logic simulation. FF2 FF1 FF0 0 0 0 Keywords-Random Counter, Synchronous Counter, Shift 0 0 1 Register, Encoder 0 1 0 0 1 1 1 I. INTRODUCTION 1 0 0 1 0 1 A random counter is mainly designed using D-FF and T- 1 1 0 FF, but JK-FF and RS-FF are still used in several purposes of 1 1 1 design. The important problem, we couldn’t arrange the sequences as we want to. If we need to design a random counter with specific sequences or orders, or according to our Shift register is another type of sequential logic circuit, design problem, we usually should use synchronous counter mainly for storing digital data. They are a group of flip-flops, design. As being known, this kind of standard method is usually D-FF, connected in series so that the output from one working, and of course need a lot more work to do, define flip-flop becomes the input of the next flip-flop, and so on truth table, draw the k-map, and find the equations for each [1, 2, 5]. All the flip-flops are driven by a common clock, flip-flop inputs. and all are set or reset simultaneously. Figure 2 shows a right Synchronous Counter is a type of sequential logic circuit shift register built from an array of D-FFs. With this logic functions for counting binary information, which clock input circuit connection, the first input will become the first output of all the flip-flop components are connected together and and stands as a Least Significant Bit. The last input will triggered positively or negatively by the input pulses. Thus, become the last output and stands as a Most Significant Bit. all the flip-flops would change current state simultaneously, Table 2 shows the truth table of this register. in parallel [1, 2, 6, 7]. The number of bit depends on number Encoder is a type of general logic function circuit, a of flip-flop being used. For example, in figure 1, in order to combinational circuit, mostly used in data encoding. The have a design output values in 3-bit length, the number of design for encoder comes from logic gate circuits. It has an JK- flip-flop that we used is 3 (three) also. This 3-bit input of 2nlines and output n lines as being referred in [1, 2, synchronous counter will give binary outputs from zero (000) 3, 4]. to seven (111). The logical connection build a counter that Using these circuits’ characteristics and each component counts in sequence with Q2 as the Most Significant Bit properties, there could be a way to design a random counter (MSB) and Q0 as the Least Significant Bit (LSB). The bit- for computer circuit or digital circuit applications. sequences are given in Table 1. JURNAL REALTECH Vol. 14, No.1, April 2018: 64-68 ISSN: 1907-0837 65 Figure. 2. Right Shift Register Figure. 3. Encoder (8 to 3) TABLE 2. TRUTH TABLE OF A SERIAL RIGHT SHIFT REGISTER TABLE 3. TRUTH TABLE OF AN ENCODER (8 TO 3) Clock Input=D1 Q1 Q2 Q3 Q4=Output 0 0 0 0 0 INPUTS OUTPUT 1 1 0 0 0 0 1 2 3 4 5 6 7 A2A1A0 0 1 1 1 1 1 1 1 111 0 1 0 0 0 x 0 1 1 1 1 1 1 110 1 1 0 1 0 x x 0 1 1 1 1 1 101 0 0 1 0 1 x x x 0 1 1 1 1 100 0 0 0 1 0 x x x X 0 1 1 1 011 x x x X x 0 1 1 010 0 1 0 0 0 x x x x x x 0 1 001 0 0 0 0 0 x x x x x x x 0 000 What will happen if we try to modify the right shift II. METHOD register circuit by adding an XNOR gate? With this circuit connection, the LED light will light one by one each cycle: A. Aims of Study 100, 010, 001, 100, … etc. The related logic circuit is shown This paper introduces an alternative way of designing a in Figure 4. We can learn the characteristic of XNOR gate simple random counter that could be used to conduct advance from the following Table 4. digital analysis or solve digital problems. Hopefully it will give a great contribution in digital science and technology, and will help students, lecturers, designers, scientists, and academics to be able to understand the parts of digital circuit. B. Methodology Learning from several methodologies from Journal [10], the methodology being used for this research mainly to understand the basic concept and combine the functions of shift register and encoder, to derive a new and simple form of Figure. 4. Right Shift Register with XNOR Gate designing a random counter. TABLE 4. TRUTH TABLE OF AN XNOR GATE III. RESULTS AND DISCUSSION INPUTS OUTPUTS A right shift register has a very simple form like the A B Y circuit diagram in Figure 2. It functions a serial input. The 0 0 1 binary input will come from the left side, and shifted to the 0 1 0 right. Every clock cycle will shift one bit to the right. We can 1 0 0 add as many flip-flops as we need, according to our design, as 1 1 1 explained in [2,3,5,9]. A simple form of low-active encoder is shown in Figure 3. At an initial condition, the outputs of all Flip-flops are 0s and The outputs will activate a binary number combination based will turn into 1s if the inputs are 1s. From the circuit we can on the active input and priority. To understand how a priority see that Q =0 and Q =0, being an input for XNOR Gate. The encoder works, there is a characteristic table being given in 1 2 output of Xnor gate will give logic 1, so input D will become Table 3. If logic 1 is given to more than one input of priority 1. The next clock cycle will set the output of Q =1, and encoder, the output will read the highest input level, and 1 followed by Q =1 again in the next cyle. When Q was transfer it as a combination of output. 2 1 changing into 1s, Xnor gate will give an output of 0s, turn D Lianly Rompis. A Random Counter in ... 66 into 0s once again. The next cycle will give an output of Q1=0, and so on. These happen continuously and build a same loop of function. If we use the output function of right shift register as an input for encoder, added with few additional digital components, we can state clearly that we have created a random counter. This circuit can be a main circuit for any random counter. To change or random the sequences, we only have to change the connection to encoder inputs according to the sequence. From the example in Figure 5, we can figure out that the circuit is a random counter with sequence: 0, 1, 3, 6, 0, 1, …, etc. This is proven by the simulation shown in figure 6 until figure 8. Figure. 8. The third output of Random Counter is 6 A logic 1 will be looped and shifted continuously from all Qn outputs. The 8 to 3 encoder has low enable inputs, so it is necessary to change all the inputs logic before connect them as inputs for encoder, which makes the encoder works according to the characteristics given in table 3. In here we can use NOT logic gates to convert the inputs from one to zero or zero to one. Because the outputs form encoder also low enable outputs, again we have to use NOT logic gates to convert those outputs logic that will then display the outputs related to Figure. 5. Random Counter using Shift Register and Encoder logical inputs shown in table 3. This random counter circuit will count based on the order of inputs given by the Qn states of right shift register. It will followed the logic sequence, the logic 1 movement from the beginning, precisely from the left to the right. In figure 5 we can see that the connection is built to the input 1, 3, and 6 of encoder, respectively.