8-Bit 0 D1 Load Reg1 a 4×1 O • Ch2 Example: Four A0 V

Home , Barrel shifter, Counter (digital)

Digital Design

Chapter 4: Datapath Components

• Chapters 2 & 3: Introduced increasingly complex digital building blocks – Gates, multiplexors, decoders, basic registers, and controllers • Controllers good for systems with control inputs/outputs – Control input: Single bit (or just a few), representing environment event or state • e.g., 1 bit representing button pressed – Data input: Multiple bits collectively representing single entity

• e.g., 7 bits representing temperature in binary ansis • Need building blocks for data – Datapath components, aka register-transfer-level (RTL) components,

store/transform data z • Put datapath components together to form a datapath • This chapter introduces numerous datapath components, and simple datapaths – Next chapter will combine controllers and datapaths into “processors”

b x • Can store data, very common in datapaths Combinational n1 logic • Basic register of Ch 3: Loaded every cycle n0 s1 s0 – Useful for implementing FSM -- stores encoded state clk State register – For other uses, may want to load only on certain cycles a load I3 I2 I1 I0 4-bit register I3 I2 I1 I0 D D D D si Q Q Q Q ansis reg(4)

clk Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0 z Basic register loads on every clock cycle How extend to only load on certain cycles?

• Add 2x1 mux to front of each flip-flop • Register’s load input selects mux input to pass – Either existing flip-flop value, or new value to load I3 I2 I1 I0 10 10 10 10 load 2⋅ 1 I3 I2 I1 I0 load D D D D Q3 Q2 Q1 Q0 Q Q Q Q Q3 Q2 Q1 Q0 (a) (c)

I3 I2 I1 I0 I3 I2 I1 I0 0 1 = 10 10 10 10 = 10 10 10 10 d d a a lo lo D D D D D D D D Q Q Q Q Q Q Q Q Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Digital Design (b ) Copyright © 2006 4 Frank Vahid Basic Example Using Registers

a3 a2 a1 a0

I3 I2 I1 I0 • This example will show how 1 ld clk R0 registers load simultaneously Q3 Q2 Q1 Q0 on clock cycles – Notice that all load inputs set to 1 in this example -- just for demonstration purposes 1 ld I3 I2 I1 I0 1 ld I3 I2 I1 I0 R1 R2 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

cl k

n 1234 5 (a) e v

gi a3..a0 1111 0001 1010

R0 ???? 1111 0001 1010 1010 1010

R1 ???? ???? 1111 0001 1010 1010

R2 ???? ???? 0000 1110 0101 0101 –> 1111 1111–> 0001 0001–> 1010 1010 1010 1010 a3 a2 a1 a0

1 ld I3 I2 I1 I0 ???? R0 1111 R0 0001 R0 1010 R0 1010 R0 1010 R0 clk R0 Q3 Q2 Q1 Q0 (b )

???? ???? ???? ???? 1111 0000 0001 1110 1010 0101 1010 0101 R1 R2 R1 R2 R1 R2 R1 R2 R1 R2 R1 R2

1 ld I3 I2 I1 I0 1 ld I3 I2 I1 I0 R1 R2 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

Digital Design Copyright © 2006 6 Frank Vahid Register Example using the Load Input: Weight Sampler • Scale has two displays – Present weight – Saved weight Scale Weight Sampler – Useful to compare 00110010 present item with previous Save item b 1 I3 I2 I1 I0 a 32 pounds load 0011 • Use register to store Present weight clk Q3 Q2 Q1 Q0 weight – Pressing button causes

present weight to be 3 pounds stored in register Saved weight • Register contents always displayed as “Saved weight,” even when new present weight appears

Digital Design Copyright © 2006 7 Frank Vahid Register Example: Temperature History Display • Recall Chpt 3 example – Timer pulse every hour – Previously used as clock. Better design only connects oscillator to clock inputs -- use registers with load input, connect to timer pulse.

a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0 I4 Q4 I4 Q4 I4 Q4 t4 I4 Q4 I4 Q4 I4 Q4 x4 I3 Q3 I3 Q3 I3 Q3 t3 I3 Q3 I3 Q3 I3 Q3 x3 I2 Q2 I2 Q2 I2 Q2 t2 I2 Ra Q2 I2 RbQ2 I2 RcQ2 x2 I1 Q1 I1 Q1 I1 Q1 t1 I1 Q1 I1 Q1 I1 Q1 x1 I0 Q0 I0 Q0 I0 Q0 t0 I0 Q0 I0 Q0 I0 Q0 x0 ld ld ld Clk Ra Rb Rc osc C C TemperatureHistoryStorage a timer new line TemperatureHistoryStorage

Shorthand notation a 0001010

er C t 8 Loaded on clock edge d0 load reg0 T

ompu

o theab

i0 r

r 2⋅ 4 or displ

omthe car's

n 8

c 1 8-bit 0 d1 load reg1 A 4×1 o • Ch2 example: Four a0 v

0001010 e i0 y simultaneous values from i1 car’s computer 1 i1 8 a1 d D • To reduce wires: Computer d2 load reg2 I 8 writes only 1 value at a time, i2 loads into one of four 8 registers d3 load e reg3 M – Was: 8+8+8+8 = 32 wires 1 load i3 s1 s0 – Now: 8 +2+1 = 11 wires 8

• Each register LED lit LED holds values for 1

one column of 0 lights 1 – 1 lights light 0 • Microprocessor loads one 0 register at a time 0 – Occurs fast 1 enough that 0 user sees Q R7 R6 R5 R4 R3 R2 R1 R0 R0 10100010 entire board I load

change at once d7 d6 d5 d4 d3 d2 d1 d0 8 ei2i1i03⋅ 8 decoder from from microprocessor decoder D (b) microprocessor Digital Design (a) Copyright © 2006 10 Frank Vahid Register Example: Computerized Checkerboard

LED

lit LED

R7 R6 R5 R4 R3 R2 R1 R0 10100010 10100010 10100010 10100010 01000101 01000101 01000101 01000101

D 10100010 010000101 10100010 010000101 10100010 010000101 10100010 010000101 i2,i1,i0 000 (R0) 001 (R1) 010 (R2) 011 (R3) 100 (R4) 101 (R5) 110 (R6) 111 (R7) e clk

Digital Design Copyright © 2006 11 Frank Vahid Shift Register Register contents 1 1 0 1 before shift right • Shift right 0 a Register contents – Move each bit one position right 0 1 1 0 after shift right – Shift in 0 to leftmost bit

Q: Do four right shifts on 1001, showing value after each shift

a A: 1001 (original) 0100 • Implementation: Connect flip-flop 0010 output to next flip-flop’s input 0001 shr_in a 0000

• To allow register to either shift or retain, use 2x1 muxes – shr: 0 means retain, 1 shift – shr_in: value to shift in • May be 0, or 1 • Note: Can easily design shift register that shifts left instead

shr_in 1

shr 10 10 10 10 = 10 10 10 10 r 2⋅ 1 2⋅ 1 sh D D D D D D D D Q Q Q Q Q Q Q Q Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 (b) (a) shr_in shr

Register contents 1 1 0 1 before shift right • Rotate right: Like shift right, Register contents 1 1 1 0 but leftmost bit comes from after shift right rightmost bit

r s e

s C t '

r 8

a e c d0 loa d e re g 0 T ompu h r mi To c l

i r t

• Earlier example: 8 a

i0 r r or 2 ⋅ 4 h t om t r e

n 8 di F

e a

c 8- b i t b w d1 s

loa d p re g 1 A 4 ⋅ 1 o

l a0 v a

+2+1 = 11wires from e i0 y 1 i1 i1 8 1 a1 d D car’s computer to d2 loa d re g 2 I 8 i2 8 above-mirror display’s d3 loa d e re g 3 M loa d i3 four registers 8 s1 s0 xy – Better than 32 wires, Note: this line is 1 bit, rather than 8 bits like before but 11 still a lot -- c xy want fewer for shr_in d0 shr reg0 T smaller wire bundles s1 s0 2⋅ 4 i0 • Use shift registers 8 shr_in 4×1 – Wires: 1+2+1=4 d1 shr reg1 A a0 i0 – Computer sends one i1 a1 i1 8 value at a time, one shr_in d D d2 shr reg2 I 8 bit per clock cycle i2 8 shr_in shr e d3 reg3 M Digital Design shift i3 Copyright © 2006 8 15 Frank Vahid Multifunction Registers • Many registers have multiple functions – Load, shift, clear (load all 0s) – And retain present value, of course Functions: • Easily designed using muxes s1 s0 Operation – Just connect each mux input to achieve 0 0 Maintain present value 0 1 Parallel load desired function 1 0 Shift right 1 1 (unused - let's load 0s) sh r_in I3 I2 I1 I0 0 0 0 0 s1 321 0 321 0 321 0 321 0 s0 4⋅ 1 sh r_in I3 I2 I1 I0 s1 D D D D s0 Q3 Q2 Q1 Q0 Q Q Q Q

s1 s0 Operation 0 0 Maintain present value 0 1 Parallel load 1 0 Shift right 1 1 Shift left

I3 I2 I1 I0

shr_in shl_in

3210 3210 3210 3210 shl_in I3 I2 I1 I0 shr_in D D D D s1 s0

Q Q Q Q Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0 (a) (b) Digital Design Copyright © 2006 17 Frank Vahid Multifunction Registers with Separate Control Inputs ld shr shl Operation 0 0 0 Maintain present value 0 0 1 Shift left 0 1 0 Shift right 0 1 1 Shift right – shr has priority over shl 1 0 0 Parallel load 1 0 1 Parallel load – ld has priority I3 I2 I1 I0 1 1 0 Parallel load – ld has priority shr_in 1 1 1 Parallel load – ld has priority ld shr_in I3 I2 I1 I0 s1 shl_in combi- shl_in shr national s0 Truth table for combinational circuit circuit shl Q3 Q2 Q1 Q0 Inputs Outputs Note ? ld shr shl s1 s0 Operation Q3 Q2 Q1 Q0 0 0 0 0 0 Maintain value 1 1 Shift left 0 0 1 a 0 1 0 1 0 Shift right 0 1 1 1 0 Shift right 1 0 0 0 1 Parallel load s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl 1 0 1 0 1 Parallel load 1 1 0 0 1 Parallel load s0 = ld’*shr’*shl + ld a 1 1 1 0 1 Parallel load

• Register operations typically shown using compact version of table – X means same operation whether value is 0 or 1 • One X expands to two rows • Two Xs expand to four rows – Put highest priority control input on left to make reduced table simple

Inputs Outputs Note ld shr shl s1 s0 Operation ld shr shl Operation 0 0 0 0 0 Maintain value 0 0 0 Maintainvalue 0 0 1 1 1 Shift left 0 0 1 Shift left 0 1 0 1 0 Shift right 0 1 X Shift right 0 1 1 1 0 Shift right 1 X X Parallel load 1 0 0 0 1 Parallel load 1 0 1 0 1 Parallel load 1 1 0 0 1 Parallel load 1 1 1 0 1 Parallel load

• Can design register with desired operations using simple four-step process

Digital Design Copyright © 2006 20 Frank Vahid Register Design Example s2 s1 s0 Operation • Desired register operations 0 0 0 Maintain present value 0 0 1 Parallel load – Load, shift left, synchronous clear, 0 1 0 Shift left synchronous set 0 1 1 Synchronous clear 1 0 0 Synchronous set 1 0 1 Maintain present value Step 1: Determine mux size 1 1 0 Maintain present value 1 1 1 Maintain present value 5 operations: above, plus maintain In 10 from a present value (don’t forget this one!) Qn-1 s2 --> Use 8x1 mux s1 76543210 s0 Step 2: Create mux operation table D Step 3: Connect mux inputs Q Qn Step 4: Map control lines Inputs Outputs s2 = clr’*set clr set ld shl s2 s1 s0 Operation s1 = clr’*set’*ld’*shl + clr 0 0 0 0 0 0 0 Maintain present value 0 0 0 1 0 1 0 Shift left s0 = clr’*set’*ld + clr 0 0 1 X 0 0 1 Parallel load 0 1 X X 1 0 0 Set to all 1s Digital Design 1 X X X 0 1 1 Clear to all 0s Copyright © 2006 21 Frank Vahid a Register Design Example

I3 I2 I1 I0

I3 I2 I1 I0 shl s2 s1 shl_in ld combi- s0 shl_in national set circuit Q3 Q2 Q1 Q0 clr Q3 Q2 Q1 Q0

Step 4: Map control lines Inputs Outputs s2 = clr’*set clr set ld shl s2 s1 s0 Operation s1 = clr’*set’*ld’*shl + clr 0 0 0 0 0 0 0 Maintain present value 0 0 0 1 0 1 0 Shift left s0 = clr’*set’*ld + clr 0 0 1 X 0 0 1 Parallel load 0 1 X X 1 0 0 Set to all 1s Digital Design 1 X X X 0 1 1 Clear to all 0s Copyright © 2006 22 Frank Vahid 4.3 Adders

• Adds two N-bit binary numbers Inputs Outputs a1 a0 b1 b0 c s1 s0 – 2-bit adder: adds two 2-bit numbers, 0 0 0 0 0 0 0 0 0 0 1 0 0 1 outputs 3-bit result 0 0 1 0 0 1 0 – e.g., 01 + 11 = 100 (1 + 3 = 4) 0 0 1 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 • Can design using combinational 0 1 1 0 0 1 1 design process of Ch 2, but doesn’t 0 1 1 1 1 0 0 1 0 0 0 0 1 0 work well for reasonable-size N 1 0 0 1 0 1 1 – Why not? 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0

Digital Design Copyright © 2006 23 Frank Vahid Why Adders Aren’t Built Using Standard 4.3 Combinational Design Process • Truth table too big Inputs Outputs a1 a0 b1 b0 c s1 s0 – 2-bit adder’s truth table shown 0 0 0 0 0 0 0 (2+2) 0 0 0 1 0 0 1 •Has 2 = 16 rows 0 0 1 0 0 1 0 (8+8) 0 0 1 1 0 1 1 – 8-bit adder: 2 = 65,536 rows 0 1 0 0 0 0 1 (16+16) 0 1 0 1 0 1 0 – 16-bit adder: 2 = ~4 billion rows 0 1 1 0 0 1 1 0 1 1 1 1 0 0 – 32-bit adder: ... 1 0 0 0 0 1 0 1 0 0 1 0 1 1 1 0 1 0 1 0 0 • Big truth table with numerous 1s/0s yields 1 0 1 1 1 0 1 1 1 0 0 0 1 1 big logic 1 1 0 1 1 0 0 1 1 1 0 1 0 1 – Plot shows number of transistors for N-bit 1 1 1 1 1 1 0 adders, using state-of-the-art automated 10000 combinational design tool 8000 Q: Predict number of transistors for 16-bit adder

ors

t 6000 A: 1000 transistors for N=5, doubles for each

ansis 4000

(N-5) T a increase of N. So transistors = 1000*2 . Thus, Transistors for N=16, transistors = 1000*2(16-5) = 1000*2048 = 2000 2,048,000. Way too many! 0 12345678 Digital Design N Copyright © 2006 24 Frank Vahid Alternative Method to Design an Adder: Imitate Adding by Hand

• Alternative adder design: mimic 0 1 0 1 1 1 A: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 how people do a addition by hand B: + 0 1 1 0 + 0 1 1 0 + 0 1 1 0 + 0 1 1 0 • One column at a time 1 0 1 1 0 1 1 0 1 0 1 – Compute sum, add carry to next column

• Create 1 1 0 component for A: 1 1 1 1 each column B: + 0 1 1 0 – Adds that a column’s bits, 1 0 1 0 1 generates sum and carry bits 110

A: 1 111

+ B: 0 1 1 0

b aci b aci b aci b a co s co s co s co s 1 0 1 0 1 SUM

1 1 0 • Half-adder: Adds 2 bits, generates sum and carry A: 1 111 • Design using combinational design + B: 0 1 1 0

process from Ch 2 b aci b aci b aci b a Inputs Outputs co s co s co s co s a b co s 1 0 0 0 0 0 1 0 1SUM Step 1: Capture the function 0 1 0 1 1 0 0 1 1 1 1 0

Step 2: Convert to equations co = ab s = a’b + ab’ (same as s = a xor b) ab

ab Step 3: Create the circuit Half-adder

1 1 0 • Full-adder: Adds 3 bits, generates sum and carry A: 1 111 • Design using combinational design + B: 0 1 1 0

process from Ch 2 b aci b aci b aci b a co s co s co s co s 1 0 1 0 1SUM Step 1: Capture the function Step 2: Convert to equations Step 3: Create the circuit Inputs Outputs a b ci a b ci co s co = a’bc + ab’c + abc’ + abc 0 0 0 0 0 co = a’bc +abc +ab’c +abc +abc’ +abc 0 0 1 0 1 co = (a’+a)bc + (b’+b)ac + (c’+c)ab 0 1 0 0 1 co = bc + ac + ab 0 1 1 1 0 1 0 0 0 1 s = a’b’c + a’bc’ + ab’c’ + abc 1 0 1 1 0 s = a’(b’c + bc’) + a(b’c’ + bc) 1 1 0 1 0 s = a’(b xor c)’ + a(b xor c) Full 1 1 1 1 1 s = a xor b xor c adder

• Using half-adder and full-adders, we can build adder that adds like we would by hand • Called a carry-ripple adder – 4-bit adder shown: Adds two 4-bit numbers, generates 5-bit output • 5-bit output can be considered 4-bit “sum” plus 1-bit “carry out” – Can easily build any size adder

a3b3 a2b2 a1b1 a0 b0

a b ci a b ci a b ci a b a3a2a1a0 b3b2b1b0 FA FA FA HA 4-bit adder co s co s co s co s co s3 s2 s1 s0

co s3 s2 s1 s0 (a) (b)

Digital Design Copyright © 2006 29 Frank Vahid Carry-Ripple Adder • Using full-adder instead of half-adder for first bit, we can include a “carry in” bit in the addition – Will be useful later when we connect smaller adders to form bigger adders

a3b3 a2b2 a1b1 a0 b0 ci

a b ci a b ci a b ci a b ci a3a2a1a0 b3b2b1b0 FA FA FA FA 4-bit adder ci co s co s co s co s co s3 s2 s1 s0

co s3 s2 s1 s0 (a) (b)

0 00000 00 0000

a b ci a b ci a b ci a b ci FA FA FA FA Assume all inputs initially 0 co s co s co s co s 000 00 000

01001011 0000 0111+0001 (answer should be 01000) a b ci a b ci a b ci a b ci FA FA FA FA a co s co s co s co s 0010 co2 co1 co0 00110 Output after 2 ns (1FA delay)

0 01010 11 001 0 0111+0001 (answer should be 01000) a b ci a b ci a b ci a b ci FA FA FA FA co s co s co s co s 0 1 1 co1 00 1 0 0 Outputs after 4ns (2 FA delays) (b) 0 01010 11 0 01 1 0

a b ci a b ci a b ci a b ci FA FA FA FA co s co s co s co s 1 11 a co2 00 0 00Outputs after 6ns (3 FA delays) (c) 0 01010 11 01 110

a b ci a b ci a b ci a b ci FA FA FA FA co s co s co s co s 111 01 000Output after 8ns (4 FA delays) Digital Design (d) Copyright © 2006 Correct answer appears after 4 FA delays 32 Frank Vahid Cascading Adders

a7a6a5a4 b7b6b5b4 a3a2a1a0 b3b2b1b0 a3a2a1a0 b3b2b1b0 a3a2a1a0 b3b2b1b0 a7.. a0 b7.. b0

4-bit adder ci 4-bit adder ci 8-bit adder ci

co s3s2s1s0 co s3s2s1s0 co s7.. s0

co s7s6s5s4 s3s2s1s0 (a) (b)

• Goal: Create calculator that adds two 8-bit binary numbers, specified using DIP switches – DIP switch: Dual-inline package switch, move each switch up or down – Solution: Use 8-bit adder DIP switches

1 0

a7..a0 b7..b0 a 8-bit carry-ripple adder ci 0 co s7..s0

CALC

• To prevent spurious values from appearing at output, can place register at output – Actually, the light flickers from spurious values would be too fast for humans to detect -- but the principle of registering outputs to avoid spurious values being read by external devices (which normally aren’t humans) applies here. DIP switches

1 0

a7..a0 b7..b0

8-bit adder ci 0 co s7..s0

e ld 8-bit register clk CALC

• Weight scale with compensation amount of 0-7 – To compensate for inaccurate sensor due to physical wear – Use 8-bit adder 0 weight 7 1 sensor 62 5 3 4 01000010 00000010000

a7..a0 b7..b0

a 8-bit adder ci 0

co s7..s0

1 ld 0100010001000010display register Weight clk Adjuster

• Shifting (e.g., left shifting 0011 yields 0110) useful for: – Manipulating bits – Converting serial data to parallel (remember earlier above-mirror display example with shift registers) – Shift left once is same as multiplying by 2 (0011 (3) becomes 0110 (6)) • Why? Essentially appending a 0 -- Note that multiplying decimal number by 10 accomplished just be appending 0, i.e., by shifting left (55 becomes 550) i3 i2 i1 i0 – Shift right once same as dividing by 2 i3 i2 i1 i0 inR i3 i2 i1 i0 inL

in 201 201 201 201 shL s0 01 01 01 01 s1 in shR sh

a <<1 q3 q2 q1 q0 q3 q2 q1 q0 Shifter with left Symbol Left shifter q3 q2 q1 q0 shift, right shift, Shifter with left Digital Design and no shift Copyright © 2006 shift or no shift 37 Frank Vahid(a) Shifter Example: Approximate Celsius to Fahrenheit Converter • Convert 8-bit Celsius input to 8-bit Fahrenheit output – F = C * 9/5 + 32 – Approximate: F = C*2 + 32 – Use left shift: F = left_shift(C) + 32

C 00001100 (12) 8 * 2

<<1 0 (shift in 0) a 8 00100000 (32) 00011000 (24) 8 8-bit adder 8 00111000 (56) F

• Four registers storing a 0000111 (7) 001000 (8) 001100 (12) 001111 (15) history of temperatures T Ra Rb Rc Rd • Want to output the clk ld average of those ld temperatures ++ • Add, then divide by four + – Same as shift right by 2 shift in 0 0101010 (42) divide by 4 – Use three adders, and right 0 >>2 shift by two 0001010 (10) a Ravg ld

Tavg

Digital Design Copyright © 2006 39 Frank Vahid Barrel Shifter i3 i2 i1 i0 in • A shifter that can shift by any amount 01 01 01 01 – 4-bit barrel left shift can shift left by 0, sh 1, 2, or 3 positions – 8-bit barrel left shifter can shift left by q3 q2 q1 q0 0, 1, 2, 3, 4, 5, 6, or 7 positions Shift by 1 shifter uses 2x1 muxes. 8x1 • (Shifting an 8-bit number by 8 positions mux solution for 8-bit barrel shifter: too is pointless -- you just lose all the bits) many wires. Q: xyz=??? to • Could design using 8x1 muxes and I shift by 5? 8 00000110 lots of wires 1 – Too many wires x sh <<4 in 0 • More elegant design 8 01100000 (by 4) – Chain three shifters: 4, 2, and 1 0 a – Can achieve any shift of 0..7 by y sh <<2 in 0 enabling the correct combination of 8 01100000 those three shifters, i.e., shifts should 1 sum to desired amount z sh <<1 in 0

• N-bit equality comparator: Outputs 1 if two N-bit numbers are equal – 4-bit equality comparator with inputs A and B • a3 must equal b3, a2 = b2, a1 = b1, a0 = b0 – Two bits are equal if both 1, or both 0 – eq = (a3b3 + a3’b3’) * (a2b2 + a2’b2’) * (a1b1 + a1’b1’) * (a0b0 + a0’b0’) • Recall that XNOR outputs 1 if its two input bits are the same – eq = (a3 xnor b3) * (a2 xnor b2) * (a1 xnor b1) * (a0 xnor b0)

a3 b3 a2 b2 a1 b1 a0 b0 0110 = 0111 ? 01100111

a3a2a1a0 b3b2b1b0 a 11 1 0 4-bit equality comparator eq

• N-bit magnitude comparator: A=1011 B=1001 Indicates whether A>B, A=B, or A B whichever’s bit is 1 is greater. If never see unequal bit pair, A=B.

• By-hand example leads to idea for design – Start at left, compare each bit pair, pass results to the right – Each bit pair called a stage – Each stage has 3 inputs indicating results of higher stage, passes results to lower stage a3 b3 a2 b2 a1 b1 a0 b0

ab ab ab ab Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage 3 Stage 2 Stage 1 Stage 0 (a)

a3 b3 a2 b2 a1 b1 a0 b0

ab ab ab ab Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage 3 Stage 2 Stage 1 Stage 0 • Each stage: – out_gt = in_gt + (in_eq * a * b’) • A>B (so far) if already determined in higher stage, or if higher stages equal but in this stage a=1 and b=0 – out_lt = in_lt + (in_eq * a’ * b) • A

• How does it 1011 = 1001 ? 1 = 1 0 0 1 0 1 1 work? a3 b3 a2 b2 a1 b1 a0 b0

ab ab ab ab 0 0 Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt Ag t B 1 1 Ieq=1 causes this Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq Ae q B 0 0 stage to compare Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt Al t B

Stage3 Stage2 Stage1 Stage0 (a) a 11 00= 10 11 a3 b3 a2 b2 a1 b1 a0 b0

ab ab ab ab 0 0 Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt Ag t B 1 1 Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB 0 0 Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt Al t B

11 00 10> 11 1011 = 1001 ? a3 b3 a2 b2 a1 b1 a0 b0 • Final answer appears on the ab ab ab ab right 0 1 Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt Ag t B 1 0 • Takes time for Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB 0 0 answer to Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt Al t B “ripple” from left Stage3 Stage2 Stage1 Stage0 to right (c) • Thus called a 11 00 10 11 “carry-ripple a3 b3 a2 b2 a1 b1 a0 b0 style” after the carry-ripple ab ab ab ab adder 0 1 Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt Ag t B 1 0 – Even though Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB 0 0 there’s no Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt Al t B “carry” involved Stage3 Stage2 Stage1 Stage0 Digital Design (d) Copyright © 2006 46 Frank Vahid Magnitude Comparator Example: Minimum of Two Numbers • Design a combinational component that computes the minimum of two 8-bit numbers – Solution: Use 8-bit magnitude comparator and 8-bit 2x1 mux • If A

11000000 01111111 MIN AB 8 8

88 8 8 a AB A B 1 I1 I0 Min 0 Igt AgtB s C 1 Ieq 8-bit magnitude comparator AeqB 0 8-bit 2x1 mux 8 0 Ilt AltB 0 8 (b) C (a) 01111111

• N-bit up-counter: N-bit register 01 that can increment (add 1) to its cnt 4-bit up-counter a own value on each clock cycle tc C 4 – 0000, 0001, 0010, 0011, ...., 1110, 1111, 0000 10 11101111000000010010001101000101... – Note how count “rolls over” from 1111 to 0000 4-bit up-counter • Terminal (last) count, tc, equals1 during value just before rollover cnt ld • Internal design 4-bit register a – Register, incrementer, and N-input 44 AND gate to detect terminal count 4 +1 4 tc C

• Counter design used incrementer • Incrementer design – Could use carry-ripple adder with B input set to 00...001 • But when adding 00...001 to another number, the leading 0’s obviously don’t need to be considered -- so just two bits being added per column – Use half-adders (adds two bits) rather than full-adders (adds three bits)

a3 a2 a1 a0 1 carries: 0 1 1 ab ab ab ab a3 a2 a1 a0 0 0 1 1 t unused HA HA HA HA n +1 + 1 co s co s co s co s co s3s2 s1 s0 010 0 0 r

• Can build faster incrementer Inputs Outputs a3 a2 a1 a0 c0 s3 s2 s1 s0 using combinational logic 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 design process 0 0 1 0 0 0 0 1 1 – Capture truth table 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 – Derive equation for each output 0 1 0 1 0 0 1 1 0 • c0 = a3a2a1a0 0 1 1 0 0 0 1 1 1 • ... 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 1 • s0 = a0’ 1 0 0 1 0 1 0 1 0 – Results in small and fast circuit 1 0 1 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 – Note: works for small N -- larger 1 1 0 0 0 1 1 0 1 N leads to exponential growth, 1 1 0 1 0 1 1 1 0 like for N-bit adder 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0

Digital Design Copyright © 2006 50 Frank Vahid Counter Example: Mode in Above-Mirror Display • Recall above-mirror display example from Chapter 2 – Assumed component that incremented xy input each time button pressed: 00, 01, 10, 11, 00, 01, 10, 11, 00, ... – Can use 2-bit up-counter • Assumes mode=1 for just one clock cycle during each button press – Recall “Button press synchronizer” example from Chapter 3

mode cnt 2-bit upcounter tc c1c0 clk

Digital Design Copyright © 2006 51 Frank Vahid Counter Example: 1 Hz Pulse Generator Using 256 Hz Oscillator • Suppose have 256 Hz oscillator, but want 1 Hz pulse – 1 Hz is 1 pulse per second -- useful for keeping time 1 – Design using 8-bit up- cnt 8-bit up-counter tc C counter, use tc output as osc pulse (256 Hz) 8 • Counts from 0 to 255 (256 p (unused) counts), so pulses tc every (1 Hz) 256 cycles

• 4-bit down-counter 4-bit down-counter – 1111, 1110, 1101, 1100, …, 0011, 0010, 0001, 0000, cnt 1111, … ld 4-bit register – Terminal count is 0000 • Use NOR gate to detect – Need decrementer (-1) – 44 design like designed 4 –1 incrementer tc C 4

• Can count either up 4-bit up/down counter or down – Includes both dir 104-bit 2 x1 incrementer and 4 decrementer clr clr – Use dir input to cnt select, using 2x1: ld 4-bit register dir=0 means up – Likewise, dir selects 444 4 appropriate terminal 4 –1 +1 count value 44 102x1 tc C

• Illuminate 8 lights from right to left, one at a time, one per 1 cnt 3-bit up-counter second clk tc c2 c1 c0 • Use 3-bit up-counter to (1 Hz) 000 100 010 counter from 0 to 7 unused

• Use 3x8 decoder to 3x8 dcd i2 i1 i0 illuminate appropriate light d7 d6 d5 d4 d3 d2 d1 d0 • Note: Used 3-bit counter a with 3x8 decoder lights – NOT an 8-bit counter – why not?

• Up-counter that can be loaded with external L4 ld value 104-bit 2x1 – Designed using 2x1 mux 4 – ld input selects cnt ld incremented value or 4-bit register external value – Load the internal register 44 when loading external +1 value or when counting 4 tc C

Digital Design Copyright © 2006 56 Frank Vahid Counter with Parallel Load • Useful to create pulses at 1000 specific multiples of clock 4 – Not just at N-bit counter’s natural N wrap-around of 2 ld L • Example: Pulse every 9 clock 1 cnt 4-bit down-counter cycles – Use 4-bit down-counter with tc C clk parallel load 4 – Set parallel load input to 8 (1000) – Use terminal count to reload • When count reaches 0, next cycle loads 8. – Why load 8 and not 9? Because 0 is included in count sequence: • 8, 7, 6, 5, 4, 3, 2, 1, 0 Æ 9 counts Digital Design Copyright © 2006 57 Frank Vahid Counter Example: New Year’s Eve Countdown Display • Chapter 2 example previously used microprocessor to counter from 59 down to 0 in binary • Can use 8-bit (or 7- or 6-bit) down-counter instead, initially loaded with 59 Happy 0 New 8 d0 59 L c0 i0 Year d1 c1 i1 1 c2 i2 d2 2 ld c3 i3 d3 3 reset c4 i4 c5 i5 d58 c6 cnt d59 c7 countdown d60 d61 58 clk 8-bit d62 59 fireworks (1 Hz) down- tc 6x64 counter dcd d63 Digital Design Copyright © 2006 58 Frank Vahid Counter Example: 1 Hz Pulse Generator from 60 Hz Clock • U.S. electricity standard

uses 60 Hz signal clr – Device may convert that to 1 cnt 6-bit up counter 1 Hz signal to count osc tc C seconds (60 Hz) • Use 6-bit up-counter p – Can count from 0 to 63 – Create simple logic to detect 59 (for 60 counts) • Use to clear the counter back to 0 (or to load 0) (1 Hz)

• A type of counter used to measure time – If we know the counter’s clock frequency and the count, we know the time that’s been counted • Example: Compute car’s speed using two sensors – First sensor (a) clears and starts timer – Second sensor (b) stops timer – Assuming clock of 1kHz, timer output represents time to travel between sensors. Knowing the distance, we can compute speed

• Can build multiplier that mimics multiplication by hand – Notice that multiplying multiplicand by 1 is same as ANDing with 1

• Generalized representation of multiplication by hand

• Multiplier design – array of AND gates

a3 a2 a1 a0 b0 pp1 b1

0 0 pp2 b2 + (5-bit) 00 pp3 AB b3 + (6-bit) * P 000 pp4

• Can build subtractor as we built carry-ripple adder – Mimic subtraction by hand – Compute borrows from columns on left • Use full-subtractor component: – wi is borrow by column on right, wo borrow from column on left 1stcolumn 2ndcolumn 3rd column 4th column 0 0 1 10 0 1 0 110 1 01110 01110 0110 0 - 011 1- 011 1- 011 1- 011 1 1 1 1 0 1 1 0 0 1 1

a3 b3 a2 b2 a1 b1 a0 b0 wi

abwi abwi abwi abwi a3 a2 a1 a0 b3 b2 b1 b0

FS FS FS FS 4-bit subtractor wi a wo s wo s wo s wo s wo s3s2s1s0

• Extend earlier DIP switches

calculator example 1 – Switch f indicates 0 whether want to 8 8 8 8 add (f=0) or 00 subtract (f=1) AABBci wi 8-bit adder 8-bit subtractor – Use subtractor and co SSwo 2x1 mux 1 f 8 8 012x1 0 8 e ld 8-bit register clk CALC 8

LEDs Digital Design Copyright © 2006 65 Frank Vahid Subtractor Example: Color Space Converter – RGB to CMYK • Color – Often represented as weights of three colors: red, green, and blue (RGB) • Perhaps 8 bits each, so specific color is 24 bits – White: R=11111111, G=11111111, B=11111111 – Black: R=00000000, G=00000000, B=00000000 – Other colors: values in between, e.g., R=00111111, G=00000000, B=00001111 • Printers use opposite color scheme would be a reddish purple – Because inks absorb light – Good for computer monitors, – Use complementary colors of RGB: which mix red, green, and blue Cyan (absorbs red), reflects green lights to form all colors and blue, Magenta (absorbs green), and Yellow (absorbs blue) Digital Design Copyright © 2006 66 Frank Vahid Subtractor Example: Color Space Converter – RGB to CMYK

RGB • Printers must quickly convert 255 255 255 8 8 8 RGB to CMY 8 8 8 – C=255-R, M=255-G, Y=255-B

o CMY – Use subtractors as shown t ---

R 888 CMY

• Try to save colored inks – Expensive – Imperfect – mixing C, M, Y doesn’t yield good-looking black • Solution: Factor out the black or gray from the color, print that part using black ink – e.g., CMY of (250,200,200)= (200,200,200) + (50,0,0). • (200,200,200) is a dark gray – use black ink

RGBK 88 8 – (200,200,200): K=200 Y – (Letter “B” already used for blue)

o CM

RGB t

• Compute minimum of C, RGB to CMY GB

R M, Y values CM Y – Use MIN component 8 8 8 8 designed earlier, using C MY comparator and mux, to MIN compute K 8 – Output resulting K value, and subtract K value from MIN 8 C, M, and Y values K – Ex: Input of (250,200,200) yields output of (50,0,0,200) --- 888 8 C2 M2 Y2 K Digital Design Copyright © 2006 69 Frank Vahid Representing Negative Numbers: Two’s Complement • Negative numbers common – How represent in binary? • Signed-magnitude – Use leftmost bit for sign bit • So -5 would be: 1101 using four bits 10000101 using eight bits • Better way: Two’s complement – Big advantage: Allows us to perform subtraction using addition – Thus, only need adder component, no need for separate subtractor component!

1 9

2 8 • Before introducing two’s complement, let’s 3 7 consider ten’s complement 4 6 – But, be aware that computers DO NOT USE TEN’S COMPLEMENT. Introduced for intuition only. 5 5 – Complements for each base ten number shown to 6 4 right – Complement is the number that when added 7 3 results in 10 8 2

9 1

• Nice feature of ten’s complement – Instead of subtracting a number, adding its complement results in answer exactly 10 too much – So just drop the 1 – results in subtracting using addition only complements 1 9 10 2 8 46

3 7 7 4 6 01020 5 5 Ð4 +6 3 - 13 6 4 13 7 3 3 8 2 7Ð-4=3 7+6=13 3 9 1 Adding thecomplement results in an answer exactly 10 too much – dropping thetenscolumn gives 010theright answer. Digital Design Copyright © 2006 72 Frank Vahid Two’s Complement is Easy to Compute: Just Invert Bits and Add 1 • Hold on! – Sure, adding the ten’s complement achieves subtraction using addition only – But don’t we have to perform subtraction to have determined the complement in the first place? e.g., we only know that the complement of 4 is 6 by subtracting 10-4=6 in the first place. • True – but in binary, it turns out that the two’s complement can be computed easily – Two’s complement of 011 is 101, because 011 + 101 is 1000 – Could compute complement of 011 as 1000 – 011 = 101 – Easier method: Just invert all the bits, and add 1 – The complement of 011 is 100+1 = 101 -- it works!

Q: What is the two’s complement of 0101? A: 1010+1=1011 a (check: 0101+1011=10000) Q: What is the two’s complement of 0011? A: 1100+1=1101 Digital Design Copyright © 2006 73 Frank Vahid Two’s Complement Subtractor Built with an Adder

• Using two’s complement A B A – B = A + (-B)

= A + (two’s complement of B) N-bit = A + invert_bits(B) + 1

• So build subtractor using A B 1 adder by inverting B’s bits, Adder cin and setting carry in to 1 S

• Adder/subtractor: control input determines whether add or subtract – Can use 2x1 mux – sub input passes either B or inverted B – Alternatively, can use XOR gates – if sub input is 0, B’s bits pass through; if sub input is 1, XORs invert B’s bits

• Previous calculator DIP switches used separate 1 adder and 0 subtractor 88 1 f AB sub 8-bit adder/subtractor • Improve by using 0 S adder/subtractor, 8 e ld and two’s 8-bit register clk complement CALC 8 DIP swtci hes numbers 1 0 LEDs 8 8 8 8 00 AABBci wi 8-bit adder 8-bit subtractor co SSwo

• Sometimes result can’t be represented with given number of bits – Either too large magnitude of positive or negative – e.g., 4-bit two’s complement addition of 0111+0001 (7+1=8). But 4- bit two’s complement can’t represent number >7 • 0111+0001 = 1000 WRONG answer, 1000 in two’s complement is -8, not +8 – Adder/subtractor should indicate when overflow has occurred, so result can be discarded

• Assuming 4-bit two’s complement numbers, can detect overflow by detecting when the two numbers’ sign bits are the same but are different from the result’s sign bit – If the two numbers’ sign bits are different, overflow is impossible • Adding a positive and negative can’t exceed largest magnitude positive or negative • Simple circuit – overflow = a3’b3’s3 + a3b3s3’ – Include “overflow” output bit on adder/subtractor sign bits

0111 1111 1000

+0001+0100+1011

1000 0111 1111 overflow overflow no overflow (a) (b) (c) If the numbers’ sign bits have the same value, which Digital Design differs from the result’s sign bit, overflow has occurred. Copyright © 2006 78 Frank Vahid Detecting Overflow: Method 2

• Even simpler method: Detect difference between carry-in to sign bit and carry-out from sign bit • Yields simpler circuit: overflow = c3 xor c4

1 11 0 00 0 00 0111 1111 1000

+0001+0100+1011

001 000 1 0111 1111 overflow overflow no overflow (a) (b) (c)

If the carry into the sign bit column differs from the carry out of that column, overflow has occurred.

• ALU: Component that can perform any of various arithmetic (add, subtract, increment, etc.) and logic (AND, OR, etc.) operations, based on control inputs • Motivation: – Suppose want multifunction calculator that not only adds and subtracts, but also increments, ANDs, ORs, XORs, etc.

• Can build multifunction calculator using separate components for each DIP switches 1 operation, and muxes 0 – But too many wires, and 88 wasted power computing AB Wasted all those operations when + Ð +1 AND OR XOR NOT power 8 8 8 at any time you only use 8 8 8 8 one of the results 8 A lot of wires 10 01234567 x s2 y 8-bit 8⋅ 1 s1 z s0 8 e Id 8-bit register clk CALC 8

• More efficient design uses ALU – ALU design not just separate components multiplexed (same problem as previous slide!), – Instead, ALU design uses single adder, plus logic in front of adder’s A and B inputs • Logic in front is called an arithmetic-logic extender – Extender modifies the A and B inputs such that desired operation will appear at output of the adder

• xyz=000: Want S=A+B – just pass a to ia, b to ib, and set cin=0 • xyz=001: Want S=A-B – pass a to ia, b’ to ib, and set cin=1 • xyz=010: Want S=A+1 – pass a to ia, set ib=0, and set cin=1 • xyz=011: Want S=A – pass a to ia, set ib=0, and set cin=0 • xyz=1000: Want S=A AND B – set ia=a*b, b=0, and cin=0 • others: likewise • Based on above, create logic for ia(x,y,z,a,b) and ib(x,y,z,a,b) for each abext, and create logic for cin(x,y,z), to complete design of the AL-extender component

DIP swi tches 1 0 88

+ Ð +1 Wasted AND OR XOR NOT power 8 8 8 8 DIP switches 8 8 8 8 10 01234567 A lot of wi res. x y s2 ⋅ s1 8-bit 8 1 z s0 1 1 8 e Id 8-bit regist er 0 0 clk CALC 8 8 LEDs 8 A B A B x • Design using ALU is y x y ALU elegant and efficient z z S –No mass of wires 8 e ld 8-bit register – No big waste of power clk 8 CALC

LEDs

ompu

efficient access to M N-?

d0 load o theab d0 loadregre0g0 T huge mux

ompu

or displ

c bit-wide registers omthe car 32

o theab

al i0 c

i0 r r 4⋅ 16 ⋅ or displ

t 2 4

omthe car's

n – If we have many 8 r

r too much

e t 32-bit c r 8-bit

F d1 loadfanout

o registers but only need e reg1 A x4×1 c 16 1 4 a0 v

o i0 y access one or two at a v

i1 e

y time, a register file is i3-i0i1 8 - a1 d D d2 load d D more efficient reg2 I 328 – Ex: Above-mirror display i2 8 congestion (earlier example), but this d3 load reg3 d15e load reg15 M time having 16 32-bit e load i15i3 s1 s0 registers load 8 32 s3-s0 • Too many wires, and xy big mux is too slow

• Instead, want component that has one data input and one data output, and allows us to specify which internal register to write and which to read

32 32 W_data R_data a 4 4 W_addr R_addr

W_en R_en 16×32 register file

• Can write one cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk register and read 1234 5 6 one register each W_dat a 9 22 X X 177 555 clock cycle W_addr 3 1XX23 – May be same W_en register R_ d at a Z ZZ9 Z 22 9 555

R_addr X XX331

R_en

0: ? 0: ? 0: ? 0: ? 0: ? 0: ? 0: ? 32 32 1: ? 1: ? 1: 22 1: 22 1: 22 1: 22 1: 22 W_data R_data 2: ? 2: ? 2: ? 2: ? 2: ? 2: 177 2: 177 2 2 W_addr R_addr 3: ? 3: 9 3: 9 3: 9 3: 9 3: 9 3: 555

W_en R_en 4x32 register file

• 16 32-bit registers that can be written by car’s 32 C OLD design computer, and a d0 load reg0 huge mux displayed 32 i0 mir 4⋅ 16 To r t e 32

s 32too much r – Use 16x32 register file t CDh or r 32-bit e

a W_dat a R_ d at a

fanout di a

c 16x1 4 b e – Simple, elegant design WA s o

ompu 4 4 p h c v l t a l W_addr R_ ad d r e y a - m r load t o i3-i0 • Register file hides n Fr e W_en R_en d D c complexity internally 16⋅ 32 1 32 register file RA – And because only one congestion register needs to be d15 load reg15 e written and/or read at a i15 load time, internal design is 32 s3-s0 simple

• Need datapath components to store and operate on multibit data – Also known as register-transfer-level (RTL) components • Components introduced – Registers – Shifters – Adders – Comparators – Counters – Multipliers – Subtractors – Arithmetic-Logic Units – Register Files • Next, we’ll combine knowledge of combinational logic design, sequential logic design, and datapath components, to build digital circuits that can perform general and powerful computations