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8-Bit 0 D1 Load Reg1 a 4×1 O • Ch2 Example: Four A0 V Digital Design Chapter 4: Datapath Components Digital Design Copyright © 2006 1 Frank Vahid 4.1 Introduction • Chapters 2 & 3: Introduced increasingly complex digital building blocks – Gates, multiplexors, decoders, basic registers, and controllers • Controllers good for systems with control inputs/outputs – Control input: Single bit (or just a few), representing environment event or state • e.g., 1 bit representing button pressed – Data input: Multiple bits collectively representing single entity si • e.g., 7 bits representing temperature in binary ansis • Need building blocks for data – Datapath components, aka register-transfer-level (RTL) components, e store/transform data z • Put datapath components together to form a datapath • This chapter introduces numerous datapath components, and simple datapaths – Next chapter will combine controllers and datapaths into “processors” Digital Design Copyright © 2006 2 Frank Vahid 4.2 Registers b x • Can store data, very common in datapaths Combinational n1 logic • Basic register of Ch 3: Loaded every cycle n0 s1 s0 – Useful for implementing FSM -- stores encoded state clk State register – For other uses, may want to load only on certain cycles a load I3 I2 I1 I0 4-bit register I3 I2 I1 I0 D D D D si Q Q Q Q ansis reg(4) clk Q3 Q2 Q1 Q0 e Q3 Q2 Q1 Q0 z Basic register loads on every clock cycle How extend to only load on certain cycles? Digital Design Copyright © 2006 3 Frank Vahid Register with Parallel Load • Add 2x1 mux to front of each flip-flop • Register’s load input selects mux input to pass – Either existing flip-flop value, or new value to load I3 I2 I1 I0 10 10 10 10 load 2⋅ 1 I3 I2 I1 I0 load D D D D Q3 Q2 Q1 Q0 Q Q Q Q Q3 Q2 Q1 Q0 (a) (c) I3 I2 I1 I0 I3 I2 I1 I0 0 1 = 10 10 10 10 = 10 10 10 10 d d a a lo lo D D D D D D D D Q Q Q Q Q Q Q Q Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Digital Design (b) Copyright © 2006 4 Frank Vahid Basic Example Using Registers a3 a2 a1 a0 I3 I2 I1 I0 • This example will show how 1 ld clk R0 registers load simultaneously Q3 Q2 Q1 Q0 on clock cycles – Notice that all load inputs set to 1 in this example -- just for demonstration purposes 1 ld I3 I2 I1 I0 1 ld I3 I2 I1 I0 R1 R2 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Digital Design Copyright © 2006 5 Frank Vahid Basic Example Using Registers clk n 12345 (a) e v gi a3..a0 1111 0001 1010 R0 ???? 1111 0001 1010 1010 1010 R1 ???? ???? 1111 0001 1010 1010 R2 ???? ???? 0000 1110 0101 0101 –>1111 1111–>0001 0001–>1010 1010 1010 1010 a3 a2 a1 a0 1 ld I3 I2 I1 I0 ???? R0 1111 R0 0001 R0 1010 R0 1010 R0 1010 R0 clk R0 Q3 Q2 Q1 Q0 (b) ???? ???? ???? ???? 1111 0000 0001 1110 1010 0101 1010 0101 R1 R2 R1 R2 R1 R2 R1 R2 R1 R2 R1 R2 1 ld I3 I2 I1 I0 1 ld I3 I2 I1 I0 R1 R2 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Digital Design Copyright © 2006 6 Frank Vahid Register Example using the Load Input: Weight Sampler • Scale has two displays – Present weight – Saved weight Scale Weight Sampler – Useful to compare 00110010 present item with previous Save item b 1 I3 I2 I1 I0 a 32 pounds load 0011 • Use register to store Present weight clk Q3 Q2 Q1 Q0 weight – Pressing button causes present weight to be 3 pounds stored in register Saved weight • Register contents always displayed as “Saved weight,” even when new present weight appears Digital Design Copyright © 2006 7 Frank Vahid Register Example: Temperature History Display • Recall Chpt 3 example – Timer pulse every hour – Previously used as clock. Better design only connects oscillator to clock inputs -- use registers with load input, connect to timer pulse. a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0 I4 Q4 I4 Q4 I4 Q4 t4 I4 Q4 I4 Q4 I4 Q4 x4 I3 Q3 I3 Q3 I3 Q3 t3 I3 Q3 I3 Q3 I3 Q3 x3 I2 Q2 I2 Q2 I2 Q2 t2 I2 Ra Q2 I2 RbQ2 I2 RcQ2 x2 I1 Q1 I1 Q1 I1 Q1 t1 I1 Q1 I1 Q1 I1 Q1 x1 I0 Q0 I0 Q0 I0 Q0 t0 I0 Q0 I0 Q0 I0 Q0 x0 ld ld ld Clk Ra Rb Rc osc C C TemperatureHistoryStorage a timer new line TemperatureHistoryStorage Digital Design Copyright © 2006 8 Frank Vahid Register Example: Above-Mirror Display 8 Shorthand notation a 0001010 er C t 8 Loaded on clock edge d0 load reg0 T ompu mi T c o theab r al i0 r r 2⋅ 4 or displ t omthe car's r n 8 F e c 1 8-bit 0 d1 load reg1 A 4×1 o • Ch2 example: Four a0 v a 0001010 e i0 y simultaneous values from i1 car’s computer 1 i1 8 a1 d D • To reduce wires: Computer d2 load reg2 I 8 writes only 1 value at a time, i2 loads into one of four 8 registers d3 load e reg3 M – Was: 8+8+8+8 = 32 wires 1 load i3 s1 s0 – Now: 8 +2+1 = 11 wires 8 Digital Design xy Copyright © 2006 9 Frank Vahid Register Example: Computerized Checkerboard • Each register LED lit LED holds values for 1 one column of 0 lights 1 – 1 lights light 0 • Microprocessor loads one 0 register at a time 0 – Occurs fast 1 enough that 0 user sees Q R7 R6 R5 R4 R3 R2 R1 R0 R0 10100010 entire board I load change at once d7 d6 d5 d4 d3 d2 d1 d0 8 ei2i1i03⋅ 8 decoder from from microprocessor decoder D (b) microprocessor Digital Design (a) Copyright © 2006 10 Frank Vahid Register Example: Computerized Checkerboard LED lit LED R7 R6 R5 R4 R3 R2 R1 R0 10100010 10100010 10100010 10100010 01000101 01000101 01000101 01000101 D 10100010 010000101 10100010 010000101 10100010 010000101 10100010 010000101 i2,i1,i0 000 (R0) 001 (R1) 010 (R2) 011 (R3) 100 (R4) 101 (R5) 110 (R6) 111 (R7) e clk Digital Design Copyright © 2006 11 Frank Vahid Shift Register Register contents 1 1 0 1 before shift right • Shift right 0 a Register contents – Move each bit one position right 0 1 1 0 after shift right – Shift in 0 to leftmost bit Q: Do four right shifts on 1001, showing value after each shift a A: 1001 (original) 0100 • Implementation: Connect flip-flop 0010 output to next flip-flop’s input 0001 shr_in a 0000 Digital Design Copyright © 2006 12 Frank Vahid Shift Register • To allow register to either shift or retain, use 2x1 muxes – shr: 0 means retain, 1 shift – shr_in: value to shift in • May be 0, or 1 • Note: Can easily design shift register that shifts left instead shr_in 1 shr 10 10 10 10 = 10 10 10 10 r 2⋅ 1 2⋅ 1 sh D D D D D D D D Q Q Q Q Q Q Q Q Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 (b) (a) shr_in shr Q3 Q2 Q1 Q0 Digital Design Copyright © 2006 (c) 13 Frank Vahid Rotate Register Register contents 1 1 0 1 before shift right • Rotate right: Like shift right, Register contents 1 1 1 0 but leftmost bit comes from after shift right rightmost bit Digital Design Copyright © 2006 14 Frank Vahid Shift Register Example: Above-Mirror Display r s e C s t ' 8 r a e c d0 load e reg0 T ompu h r mi To c l i r t • Earlier example: 8 a i0 r r or 2⋅ 4 h t om t r 8 e n di F e 8-bit a c b w d1 load s p reg1 A 4⋅ 1 o l a0 v a +2+1 = 11wires from e i0 y 1 i1 i1 8 1 a1 d D car’s computer to d2 load reg2 I 8 i2 8 above-mirror display’s d3 load e reg3 M load i3 four registers 8 s1 s0 xy – Better than 32 wires, Note: this line is 1 bit, rather than 8 bits like before but 11 still a lot -- c xy want fewer for shr_in d0 shr reg0 T smaller wire bundles s1 s0 2⋅ 4 i0 • Use shift registers 8 shr_in 4×1 – Wires: 1+2+1=4 d1 shr reg1 A a0 i0 – Computer sends one i1 a1 i1 8 value at a time, one shr_in d D d2 shr reg2 I 8 bit per clock cycle i2 8 shr_in shr e d3 reg3 M Digital Design shift i3 Copyright © 2006 8 15 Frank Vahid Multifunction Registers • Many registers have multiple functions – Load, shift, clear (load all 0s) – And retain present value, of course Functions: • Easily designed using muxes s1 s0 Operation – Just connect each mux input to achieve 0 0 Maintain present value 0 1 Parallel load desired function 1 0 Shift right 1 1 (unused - let's load 0s) shr_in I3 I2 I1 I0 0 0 0 0 s1 3210 3210 3210 3210 s0 4⋅ 1 shr_in I3 I2 I1 I0 s1 D D D D s0 Q3 Q2 Q1 Q0 Q Q Q Q Q3 Q2 Q1 Q0 (b) (a) Digital Design Copyright © 2006 16 Frank Vahid Multifunction Registers s1 s0 Operation 0 0 Maintain present value 0 1 Parallel load 1 0 Shift right 1 1 Shift left I3 I2 I1 I0 shr_in shl_in 3210 3210 3210 3210 shl_in I3 I2 I1 I0 shr_in D D D D s1 s0 Q Q Q Q Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 (a) (b) Digital Design Copyright © 2006 17 Frank Vahid Multifunction Registers with Separate Control Inputs ld shr shl Operation 0 0 0 Maintain present value 0 0 1 Shift left 0 1 0 Shift right 0 1 1 Shift right – shr has priority over shl 1 0 0 Parallel load 1 0 1 Parallel load – ld has priority I3 I2 I1 I0 1 1 0 Parallel load – ld has priority shr_in 1 1 1 Parallel load – ld has priority ld shr_in I3 I2 I1 I0 s1 shl_in combi- shl_in shr national s0 Truth table for combinational circuit circuit shl Q3 Q2 Q1 Q0 Inputs Outputs Note ? ld shr shl s1 s0 Operation Q3 Q2 Q1 Q0 0 0 0 0 0 Maintain value 1 1 Shift left 0 0 1 a 0 1 0 1 0 Shift right 0 1 1 1 0 Shift right 1 0 0 0 1 Parallel load s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl 1 0 1 0 1 Parallel load 1 1 0 0 1 Parallel load s0 = ld’*shr’*shl + ld a 1 1 1 0 1 Parallel load a Digital Design Copyright © 2006 18 Frank Vahid Register Operation Table • Register operations typically shown using compact version of table – X means same operation whether value is 0 or 1 • One X expands to two rows • Two Xs expand to four rows – Put highest priority control input on left to make reduced table simple Inputs Outputs Note ld shr shl s1 s0 Operation ld shr shl Operation 0 0 0 0 0 Maintain value 0 0 0 Maintainvalue 0 0 1 1 1 Shift left 0 0 1 Shift left 0 1 0 1 0 Shift right 0 1 X Shift right 0 1 1 1 0 Shift right 1 X X Parallel load 1 0 0 0 1 Parallel load 1 0 1 0 1 Parallel load 1 1 0 0 1 Parallel load 1 1 1 0 1 Parallel load Digital Design Copyright © 2006 19 Frank Vahid Register Design Process • Can design register with desired operations using
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