Order this document MOTOROLA by AN211A/D SEMICONDUCTOR APPLICATION NOTE AN211A FIELD EFFECT TRANSISTORS IN THEORY AND PRACTICE

INTRODUCTION increase in channel resistance that prevents any further increase in drain current. The drain-source voltage that There are two types of field-effect transistors, the Junction causes this current limiting condition is called the “pinchoff” Field-Effect Transistor (JFET) and the “Metal-Oxide voltage (Vp). A further increase in drain-source voltage Semiconductor” Field-Effect Transistor (MOSFET), or produces only a slight increase in drain current. Insulated-Gate Field-Effect Transistor (IGFET). The prin- The variation in drain current (ID) with drain-source ciples on which these devices operate (current controlled by voltage (VDS) at zero gate-source voltage (VGS) is shown an electric field) are very similar — the primary difference in Figure 2a. In the low-current region, the drain current is being in the methods by which the control element is made. linearly related to VDS. As ID increases, the “channel” begins This difference, however, results in a considerable difference to deplete and the slope of the ID curve decreases. When in device characteristics and necessitates variances in circuit the VDS is equal to Vp, ID “saturates” and stays relatively design, which are discussed in this note. constant until drain-to-gate avalanche, VBR(DSS) is reached. DRAIN DRAIN If a reverse voltage is applied to the gates, channel pinch-off occurs at a lower ID level (Figure 2b) because the depletion GATE GATE region spread caused by the reverse-biased gates adds to that produced by VDS. Thus reducing the maximum current for any value of VDS.

SOURCE SOURCE

È ÈÈ SOURCE DRAIN

N-CHANNEL JFET P-CHANNEL JFET GATE 1 ÈÈ

È N

ÈÇÇÈ ÈÈ JUNCTION FIELD-EFFECT TRANSISTOR (JFET) È P

DRAIN

ÇÇÈ In its simplest form the junction field-effect transistor starts (a) ÈN

with nothing more than a bar of doped silicon that behaves SOURCE

ÇÇ È GATE 1 È P

as a resistor (Figure 1a). By convention, the terminal into (–)

ÇÇ È DEPLETION ZONES È which current is injected is called the source terminal, since, GATE 2

(b)

ÈÇÇÈ as far as the FET is concerned, current originates from this ÇÇÇP SOURCE DRAIN

terminal. The other terminal is called the drain terminal. N

ÈÇÇÈ Current flow between source and drain is related to the ÇÇÇ

P

ÇÇÇÇÇ È drain-source voltage by the resistance of the intervening È material. In Figure 1b, p-type regions have been diffused into (–) GATE 2 GATE 1

the n-type substrate of Figure 1a leaving an n-type channel (c)

ÈÈÇÇÈ between the source and drain. (A complementary p-type ÇÇÇP

SOURCE (+) DRAIN

ÈÈÇÇÈ device is made by reversing all of the material types.) These ÇÇÇ I

p-type regions will be used to control the current flow D +V

ÇÇÇÇÇ È ÈÈ P DS

between the source and the drain and are thus called gate ID

ÇÇÇÇÇ È regions. ÈÈ GATE 2 As with any p-n junction, a depletion region surrounds (d) the p-n junctions when the junctions are reverse biased Figure 1. Development of Junction (Figure 1c). As the reverse voltage is increased, the Field-Effect Transistors depletion regions spread into the channel until they meet, V LOCUS creating an almost infinite resistance between the source and P the drain. If an external voltage is applied between source and drain I VGS = 0 I VGS = 0 (Figure 1d) with zero gate voltage, drain current flow in the D D V = – 1 V channel sets up a reverse bias along the surface of the gate, GS IP parallel to the channel. As the drain-source voltage VGS = – 2 V increases, the depletion regions again spread into the channel because of the voltage drop in the channel which reverse biases the junctions. As V is increased, the VP V(BR)DSS DS V V depletion regions grow until they meet, whereby any further DS DS increase in voltage is counterbalanced by an increase in the (a) (b) depletion region toward the drain. There is an effective Figure 2. Drain Current Characteristics

RF Application Reports 1  Motorola, Inc. 1993 Copyright of Motorola. Used by Permission. AN211A

Due to the difficulty of diffusing impurities into both sides absence of gate voltage is extremely low because the of a semiconductor wafer, a single ended geometry is structure is analogous to two diodes connected back to back. normally used instead of the two-sided structure discussed The metal area of the gate forms a capacitor with the above. Diffusion for this geometry (Figure 3) is from one side insulating layers and the semiconductor channel. The metal only. The substrate is of p-type material onto which an n-type area is the top plate; the substrate material and channel are channel is grown epitaxially. A p-type gate is then diffused the bottom plate. into the n-type epitaxial channel. Contact metallization For the structure of Figure 4, consider a positive gate completes the structure. potential (see Figure 5). Positive charges at the metal side The substrate, which functions as Gate 2 of Figure 1, is of the metal-oxide capacitor induce a corresponding negative of relatively low resistivity material to maximize gain. For the charge at the semiconductor side. As the positive charge same purpose, Gate 1 is of very low resistivity material, at the gate is increased, the negative charge “induced” in allowing the depletion region to spread mostly into the n-type the semiconductor increases until the region beneath the channel. In most cases the gates are internally connected oxide effectively becomes an n-type semiconductor region, together. A tetrode device can be realized by not making and current can flow between drain and source through the this internal connection. “induced” channel. In other words, drain current flow is “enhanced” by the gate potential. Thus drain current flow can DRAIN DRAIN be modulated by the gate voltage; i.e. the channel resistance is directly related to the gate voltage. The n-channel structure TYPE C GATE GATE may be changed to a p-channel device by reversing the SUBSTRATE SUBSTRATE material types. DRAIN SOURCE SOURCE GATE SOURCE DRAIN DRAIN SOURCE

TYPE B GATE GATE SUBSTRATE SUBSTRATE SOURCE SOURCE

P ËËËË N-CHANNEL MOSFET P-CHANNEL MOSFET P

ID ËËËËËËËË

N ËËËË ËËËËËËËË MOS FIELD-EFFECT TRANSISTORS (MOSFET) ËËËË P L

(SUBSTRATE) ËËËËËËËË The metal-oxide-semiconductor (MOSFET) operates with ËËËË CHANNEL

a slightly different control mechanism than the JFET. Figure

ËËËËËËËË ËËËË 4 shows the development. The substrate may be high CHANNEL LENGTH resistivity p-type material, as for the 2N4351. This time two ËËËËËËËË separate low-resistivity n-type regions (source and drain) are Figure 3. Junction FET with Single-Ended Geometry diffused into the substrate as shown in Figure 4b. Next, the SOURCE DRAIN surface of the structure is covered with an insulating oxide layer and a nitride layer. The oxide layer serves as a NN protective coating for the FET surface and to insulate the P P (SUBSTRATE) channel from the gate. However the oxide is subject to (SUBSTRATE) contamination by sodium ions which are found in varying quantities in all environments. Such contamination results (a) (b) in long term instability and changes in device characteristics. SILICON NITRATE SGMETAL D Silicon nitride is impervious to sodium ions and thus is used OXIDE Si3N4 to shield the oxide layer from contamination. Holes are cut SiO2

into the oxide and nitride layers allowing metallic contact to

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ the source and drain. Then, the gate metal area is overlayed

NN NN ÉÉÉÉÉÉÉ on the insulation, covering the entire channel region and, ÉÉÉÉÉÉÉ P P simultaneously, metal contacts to the drain and source are (SUBSTRATE) (SUBSTRATE) made as shown in Figure 4d. The contact to the metal area covering the channel is the gate terminal. Note that there (c) (d) is no physical penetration of the metal through the oxide and nitride into the substrate. Since the drain and source are Figure 4. Development of Enhancement-Mode isolated by the substrate, any drain-to-source current in the N-Channel MOSFET

2 RF Application Reports AN211A

SOURCE GATE (+) DRAIN to the increase of carriers in the channel due to application ALUMINUM Si3N4 of gate voltage. A third type of FET that can operate in both SiO2 the depletion and the enhancement modes has also been + + + + + + + + + described.

ÍÍÍÍÍÍÍÍÍÍÍÍ%%%%%%%%% The basic differences between these modes can most

+ + + + + + + + + easily be understood by examining the transfer characteris-

ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ – – – – – – – – – tics of Figure 9. The depletion-mode device has considerable ÍÍÍÍÍÍÍÍÍÍÍÍ drain-current flow for zero gate voltage. Drain current is N + N + reduced by applying a reverse voltage to the gate terminal. INDUCED The depletion-type FET is not characterized with forward CHANNEL gate voltage. P (SUBSTRATE) The depletion/enhancement mode type device also has considerable drain current with zero gate voltage. This type device is defined in the forward region and may have usable forward characteristics for quite large gate voltages. Notice Figure 5. Channel Enhancement. Application of Positive that for the junction FET, drain current may be enhanced Gate Voltage Causes Redistribution of Minority Carriers by forward gate voltage only until the gate-source p-n in the Substrate and Results in the Formation of a junction becomes forward biased. Conductive Channel Between Source and Drain The third type of FET operates only in the enhancement mode. This FET has extremely low drain current flow for zero An equivalent circuit for the MOSFET is shown in Figure gate-source voltage. Drain current conduction occurs for a 6. Here, C is the distributed gate-to-channel capacitance g(ch) V greater than some threshold value, V . For gate representing the nitride-oxide capacitance. C is the GS GS(th) gs voltages greater than the threshold, the transfer characteris- gate-source capacitance of the metal gate area overlapping tics are similar to the depletion/ enhancement mode FET. the source, while Cgd is the gate-drain capacitance of the metal gate area overlapping the drain. Cd(sub) and Cs(sub) are junction capacitances from drain to substrate and source SOURCE GATE DRAIN to substrate. Yfs is the transadmittance between drain current and gate-source voltage. The modulated channel resistance is rds. RD and RS are the bulk resistances of the drain and source. Cgs Cgd The input resistance of the MOSFET is exceptionally high Cg(ch) because the gate behaves as a capacitor with very low RS RD leakage (rin [ 1014 Ω). The output impedance is a function of rds (which is related to the gate voltage) and the drain rds and source bulk resistances (RD and RS). To turn the MOSFET “on”, the gate-channel capacitance, CS(sub) CD(sub) Y V Cg(ch), and the Miller capacitance, Cgd, must be charged. fs GS P SUBSTRATE In turning “on”, the drain-substrate capacitance, Cd(sub), must be discharged. The resistance of the substrate determines the peak discharge current for this capacitance. Figure 6. Equivalent Circuit of Enhancement- The FET just described is called an enhancement-type Mode MOSFET MOSFET. A depletion-type MOSFET can be made in the following manner: Starting with the basic structure of Figure 4, a moderate resistivity n-channel is diffused between the DIFFUSED CHANNEL source and drain so that drain current can flow when the SOURCE GATE DRAIN gate potential is at zero volts (Figure 7). In this manner, the ALUMINUM MOSFET can be made to exhibit depletion characteristics. Si3N4 For positive gate voltages, the structure enhances in the same manner as the device of Figure 4. With negative gate SiO2

voltage, the enhancement process is reversed and the ÍÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍÍ channel begins to deplete of carriers as seen in Figure 8. ÍÍÍÍÍÍÍÍÍÍÍÍÍ As with the JFET, drain-current flow depletes the channel N area nearest the drain first. N + N + The structure of Figure 7, therefore, is both a depletion-mode and an enhancement-mode device. P (SUBSTRATE) MODES OF OPERATION There are two basic modes of operation of FET’s — depletion and enhancement. Depletion mode, as previously Figure 7. Depletion Mode MOSFET Structure. mentioned, refers to the decrease of carriers in the channel This Type of Device may be Designed to Operate in due to variation in gate voltage. Enhancement mode refers Both the Enhancement and Depletion Modes

RF Application Reports 3 AN211A

SOURCE GATE DRAIN ly different. An understanding of FET terminology and (–) SiO2 characteristics are necessary to evaluate their comparative Si3N4 merits from data-sheet specifications. – – – – – – – – – – – – – Static Characteristics ÍÍÍÍÍÍÍÍÍÍÍÍ+ + + + + + + + + + + + +

±±±±±±±±±±±±± ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ Static characteristics define the operation of an active + + + + + + + + + + + + + device under the influence of applied dc operating conditions. ÍÍÍÍÍÍÍÍÍÍÍÍ+ + + Of primary interest are those specifications that indicate the N + N N + effect of a control signal on the output current. The VGS – ID transfer characteristics curves are illustrated in Figure 9 P (SUBSTRATE) for the three types of FETs. Figure 10 lists the data-sheet specifications normally employed to describe these curves, as well as the test circuits that yield the indicated specifications. Figure 8. Channel Depletion Phenomenon. Of additional interest is the special case of tetrode-con- Application of Negative Gate Voltage Causes nected devices in which the two gates are separately Redistribution of Minority Carriers in Diffused Channel accessible for the application of a control signal. The and Reduces Effective Channel Thickness. This Results pertinent specifications for a junction tetrode are those which in Increased Channel Resistance. define drain-current cutoff when one of the gates is connected to the source and the bias voltage is applied to ELECTRICAL CHARACTERISTICS the second gate. These are usually specified as VG1S(off), Gate 1 — source cutoff voltage (with Gate 2 connected to Because the basic mode of operation for field-effect source), and VG2S(off), Gate 2 — source cutoff voltage (with devices differs greatly from that of conventional junction Gate 1 connected to source). The gate voltage required for transistors, the terminology and specifications are necessari- drain current cutoff with one of the gates connected to the

N-CHANNEL N-CHANNEL JUNCTION FET ID VGS = 1 V/STEP DEPLETION ENHANCEMENT VGS = 0

DEPLETION ONLY – 1 V NOT DEFINED = 1 mA/DIV DS

IN THIS AREA I – 2 V

(–) VGS (+) 0 VDS = 2 V/DIV N-CHANNEL MOS 2N3797 ID VGS = 1 V/STEP DEPLETION ENHANCEMENT VGS = 2 V

DEPLETION AND ENHANCEMENT MODE 1 V = 1 mA/DIV

DS 0 I – 1 V – 2 V

0 VDS = 2 V/DIV (–) VGS (+) N-CHANNEL MOS 2N4351 ID VGS = 1 V/STEP DEPLETION ENHANCEMENT VGS = 4 V

ENHANCEMENT ONLY 3 V = 1 mA/DIV DS I 2 V

0 V = 2 V/DIV (–) VGS VGS(th) (+) DS

Figure 9. Transfer Characteristics and Associated Scope Traces for the Three FET Types

4 RF Application Reports AN211A source is always higher than that for the triode-connected Some reflection will reveal that for junction FETs, the case where both gates are tied together. V(BR)DGO specification really provides the same information Reach-through voltage is another specification uniquely as V(BR)GSS. For this measurement, an increasing voltage applicable to tetrode-connected devices. This defines the is applied between drain and gate. When this applied voltage amount of difference voltage that may be applied to the two becomes high enough, the drain-gate junction will go into gates before the depletion region of one spreads into the avalanche, indicated either by a significant increase in drain junction of the other — causing an increase in gate current current or by an increase in gate current (beyond IDGO). For to some small specified value. Obviously, reach-through is both V(BR)DGO and V(BR)GSS specifications, breakdown an undesirable condition since it causes a decrease in input should normally occur at the same voltage value. resistance as a result of an increased gate current, and large From Figure 2 it is seen that avalanche occurs at a lower amounts of reach-through current can destroy the FET. value of VDS when the gate is reverse biased than for the zero-bias condition. This is caused by the fact that the Gate Leakage Current reverse-bias gate voltage adds to the drain voltage, thereby increasing the effective voltage across the junction. The Of interest to circuit designers is the input resistance of maximum amount of drain-source voltage that may be an active component. For FETs, this characteristic is applied V is, therefore, equal to V minus specified in the form of I — the reverse-bias DS(max) (BR)DGO GSS V , which indicates avalanche with reverse bias gate gate-to-source current with the drain shorted to the source GS voltage applied. (Figure 11). As might be expected, because the leakage For MOSFETs, the breakdown mechanism is somewhat current across a reverse-biased p-n junction (in the case of different. Consider, for example, the enhancement-mode a JFET) and across a capacitor (in the case of a MOSFET) structure of Figure 5. Here, the gate is completely insulated is very small, the input resistance is extremely high. At a from the drain, source, and channel by an oxide-nitride layer. temperature of 25°C, the JFET input resistance is hundreds The breakdown voltage between the gate and any of the of megohms while that of a MOSFET is even greater. For other elements, therefore, is dependent on the thickness and junction devices, however, input resistance may decrease purity of this insulating layer, and represents the voltage that by several orders of magnitude as temperature is raised to will physically puncture the layer. Consequently, the voltage 150°C. Such devices, therefore, have gate-leakage current must be specified separately. specified at two temperatures. Insulated-gate FETs are not The drain-to-source breakdown is a different matter. For drastically affected by temperature, and their input resistance enhancement mode devices, with the gate connected to the remains extremely high even at elevated temperatures. source (the cutoff condition) and the substrate floating, there Gate leakage current may also be specified as I GDO is no effective channel between drain and source and the (leakage between gate and drain with the source open), or applied drain-source voltage appears across two opposed as I (leakage between gate and source with the drain GSO series diodes, represented by the source-to-substrate and open). These usually result in lower values of leakage current substrate-to-drain junctions. Drain current remains at a very and do not represent worst-case conditions. The I GSS low level (picoamperes) as drain voltage is increased until specification, therefore, is usually preferred by the user. the drain voltage reaches a value that causes reverse Voltage Breakdown (avalanche) breakdown of the diodes. This particular condition, represented by V(BR)DSS, is indicated by an A variety of specifications can be used to indicate the increase in ID above the IDSS level, as shown in Figure 12b. maximum voltage that may be applied to various elements For depletion/enhancement mode devices, the V(BR)DSS of a FET. Among those in common use are the following: symbol is sometimes replaced by V(BR)DSX. Note that the principal difference between the two symbols is the V(BR)GSS = Gate-to-source breakdown voltage replacement of the last subscript s with the subscript x. V(BR)DGO = Drain-to-gate breakdown voltage Whereas the s normally indicates that the gate is shorted V(BR)DSX = Drain-to-source breakdown voltage to the source, the x indicates that the gate is biased to cutoff (normally used only for MOSFETs) or beyond. To achieve cutoff in these devices, a depleting In addition, there may be ratings and specifications bias voltage must be applied to the gate, Figure 12b. indicating the maximum voltages that may be applied An important static characteristic for switching FETs is the between the individual gates and the drain and source (for “on” drain-source voltage VDS(on). This characteristic for the tetrode connected devices). Obviously, not all of these MOSFETs is a function of VGS, and resembles the VCE(sat) specifications are found on every data sheet since some of versus IB characteristics of junction transistors. The curve them provide the same information in somewhat different for these characteristics can be used as a design guide to form. By understanding the various breakdown mechanisms, determine the minimum gate voltage necessary to achieve however, the reader should be able to interpret the intent a specified output logic level. of each specification and rating. For example: Dynamic Characteristics In junction FETs, the maximum voltage that may be applied between any two terminals is the lowest voltage that Unlike the static characteristics, the dynamic characteris- will lead to breakdown or avalanche of the gate junction. To tics of field-effect transistors apply equally to all FETs. The measure V(BR)GSS (Figure 12a), an increasingly higher conditions and presentation of the dynamic characteristics, reverse voltage is applied between the gate and the source. however, depend largely upon the intended application. For Junction breakdown is indicated by an increase in gate example, the following table indicates the dynamic current (beyond IGSS) which signals the beginning of characteristics needed to adequately describe a FET for avalanche. various applications.

RF Application Reports 5 AN211A

DRAIN DC GATE* mA

SOURCE VDS DEPLETION MODE JFETs ID TEST CIRCUIT FOR IDSS CHARACTERISTIC DESCRIPTION

I @ V = 0, Zero-gate-voltage drain current. DRAIN DEPLETION MODE IDSS DSS GS DC VP < VDS < V(BR)DSS Represents maximum drain current. GATE* mA/µA

0.1 IDSS V @ I = 0.001 I , Gate voltage necessary to reduce GS(off) D DSS V † VDS V < V < V I to some specified negligible value GS SOURCE ID(off) P DS (BR)DSS D at the recommended VDS i.e. cutoff. TEST CIRCUIT FOR VGS AND VGS(off) – V V 0+ GS(off) GS VGS @ ID = 0.1 IDSS, Gate voltage for a specified value of * GATES INTERNALLY CONNECTED I between I and I at cutoff – GATE VOLTAGE VP < VDS < V(BR)DSS D DSS DS † ADJUST FOR DESIRED ID normally 0.1 IDSS.

DEPLETION/ENHANCEMENT MODE MOSFETs DRAIN ID ENHANCEMENT MODE CHARACTERISTIC DESCRIPTION DC I GATE D(on) An arbitrary current value (usually near mA DEPLETION MODE ID(on) @ VGS > 0, max rated current) that locates a point V < V < V P DS (BR)DSS in the enhancement operation mode. V † IDSS GS SOURCE V Zero-gate-voltage drain current. DS IDSS @ VGS = 0, TEST CIRCUIT FOR ID(on) VP < VDS < V(BR)DSS † ADJUST FOR DESIRED ID, NORMALLY NEAR MAX-RATED I VGS(off) @ ID = 0.001 IDSS Voltage necessary to reduce ID to D V V = 0 GS(off) GS some specified negligible value at TEST CIRCUIT FOR I AND V the recommended V , i.e. cutoff. DSS GS(off) GATE VOLTAGE DS

ENHANCEMENT MODE MOSFETs I TEST CIRCUIT ENHANCEMENT MODE D(on) SAME AS FOR DEPLETION/ ID CHARACTERISTIC DESCRIPTION I ENHANCEMENT D(on) An arbitrary current value (usually near I @ V > 0, D(on) GS max rated current) that locates a point VGS TEST CIRCUIT V < V < V P DS (BR)DSS in the enhancement operation mode. SAME AS FOR ID(on) 0.1 ID(on) Gate-source voltage for a specified V TEST CIRCUIT VGS @ 0.1 ID(on) GS(th) drain current of 0.1 ID(on) . SAME AS FOR VGS(off) FOR JFET EXCEPT IDSS VGS(th) @ ID = 0.001 Gate cutoff or turn-on voltage. REVERSE V BATTERY ID(on) or less GS 0 V V POLARITY GS(th) GS IDSS @ VGS = 0, Leakage drain current. GATE VOLTAGE VP < VDS < V(BR)DSS IDSS TEST CIRCUIT SAME AS FOR JFET

Figure 10. Static Characteristics for the Three FET Types are Defined by the Above Curves, Tables, and Test Circuits

VGS(off)tVGS V(BR)DGO V  DRAIN GS 2 GATE

VGS SOURCE

nA/µA

Figure 11. Test Circuit for Leakage Current

6 RF Application Reports AN211A

It is interesting to note that yfs varies considerably with ID due to nonlinearity in the ID – VGS characteristics. This variation, for a typical n-channel, JFET is illustrated in Figure 14. Obviously, the operating point must be carefully selected to provide the desired yfs and signal swing. V GS For tetrode-connected FETs, three yfs measurements are usually specified on data-sheet tables. One of these, wlth µA the two gates tied together, provides a yfs value for the condition where a signal is applied to both gates Figure 12a. V(BR)GSS Test Circuit simultaneously; the others provide the yfs for the two gates individually. Generally, with the two gates tied together, yfs is higher and more gain may be realized in a given circuit. VDS VDS Because of the increased capacitance, however, gain-band- width product is much lower. µA µA For rf field-effect transistors, an additional value of yfs is sometimes specified at or near the highest frequency of VGS operation. This value should also be measured at the same voltage conditions as those used for ID(on) or IDSS. Because TYPE C TYPE B of the importance of the imaginary component at radio frequencies, the high frequency y specification should be Figure 12b. V(BR)DSS and V(BR)DSX Test Circuit fs (Usually Used for MOSFETs Only). a complex representation, and should be given either in the specifications table or by means of curves showing typical variations, as in Figure 15 for the MPF102 JFET. Audio RF-IF Switching Chopper The real portion of this high-frequency yfs, Re (yfs) or G21, yfs (1 kHz) yfs (1 kHz) is usually considered a significant figure of merit. C C C C iss iss iss iss yos Another FET parameter that offers a direct vacuum Crss Crss Crss Crss tube analogy is yos, the output admittance: yos (1 kHz) GP Cd(sub) Cd(sub) yos = ∆ID/∆VDS NF Re(yis) (HF) rds(on) rds(on) VGS = K Re(yos) (HF) td1, td2 In this case, the analogous tube parameter is rp — i.e., y = 1/r . For depletion mode devices, y is measured with NF t , t os p os r f gate and source grounded (see Figure 16). For enhancement mode units, it is measured at some specified V that y The forward transadmittance is a key dynamic charac- GS fs permits substantial drain-current flow. teristic for field-effect transistors. It serves as a basic design As with y , many expressions are used for y . In addition parameter in audio and rf circuits and is a widely accepted fs os to the obvious parallels such as y , g , and g , it is also figure of merit for devices. 22 os 22 sometimes specified as r , where r = 1/y . Because field-effect transistors have many characteristics d d os similar to those of vacuum tubes, and because many VDD engineers still are more comfortable with tube parameters, the symbol gm used for tube transconductance is often specified instead of yfs. To further confuse things, the “g” school also uses a variety of subscripts. In addition to gm, BYPASS RL some data sheets show gfs while others even show g21. Vout Regardless of the symbol used, y defines the relation fs G D between an input signal voltage and an output signal current: Vin I

∆ ∆ yfs = ID/ VGS AC AC VDS = K VTVM Rg VTVM The unit is the mho — current divided by voltage. Figure S 13 is a typical yfs test circuit for a junction FET. As a characteristic of all field-effect devices, yfs is specified at 1 kHz with a VDS the same as that for which Vout Rg TYPICALLY 1 MΩ Yfsl = ID(on) or IDSS is characterized. Since yfs has both real and Vin RL RL OF SUCH VALUE AS TO CAUSE imaginary components, but is dominated by the real NEGLIGIBLE DC DROP AT IDSS component at low frequency, the 1 kHz characteristic is given as an absolute magnitude and indicated as yfs. Figure 13. Typical yfs Test Circuit

RF Application Reports 7 AN211A

6000 µ Closely related to yos and yfs is the amplification fac- 5000 2N4222, A µ V = 15 V tor, : µ DS T = 25°C A 2N4221, A µ ∆ ∆ f = 1.0 kHz = VDS/ VGS 3000 ID = K

2000 2N4220, A The amplification factor does not appear on the field-effect transistor registration format but can be calculated as yfs/yos. 1000 For most small-signal applications, µ has little circuit significance. It does, however, serve as a general indication 700 of the quality of the field-effect manufacturing process. 500 Ciss The common-source-circuit input capacitance, Ciss,

, FORWARD TRANSFER ADMITTANCE ( mhos) ADMITTANCE TRANSFER , FORWARD 300 takes the place of yis in low-frequency field-effect transistors.

fs 0.1 0.2 0.5 1.0 2.0 5.0 10 y This is because yis is entirely capacitive at low frequencies.  ID, DRAIN CURRENT (mA) Ciss is conveniently measured in the circuit of Figure 17 for the tetrode JFET. As with yfs, two measurements are neces- Figure 14. Forward Transfer Admittance versus Drain sary for tetrode-connected devices. Current for Typical JFETs At very high frequencies, the real component of yis becomes important so that rf field-effect transistors should 5.0 have yis specified as a complex number at the same gfs conditions as other high-frequency parameters. For yfs tetrode-connected rf FETs, reading of both Gate 2 to source 4.0 VDS = 15 Vdc and Gate 1 tied to Gate 2 are necessary. VGS = 0 In switching applications Ciss is of major importance since 3.0 a large voltage swing at the gate must appear across Ciss. Thus, Ciss must be charged by the input voltage before turn-on effectively begins. 2.0 – bfs Crss Reverse transfer admittance (yrs) does not appear on FET data sheets. Instead C , the reverse transfer capaci- 1.0 rss tance, is specified at low frequency. Since yrs for a field-effect transistor remains almost completely capacitive and relative- FORWARD TRANSFER ADMITTANCE (mmhos) ADMITTANCE TRANSFER FORWARD 0 ly constant over the entire usable FET frequency spectrum, 10 20 30 50 100 200 300 500 1000 the low-frequency capacitance is an adequate specification. f, FREQUENCY (MHz) Crss is measured by the circuit of Figure 18. For tetrode FETs, values should be specified for Gate 1 and for both Figure 15. Forward Transfer Admittance versus gates tied together. Frequency Again, for switching applications Crss is a critical characteristic. Similar to the Cob of a junction transistor, Crss VDS Vout must be charged and discharged during the switching VDD interval. For a chopper application, Crss is the feedthrough D RS capacitance for the chopper drive. AC AC GI BYPASS VTVM VTVM Cd(sub) For the MOSFET, the drain-substrate junction ca- S pacitance becomes an important characteristic affecting the switching behavior. Cd(sub) appears in parallel with the load in a switching circuit and must be charged and discharged between the two logic levels during the switching interval. Vout RS OF SUCH VALUE AS TO CAUSE YOS = NEGLIGIBLE DC DROP. VDS RS RS SENSES AC DRAIN CURRENT Noise Figure (NF) Like all other active components, field- effect transistors generate a certain amount of noise. The noise figure for field-effect transistors is normally specified Figure 16. yos Measurement Circuit for Depletion FETs on the data sheet as “spot noise”, referring to the noise at a particular frequency. The noise figure will vary with frequency Voltages and frequencies for measuring yos should be and also with the resistance at the input of the device. Typical exactly the same as those for measuring yfs. Like yfs, it is graphs of such variations are illustrated in Figure 19 for the a complex number and should be specified as a magnitude 2N5458. From graphs of this kind the designer can anticipate at 1 kHz and in complex form at high frequencies. the noise level inherent in his design.

8 RF Application Reports AN211A

VGS may be measured with dc gate bias in the enhancement mode.

V i RFC D AC AM- METER GI BYPASS D S CAPACI- AC TANCE VTVM METER G Y S C or is iss ω

Figure 17. C Measurement Circuit iss v Vds(on) r = ds(on) i D CAPACI- TANCE GI Figure 20. Circuit for Measuring JFET METER Channel Resistance S Rg APPLICATIONS GUARD Device Selection Yrs VGD Cc Crss or ω Obviously, different applications call for special emphasis (a) VGD = – VDS on specific characteristics so that a simple figure of merit Rg TYPICALLY 1 MΩ that compares devices for all potential uses would be hard Cc AC SOURCE TO GUARD SIGNAL. to formulate. Nevertheless, an attempt to pinpoint the characteristics that are most significant for various applications has been made* to permit a rapid, first-order Figure 18. Recommended C Test Circuit rss evaluation of competitive devices. Rg, SOURCE RESISTANCE (MEGOHMS) — — The most important single FET parameter, one that 0.2 0.5 1.0 2 5 10 20 50 100 applies for any amplifier application, is y . This parameter, 12 fs or one of its many variations, is specified on most data VDS = 15 V I = I sheets, yet some evaluation is required to come up with a 10 Rg = 1 MΩ D DSS TA = 25°C reasonable comparison. For example, in the table of electrical characteristics on most JFET data sheets, yfs is 8 specified at IDSS (VGS = 0) where, for JFETs devices, yfs is maximum. This is illustrated in Figure 14, where typical 6 variations of yfs as a function of ID are plotted. For some f = 1 kHz small-signal applications, the IDSS (VGS = 0) point can 4 actually be used as a dc operating point because NF, NOISE FIGURE (dB) NF, small-signal excursions into the forward bias region will not 2 actually cause the gate-source junction to become forward-biased. However, in most practical uses, some bias 0 is necessary to allow for the anticipated signal swing; and 10 100 1 kHz 10 kHz it must be recognized the yfs goes down as the bias is f, FREQUENCY (Hz) increased. It is seen, also, that maximum yfs increases as IDSS increases so that, where maximum yfs is important, a device Figure 19. Typical Variations of FET Noise Figure with with a high IDSS specification is normally desirable. Frequency and Source Resistance On the other hand, where power dissipation is a factor to be considered, the figure of merit yfs/VGS(off) IDSS has rds(on) Channel resistance describes the bulk resistance of been proposed. This term factors in not only IDSS, which the channel in series with the drain and source. From an ap- should be low if power dissipation is to be low, but also plications standpoint, it is important primarily for switching VGS(off), which indicates maximum input voltage swing. and chopper circuits since it affects the switching speed and Since the signal peaks are represented by VGS = VGS(off) determines the output level. To complete the confusion of and VGS = 0, the lower VGS(off), the higher the figure of multiple symbols for FET parameters, channel resistance is merit. And, for amplifier applications requiring a large signal sometimes indicated as rd(on) and also as rDS and rds. In ei- swing, V(BR)GSS/VGS(off) (assuming that VGS(off) is the ther case, however, it is measured, for JFETs, by tying the “pinch-off” voltage) is a satisfactory merit figure because it gates to the source, setting all terminals equal to 0 Vdc, and indicates the ratio of maximum and minimum drain voltages. applying an ac voltage from drain to source (see Figure 20). The magnitude of the ac voltage should be kept low so that * Christiansen, Donald, “Semiconductors: The New Figures of Merit,” there will be no pinchoff in the channel. Insulated-gate FETs EEE, October, 1965.

RF Application Reports 9 AN211A

For high-frequency circuits, the input capacitance (Ciss) With its high input impedance, the field-effect transistor and the Miller-effect capacitance (Crss) become important, will play an important role in input circuitry for instrumentation so yfs/(Ciss + Crss) indicates a relative measure of device and audio applications where low-impedance junction performance. For switching and chopper circuits, a figure of transistors have generally been least successful. merit is not often useful. Here the magnitudes of Ciss, Crrs, Cd(sub) and rds are of primary interest. + 12 V Circuits

The types of circuits that can utilize FETs are practically unlimited. In fact, many circuits designed to utilize TO MIXER TUNING small–signal pentode tubes can utilize FETs with only minor MPF102 D modifications. For example, the circuit in Figure 21 shows a typical rf stage for a broadcast-band auto radio. In this circuit, a MPF102 n-channel JFET has replaced the 12BL6 S G pentode normally employed. The specifications for the two I devices, including the AGC characteristics, are similar enough to perform adequately in the circuit of Figure 21. In an audio application, a field-effect transistor such as the 2N5460 can be combined with a high voltage bipolar AGC transistor to make a simple line-operated phonograph amplifier such as that shown in Figure 22. The ceramic Figure 21. RF Stage of Broadcast Auto Radio pickup is connected through a potentiometer volume control to the field-effect transistor. Collector current of the transistor, MFE4007 D in turn, is set by the potentiometer in the source of the FET. With the proper bipolar output transistor, the circuit can be G driven directly from the rectified line voltage, while the low S VOLUME voltage for the FET can be derived from a voltage divider in the power supply line. Figure 23 shows three basic chopper circuits. The BIAS TONE advantage of the more complex series-shunt circuit (24c) is ADJUST that it balances out the leakage currents of the FETs in order to reduce voltage error and is used to attain high chopping frequencies. From an applications standpoint, the FET circuit is superior to a junction transistor circuit in that there is no – 120 V – 30 V offset voltage with the FET turned on. On the minus side, however, the field-effect-transistor chopper generally has a higher series resistance (rds(on)) than the junction transistor. As newer and better FETs are introduced and as a larger number of designers learn to use them, the range of applications of FETs should broaden considerably. Figure 22. Line Operated Phono Amplifiers

10 RF Application Reports AN211A

MFE2012

eout RS MFE2012 MFE2012 R es L

ec RS ec

(a) SERIES CHOPPER CIRCUIT es ec RL Re RS MFE2012 (c) SERIES-SHUNT CHOPPER ec es RL

Re

(b) SHUNT CHOPPER

Figure 23. FET Chopper Circuits

RF Application Reports 11 AN211A

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