Jfet Amplifier Configurations

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JFET AMPLIFIER CONFIGURATIONS

+15V +15V +15V

RL RL

+ +

+ + + + + + + + V + + V V R OUT V R R V V OUT in G in G S OUT in RS R - S - - - - -

[a] Common Source Amplifier [b] Common Drain [Source Follower] Amplifier [c] Common Gate Amplifier

Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS COMMON SOURCE AMPLIFIER WITH BYPASSED SOURCE RESISTOR

+15V

ID RL

d + g + 2N5459

Ri s Vout + RG RS Vi _ _

g d + V gs gmVgs + _ Ri s + R L Vout Vi _ RS

vout − Rvg Lgsm − Rvg Lgsm Av == = vin + Rvgv Sgsmgs gs []1+ Rgv Sm

− Rg Lm Av = or −= RgA Lmv 1+ Rg Sm 2 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS COMMON DRAIN [SOURCE FOLLOWER] AMPLIFIER

+15V

+ g 2N5459

Ri s R + + G R S V Vi out _ _

g d + V gs gmVgs _ Ri s + +

Vi _ Vout RS

vout Rvg Sgsm Rvg Sgsm Rg Sm Av == = ; Av = vin + Rvgv Sgsmgs gs []1 + Rgv Sm 1+ Rg Sm

3 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

JFET AMPLIFIER CONFIGURATIONS WITH HYBRID-Π EQUIVALENT CIRCUITS COMMON GATE AMPLIFIER

+15V

ID RL

d g + 2N5459 + s

R Vout i + RS Vi _ _

gmVgs + s _ RL V Ri out V + gs RS Vi + _ _ g

4 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY]. v − Rvg Lgsm Rg A out == = Lm ; if R = 0, v R i vin ⎡ Ri ⎤ i − Rgv ++ 1 1 Rg im ++ ⎢ imgs ⎥ R ⎣ RS ⎦ S

then = RgA Lmv

5 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY]. DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE MASSACHUSETTS INSTITUTE OF TECHNOLOGY CAMBRIDGE, MASSACHUSETTS 02139

Low Frequency Hybrid-π Equation Chart

TRANSISTORS

Characteristic Common CE with RE CC [E. Follower] Common Base Emitter Voltage Gain −= RgA R A ≈ 1 β R v Lm A −≈ L v A = Lo [if ro >>RL] v v RE π // Rr ()β ++ 1 RsoE

Current Gain βo βo βo+1 β o β o +1 Input r π // Rr B []rπ ()β o ++ //1 RR BE []rπ ()β o ++ //1 RR BE π Impedance β o +1

Output RL RL RL ⎡()π + // RRr Bs ⎤ Impedance ⎢ ⎥ // RE β +1 [if ro >>RL] [if ro >>RL] ⎣ o ⎦ [if ro >>RL]

Phase Yes Yes No No Reversal?

JFET’S

Characteristic Common Source C Source with Common Drain Common Gate

RS [Source Follower] Voltage Gain v −= RgA Lm − Rg Lm Rg Sm Rg Lm Av = Av = Av = 1+ Rg Sm 1+ Rg Sm Ri [if rds >>RL] 1 Rg im ++ RS

Ri = generator resistance Current Gain I D I D I D Rg Sm Ai = I S I S I S Rg Sm +1 Very large! Very large! Very large! Input R R R G G G RS 1 Impedance = // RS Sm +1 gRg m Output RL RL R 1 RL S Impedance [if rds >> RL] [if rds >> RL] = // RS [if rds >>RL] Sm +1 gRg m Phase Yes Yes No No Reversal?

6 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #1

1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER. [VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]

2. ASSUME RS << RL.

3. PLOT A LOAD LINE ON THE OUTPUT CHARACTERISTICS. KEEP THE ID , VDS = 0 INTERCEPT ON THE GRAPH PAGE; I. E. STAY AWAY FROM NEARLY VERTICAL LOAD LINES.

4. CALCULATE RL FROM THE LOAD LINE INTERCEPTS. USE CLOSEST STD. VALUE.

5. PICK Q-POINT VALUE OF VGS FOR MAXIMUM LINEAR OUTPUT SWING.

2 ⎛ V ⎞ 6. CALCULATE I : ⎜1II −= GS ⎟ ; OR ESTIMATE FROM CHARACTERISTICS. D D DSS ⎜ ⎟ ⎝ V )off(GS ⎠

⎛ VGS ⎞ 7. CALCULATE RS FOR VGS AT ID .⎜ RS = ⎟ . USE CLOSEST STANDARD VALUE. ⎝ ID ⎠

8. COMPARE RS AND RL ; IF RS IS CLOSE TO RL , REPLOT THE LOAD LINE.

9. RECALCULATE RS FOR NEW VGS . REPEAT STEPS 7 AND 8 AS NECESSARY!

CALCULATING JFET SMALL-SIGNAL gm

1. CALCULATE gm FROM ΔID /ΔVGS ON DRAIN CHARACTERISTICS FROM CURVE TRACER [LARGE SIGNAL gm ]

2. OR USE MEDIAN SPECIFICATION SHEET VALUE. [FOR A FAST ESTIMATE.]

− I2 ⎛ V ⎞ − I2 I OR g = DSS ⎜1− GS ⎟ = DSS D WHERE V or I = OPERATING POINT. m ⎜ ⎟ GS D V )off(GS ⎝ V )off(GS ⎠ V )off(GS IDSS

When VGS = VGS(OFF), ID = 0 ; IDSS = ID @ VGS = 0. NOTE THAT THE SMALL-SIGNAL

TRANSCONDUCTANCE DEPENDS ON THE DC BIAS POINT, JUST AS IT DOES FOR THE BIPOLAR TRANSISTOR!

7 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

FET COMMON-SOURCE AMPLIFIER BIASING-GRAPHICAL METHOD #2

1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER. [VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]

2. REFER TO THE COMBINED TRANSFER [TRANSCONDUCTANCE] CHARACTERISTICS AND DRAIN CHARACTERISTICS CURVES [ATTACHED].

V )OFF(GS 3. CHOOSE RS AS FOLLOWS: R S = . DRAW THE LINE REPRESENTING RS IDSS FROM THE ORIGIN OF THE TRANSFER CURVE GRAPH; THE “Q” POINT IS AT THE INTERSECTION OF THE TWO PLOTS. THIS SETS IDQ AT ABOUT 0.4 IDSS.

4. EXTEND A HORIZONTAL LINE FROM THE IDQ VALUE ON THE TRANSFER CHARACTERISTICS’ LEFT-HAND AXIS ALL THE WAY ACROSS THROUGH THE DRAIN CHARACTERISTICS.

5. THE RIGHT-HAND VOLTAGE INTERCEPT FOR THE LOAD LINE [ON THE DRAIN CHARACTERISTICS] IS EQUAL TO THE SUPPLY VOLTAGE VDD. CHOOSE A VALUE FOR VDSQ THAT GIVES A ROUGHLY SYMMETRICAL OUTPUT VOLTAGE SWING AROUND VDSQ.

6. DRAW A VERTICAL LINE FROM VDSQ UPWARDS TO INTERSECT WITH THE LINE DRAWN IN STEP #4. THIS INTERSECTION GIVES THE Q-POINT.

7. DRAW THE LOAD LINE FROM THE SUPPLY VOLTAGE THRU THE Q-POINT UNTIL IT INTERSECTS WITH THE CURRENT AXIS.

8. DIVIDE THE SUPPLY VOLTAGE BY THE CURRENT AXIS VALUE TO GET THE TOTAL VALUE OF RESISTANCE IN THE DRAIN-SOURCE CIRCUIT.

9. SUBTRACT THE VALUE OF RS FOUND IN STEP #3 FROM THE VALUE FOUND IN STEP #8 TO GET THE VALUE OF LOAD [OR DRAIN] RESISTOR. USE CLOSEST STANDARD VALUE FOR BOTH RESISTORS.

10. NOTE THAT THE MORE VERTICAL THE LOAD LINE, THE SMALLER THE VALUE OF RL. LOW RL EQUALS LOW VOLTAGE GAIN [AV = - gmRL]. ACCEPTING A LOWER VOLTAGE VDQ WITH ITS ATTENDANT ASYMMETRICAL VOLTAGE SWING WILL ALLOW A HIGHER VALUE RL. INCREASING SUPPLY VOLTAGE WILL ALSO ALLOW A LARGER VALUE OF RL AND A MORE SYMMETRICAL VOLTAGE SWING. [THE MORE HORIZONTAL THE LOAD LINE, THE HIGHER THE TOTAL DRAIN-SOURCE RESISTANCE.]

8 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].

FET SOURCE-FOLLOWER LOAD LINE/GAIN EXAMPLES & METHOD

1. FIND VGS(OFF) & IDSS FOR YOUR DEVICE; MEASURE USING CURVE TRACER. [VGS(OFF) = GATE-SOURCE VOLTAGE FOR WHICH ID = 0. IDSS = ID WHEN VGS = 0]

2. CHOOSE Q-POINT; i.e. CHOOSE -VGS FROM DRAIN CHARACTERISTICS GRAPH.

2 ⎛ V ⎞ 3. CALCULATE I : ⎜1II −= GS ⎟ ; OR ESTIMATE FROM CHARACTERISTICS. D D DSS ⎜ ⎟ ⎝ V )off(GS ⎠

4. CALCULATE RS; USE CLOSEST STANDARD VALUE.

5. CALCULATE LOAD LINE INTERCEPTS, [MAY HAVE TO USE Δ BECAUSE THE ID-VDS = 0 INTERCEPT MAY BE WAY OFF THE GRAPH PAGE].

− I2 ⎛ V ⎞ − I2 I 6. CALCULATE g g = DSS ⎜1− GS ⎟ = DSS D m: m ⎜ ⎟ V )off(GS ⎝ V )off(GS ⎠ V )off(GS IDSS

gRmS 7. CALCULATE Av: Av = 1+ gRmS 1 8. Ro = // RS g m

9. EXAMPLES [VP = VGS(OFF) = -5.8V; IDSS = 9mA]

Example 1 Example 2 Example 3

1. VGS, ID -4V, 1.2mA -3V, 2.3mA -2V, 4.2mA

2. RS= 3.3 kΩ 1.2 kΩ 470 Ω

3. Δ ID @ Δ VDS 4.55mA 12.5V, 5.32mA 10V, 4.17mA

4. gm= 963 μMHO 1,500 μMHO 2,030 μMHO

9 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY]. 5. Av= .761 .643 .488

6. Ro= 790Ω 428Ω 240Ω

10 9/27/06 Cite as: Ron Roscoe, course materials for 6.101 Introductory Analog Electronics Laboratory, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].