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Section J7: FET Amplifier Design

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Section J7: FET Amplifier Design Section J7: FET Amplifier Design The expressions for amplifier characteristics developed in the previous section will now be used in the design process. Remember that for design, it is fundamentally important to understand what it is that you are designing by defining the operational conditions, any constraints (physical or operational) that may exist, what is known and what is unknown. Only after a complete understanding has been achieved can the design process be implemented effectively – say it with me now, don’t just grab equations! The CS and SR Amplifier The circuit for a SR amplifier using an n-channel JFET is given in Figure 6.40a and is reproduced to the right Note that your text describes this amplifier circuit as a common source configuration. The only difference between the SR and CS is the addition of a bypass capacitor (CS) across RS. As you go through your text, don’t let this confuse you – when your author refers to this configuration as common source, he is implying common source with source resistance. The following discussion on the design procedure of an SR amplifier holds for JFET and MOSFET devices. It is assumed that a device has been selected and that its characteristics are known. Also assumed is that sufficient information as to the supply voltage(s), load resistance, voltage gain, current gain, and/or input resistances are provided and that the gain requirements are within the range of the transistor being used. This is the same thing we did in our study of BJT amplifier design – and just like then, it is our job as designers to determine the remaining circuit components to satisfy specifications. As we did for BJT design, the first step is to define a Q-point. For convenience, the Thevenin equivalent voltage and resistance and the Q- point relationships developed in Section J4 are repeated here (remember that the assumption |λvDS|<<1 in the derivation of these equations): R1 R2 RG = R1 || R2 = R1 + R2 VDD R1 VGG = R1 + R2 2 2 ⎛ V ⎞ ⎛ V ⎞ I = K(V −V )2 (1+ λV ) ≅ K(V −V )2 = KV 2 ⎜1− GSQ ⎟ = I ⎜1− GSQ ⎟ (MOSFET) DQ GSQ T DSQ GSQ T T ⎜ ⎟ DSS ⎜ ⎟ ⎝ VT ⎠ ⎝ VT ⎠ 2 2 ⎛ V ⎞ ⎛ V ⎞ I = I ⎜1− GSQ ⎟ (1+ λV ) ≅ I ⎜1− GSQ ⎟ (JFET) DQ DSS ⎜ ⎟ DSQ DSS ⎜ ⎟ ⎝ VP ⎠ ⎝ VP ⎠ VGG = VGSQ + I DQ RS VDD = I DQ RD +VDSQ + I DQ RS = VDSQ + I DQ (RD + RS ) 2I ⎛ V ⎞ g DSS ⎜1 GSQ ⎟ Note :V V for JFETs m = − ⎜ − ⎟ T = P VT ⎝ VT ⎠ A generic family of characteristic curves for an n-channel device is shown to the right. This figure is based on Figure 6.40 of your text, but all specifics as to identifying numbers have been removed. Note that the Q-point must be in the saturation region of the curves. As illustrated, definition of the Q-point identifies the operational conditions VDSQ, VGSQ and IDQ. Assuming we have been given sufficient information as to VDD, RL, gain(s) and Rin, our task is to define RS, RD, R1 and R2. R1 and R2 are defined once VGG and RG are determined, so we’ll go along with your author and solve for RS and RD first. We will be (somewhat) following your text’s derivations, since it cannot be stressed enough that the resulting equations may have assumptions and/or constraints that must be followed. Writing the dc KVL around the drain source loop in the figure above (assuming IS•ID) and solving for the unknown resistors RS and RD yield one equation in two unknowns: VDD −VDS RS + RD = = K1 , (Equation 6.59) I D where the constant K1 is introduced to simplify future notation. Note that we need another equation to solve for the resistances (two unknowns requires two independent equations). For our second equation, we can use either the voltage gain or current gain expression derived in the previous section: − g m (RD || RL ) − (RD || RL ) − RG RD AV = = Ai = (1+ g m RS ) RS +1/ g m RS +1/ g m RD + RL The trick here is to realize that RS = K1 − RD or RD = K1 − RS and substitute into one of the gain equations (where K1=(VDD-VDS)/ID from Equation 6.59). When this approach is taken, the gain equation has only one unknown and may be solved. To follow your text, if we use the voltage gain equation and substitute for RS, the resulting equation becomes: − (RD || RL ) AV = . (Equation 6.60) (K1 − RD ) +1/ g m Solving this equation for RD results in the quadratic equation 2 RD − (K1 + 1 / gm − RL − RL / Av )RD − (K1 + 1 / gm)RL = 0. There are two possible solutions to the quadratic equation, one negative and one positive. Since RD must be greater than zero, only the positive solution is used. However, it’s not quite that simple and we must get through checkpoint #1… ¾ If the positive solution of the quadratic results in RD > K1 (recall that RS=K1-RD and K1=(VDD-VDS)/ID), a negative value for RS results. If this happens, a new Q-point must be selected (i.e., start all over). ¾ If the positive solution results in a positive RS, we’re good to go and can proceed as follows. With RS and RD known, the remaining unknowns are R1 and R2. Directly analogous to our work with BJT amplifiers, the first thing we do is write the general dc KVL for the gate source loop to solve for VGG: VGG = VGS + I D RS . (Equation 6.62) Once a value for VGG is obtained, we hit checkpoint #2…if VGG has the same polarity as VDD, use either the equation for input resistance or current gain (reproduced below) to solve for RG. − RG RD Rin = RG = R1 || R2 Ai = RS +1/ g m RD + RL Using the expressions for the Thevenin equivalent voltage and resistance, we can now solve for R1 and R2: RG RGVDD R1 = R2 = . (Equation 6.63) 1−VGG /VDD VGG And we’re done! Otherwise, if VGG has the opposite polarity of VDD, it is not possible to directly solve for R1 and R2 (since both R1 and R2 must be positive and greater than RG). In this case, a rule of thumb is to let VGG=0V. This means that R2 → ∞ (reference the equation above), and R1 = RG . However, the value of RS now needs to be modified to ensure that Equation 6.62 is equal to zero, which is direct contradiction to the solution of the quadratic we started with! Oh well, can’t do it right? Come now, you’ve been at this long enough to know that there’s a trick involved! The solution to these conflicting requirements is illustrated in Figure 6.41 of your text and is shown to the right. This is the same n- channel JFET CS amplifier we started with, but now the source resistance is split and part of it is bypassed by the capacitor CD. Using our standard assumption that the capacitor is open to dc and a short for the operational frequency range, we get RS dc = RS1 + RS2 ; RS ac = RS1 . Going back to our dc KVL equation for the gate-source loop and setting VGG equal to zero, we can define RSdc: VGG = 0= VGS + I D RSdc , and (Equation 6.64) −VGS RSdc = . I D Once we have defined RSdc, we must back up and revise other values in the design. The dc KVL equation for the drain-source loop (Equation 6.59) now becomes: VDD −VDS RS dc + RD = = K1 , I D yielding RD = K1 − RSdc ( where K1 is still (VDD-VDS)/ID). To find the ac portion of the source resistance (RSac=RS1), we repeat the step that uses the either the voltage or current gain and solve the resulting equation. To follow the earlier procedure, we use the voltage gain and Equation 6.60 becomes: − (RD || RL ) AV = . (Equation 6.66) RSac +1/ g m Note that, in this case, RSac is the only unknown. Solving for RSac, we get − (RD || RL ) 1 RSac = RS1 = − . (Equation 6.67) AV gm If we’re taking this route, we’ve got yet one more checkpoint to encounter! If RSac is positive and ¾ less than RSdc, we can solve for RS2 (RS2 = RSdc − RSac ) and the design is complete; or ¾ greater than RSdc. If this happens, the amplifier cannot be designed with the gain specified and the Q-point selected. If the gain specification is reasonable, a new Q-point should be chosen and the design process repeated. However, if the gain specified is too high, the amplifier cannot be designed with a single stage and/or with the transistor chosen – which, after all this work, is a total bummer! The CD (SF) Amplifier The two-source n-channel JFET implementation of the CD configuration is reproduced to the right (note that this is a corrected version of Figure 6.39a of your text). As usual, before we start the specifics of this design process, keep in mind that the important part of this discussion is how the theory (device and circuit) is used to develop a sequence of logical steps – not the exact equations that we’re going to come up with! The characteristic relationships developed for the CD amplifier in the previous section are reproduced below. Keep in mind that these expressions were derived using assumptions such as rO very large and |λvDS|<<1. If this condition does not hold, all bets are off and these equations must be revised before the design process is begun.
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