Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages
Outline • Common-drain amplifier • Common-gate amplifier
Reading Assignment: Howe and Sodini; Chapter 8, Sections 8.7-8.9
6.012 Spring 2007 1 1. Common-drain amplifier VDD
signal source
RS
signal vs + load
iSUP RL vOUT VBIAS -
VSS • A voltage buffer takes the input voltage which may have a relatively large Thevenin resistance and replicates the voltage at the output port, which has a low output resistance • Input signal is applied to the gate • Output is taken from the source • To first order, voltage gain ≈ 1 • Input resistance is high • Output resistance is low – Effective voltage buffer stage
How does it work?
•vgate ↑⇒ iD cannot change ⇒ vsource ↑ – Source follower
6.012 Spring 2007 2 Biasing the Common-drain amplifier VDD
signal source
RS VSS signal + load vs iSUP RL vOUT VBIAS -
VSS
• Assume device in saturation; neglect RS and RL; neglect CLM (λ = 0) • Obtain desired output bias voltage
– Typically set VOUT to”halfway” between VSS and VDD.
• Output voltage maximum VDD-VDSsat • Output voltage minimum set by voltage
requirement across ISUP. VBIAS = VGS + VOUT I V = V (V ) + SUP GS Tn SB W µ C 2L n ox
6.012 Spring 2007 3 Small-signal Analysis
Unloaded small-signal equivalent circuit model:
D G +
gmvgs ro S vin +
roc vout - -
+ vgs - + +
vin gmvgs ro//roc vout - -
vin = vgs + vout vout = gmvgs(ro // roc ) Then: g A m 1 vo = 1 ≈ gm + ro // roc
6.012 Spring 2007 4 Input and Output Resistance
Input Impedance : Rin = ∞ Output Impedance:
i + v - t + gs + RS vin gmvgs ro//roc vt - -
vin = 0; vt = -vgs
effectively: it resistance of value 1/gm + gmvt ro//roc vt -
1 1 R = ≈ out 1 g gm + m ro // roc Small! Loaded voltage gain: R R A = A L ≈ L ≈ 1 v vo R + R 1 L out RL + gm
6.012 Spring 2007 5 Effect of Back Bias If MOSFET was not fabricated in an isolated p-well,
then body is tied to wafer substrate (connected to VSS) VDD
signal source
RS VSS signal + load vs iSUP RL vOUT VBIAS -
VSS Two consequences: • Bias is affected
–VT depends on VBS
–VBS = VSS –VOUT ≠ 0
• Small signal figures of merit affected – Signal shows up between B and S
–vbs = -vout
6.012 Spring 2007 6 Small-signal Analysis (with back-bias) See text pp.523-527 for details D G +
gmvgs gmbvbs ro S vin +
roc vout - B -
vbs=-vout
+ vgs - + +
vin gmvgs gmbvout ro//roc vout - -
g g A = m ≈ m < 1 vo 1 g + g gm + gmb + m mb ro // roc
Also: 1 1 R = ≈ out 1 g + g gm + gmb + m mb ro // roc
6.012 Spring 2007 7 Common-Drain Two-Port Model
1 + (gm gmb) + +
+ gm vin + v vout − (gm gmb) in − −
• Open circuit voltage gain ~ 1 • Input resistance ~ CS Amplifier – We want a large input resistance because the controlled generator is voltage controlled • Output resistance << CS Amplifier – We want a low output resistance to deliver most of the output voltage to the load
6.012 Spring 2007 8 Relationship between circuit parameters and device parameters: W g = 2I µ C m D L n ox γ gmb = gm 2 −2φp − VBS
Circuit Parameters
Device* |Avo|Rin Rout Parameters gm ∝ 1 gm + gmb gm + gmb ↓ ISUP ↑ -- W ↑ --↓ ↓ µnCox ↑ -- L ↑ --↑
* VBIAS is adjusted so that none of the other parameters change
Common Drain amplifier is often used as a voltage buffer to drive small output loads (in multistage amplifiers, other stages provide the voltage gain).
6.012 Spring 2007 9 2. Common-Gate Amplifier:
VDD
iSUP iOUT signal load VSS RL signal source
is RS IBIAS
VSS • A current buffer takes the input current which may have a relatively small Norton resistance and replicates the current at the output port, which has a high output resistance • Input signal is applied to the source • Output is taken from the drain • To first order, current gain ≈ 1
–is ≈ -iout.(Current Buffer) • Input resistance is low • Output resistance is high – Effective current buffer stage
6.012 Spring 2007 10 Biasing the Common-Gate Amplifier:
Assume device in saturation; neglect RS and RL; neglect CLM (λ = 0) VDD
ISUP IOUT
VSS
IBIAS ISUP + IOUT + IBIAS = 0
VSS
Select bias such that IOUT=0 ⇒ VOUT = 0. Assume MOSFET in saturation (no channel modulation): W 2 I = µ C ()V − V = I =−I D 2L n ox GS T SUP BIAS
But VT depends on VBS:
VT = VTo + γn( −2φp − VBS −−2φp ) Must solve these two equations iteratively.
6.012 Spring 2007 11 Small-signal equivalent circuit (unloaded) i D out + G
vgs gmvgs gmbvbs ro - S roc B is
vbs=vgs
iout -
it is vgs gmvgs gmbvgs ro +
iout
-1 -1 it is gm gmb ro
iout it =−iout ⇒ Aio = =−1 it Aio is the short circuit current gain. Not surprising, since in a MOSFET: ig = 0
6.012 Spring 2007 12 Input Resistance
+
vgs gmvgs gmbvgs ro - roc RL +
it vt -
vgs=-vt
+
gmvt gmbvt ro
it vt
roc//RL -
Do KCL on input node:
vt − it (roc // RL ) it − gmvt − gmbvt − = 0 ro Then: r // R 1 + oc L v r 1 R = t = o ≈ in i 1 g + g t gm + gmb + m mb ro
6.012 Spring 2007 13 Output Resistance
+
vgs gmvgs gmbvgs ro it - + roc vt - RS
+ ' vgs gmvgs gmbvgs ro it - + vt' - RS
Do KCL on input node: vt ′ + vgs i t′ − gmvgs − gmbvgs − = 0 ro Notice also: vgs = −i t′ Rs Then: ⎛ ⎡ ⎛ 1 ⎞⎤ ⎞ ⎜ ⎟ Rout = roc //⎜ ro⎢1 + Rs⎜ gm + gmb + ⎟⎥ ⎟ ⎝ ⎣ ⎝ ro ⎠⎦ ⎠
Rout ≈ roc //[]ro ()1+ gm Rs ≈ roc //[]()gm ro Rs
6.012 Spring 2007 14 Common-Gate Two-Port Model
iin iout
1 − ⎢⎢ iin roc (ro + gmroRS) gm + gmb
• The output resistance depends on the source resistance – The CG current buffer is not unilateral • Input resistance << CS Amplifier – We want a small input resistance because the controlled generator is current controlled • Output resistance >> CS Amplifier – We want a large output resistance to deliver most of the output current to the load
6.012 Spring 2007 15 Relationship between circuit figures of merit and device parameters: W g = 2I µ C m D L n ox γ gmb = gm 2 −2φp − VBS 1 ro ≈ λnID
Circuit Parameters
Device* |Aio|Rin Rout 1 Parameters r //[r (1+ g R )] -1 gm + gmb oc o m s ↓↓ ISUP ↑ - W ↑ - ↓↑ ↓↑ µnCox ↑ - L ↑ - ↑↑
* VBIAS is adjusted so that none of the other parameters change Common Gate amplifier is often used as a current buffer i.e. transform a current source with medium source resistance to an equal current with high source resistance (in multistage amplifiers, other stages provide the current gain).
6.012 Spring 2007 16 What did we learn today?
Summary of Key Concepts
• Common-source amplifier: good voltage amplifier better transconductance amplifier – Large voltage gain – High input resistance – Medium / high output resistance
• Common-drain amplifier: good voltage buffer – Voltage gain ≈ 1 – High input resistance – Low output resistance • Common-gate amplifier: good current buffer – Current gain ≈ 1 – Low input resistance – High output resistance
6.012 Spring 2007 17