DOCSLIB.ORG

Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages Outline • Common-drain amplifier • Common-gate amplifier Reading Assignment: Howe and Sodini; Chapter 8, Sections 8.7-8.9 6.012 Spring 2007 1 1. Common-drain amplifier VDD signal source RS signal vs + load iSUP RL vOUT VBIAS - VSS • A voltage buffer takes the input voltage which may have a relatively large Thevenin resistance and replicates the voltage at the output port, which has a low output resistance • Input signal is applied to the gate • Output is taken from the source • To first order, voltage gain ≈ 1 • Input resistance is high • Output resistance is low – Effective voltage buffer stage How does it work? •vgate ↑⇒ iD cannot change ⇒ vsource ↑ – Source follower 6.012 Spring 2007 2 Biasing the Common-drain amplifier VDD signal source RS VSS signal + load vs iSUP RL vOUT VBIAS - VSS • Assume device in saturation; neglect RS and RL; neglect CLM (λ = 0) • Obtain desired output bias voltage – Typically set VOUT to”halfway” between VSS and VDD. • Output voltage maximum VDD-VDSsat • Output voltage minimum set by voltage requirement across ISUP. VBIAS = VGS + VOUT I V = V (V ) + SUP GS Tn SB W µ C 2L n ox 6.012 Spring 2007 3 Small-signal Analysis Unloaded small-signal equivalent circuit model: D G + gmvgs ro S vin + roc vout - - + vgs - + + vin gmvgs ro//roc vout - - vin = vgs + vout vout = gmvgs(ro // roc ) Then: g A m 1 vo = 1 ≈ gm + ro // roc 6.012 Spring 2007 4 Input and Output Resistance Input Impedance : Rin = ∞ Output Impedance: i + v - t + gs + RS vin gmvgs ro//roc vt - - vin = 0; vt = -vgs effectively: it resistance of value 1/gm + gmvt ro//roc vt - 1 1 R = ≈ out 1 g gm + m ro // roc Small! Loaded voltage gain: R R A = A L ≈ L ≈ 1 v vo R + R 1 L out RL + gm 6.012 Spring 2007 5 Effect of Back Bias If MOSFET was not fabricated in an isolated p-well, then body is tied to wafer substrate (connected to VSS) VDD signal source RS VSS signal + load vs iSUP RL vOUT VBIAS - VSS Two consequences: • Bias is affected –VT depends on VBS –VBS = VSS –VOUT ≠ 0 • Small signal figures of merit affected – Signal shows up between B and S –vbs = -vout 6.012 Spring 2007 6 Small-signal Analysis (with back-bias) See text pp.523-527 for details D G + gmvgs gmbvbs ro S vin + roc vout - B - vbs=-vout + vgs - + + vin gmvgs gmbvout ro//roc vout - - g g A = m ≈ m < 1 vo 1 g + g gm + gmb + m mb ro // roc Also: 1 1 R = ≈ out 1 g + g gm + gmb + m mb ro // roc 6.012 Spring 2007 7 Common-Drain Two-Port Model 1 + (gm gmb) + + + gm vin + v vout − (gm gmb) in − − • Open circuit voltage gain ~ 1 • Input resistance ~ CS Amplifier – We want a large input resistance because the controlled generator is voltage controlled • Output resistance << CS Amplifier – We want a low output resistance to deliver most of the output voltage to the load 6.012 Spring 2007 8 Relationship between circuit parameters and device parameters: W g = 2I µ C m D L n ox γ gmb = gm 2 −2φp − VBS Circuit Parameters Device* |Avo|Rin Rout Parameters gm ∝ 1 gm + gmb gm + gmb ↓ ISUP ↑ -- W ↑ --↓ ↓ µnCox ↑ -- L ↑ --↑ * VBIAS is adjusted so that none of the other parameters change Common Drain amplifier is often used as a voltage buffer to drive small output loads (in multistage amplifiers, other stages provide the voltage gain). 6.012 Spring 2007 9 2. Common-Gate Amplifier: VDD iSUP iOUT signal load VSS RL signal source is RS IBIAS VSS • A current buffer takes the input current which may have a relatively small Norton resistance and replicates the current at the output port, which has a high output resistance • Input signal is applied to the source • Output is taken from the drain • To first order, current gain ≈ 1 –is ≈ -iout.(Current Buffer) • Input resistance is low • Output resistance is high – Effective current buffer stage 6.012 Spring 2007 10 Biasing the Common-Gate Amplifier: Assume device in saturation; neglect RS and RL; neglect CLM (λ = 0) VDD ISUP IOUT VSS IBIAS ISUP + IOUT + IBIAS = 0 VSS Select bias such that IOUT=0 ⇒ VOUT = 0. Assume MOSFET in saturation (no channel modulation): W 2 I = µ C ()V − V = I =−I D 2L n ox GS T SUP BIAS But VT depends on VBS: VT = VTo + γn( −2φp − VBS −−2φp ) Must solve these two equations iteratively. 6.012 Spring 2007 11 Small-signal equivalent circuit (unloaded) i D out + G vgs gmvgs gmbvbs ro - S roc B is vbs=vgs iout - it is vgs gmvgs gmbvgs ro + iout -1 -1 it is gm gmb ro iout it =−iout ⇒ Aio = =−1 it Aio is the short circuit current gain. Not surprising, since in a MOSFET: ig = 0 6.012 Spring 2007 12 Input Resistance + vgs gmvgs gmbvgs ro - roc RL + it vt - vgs=-vt + gmvt gmbvt ro it vt roc//RL - Do KCL on input node: vt − it (roc // RL ) it − gmvt − gmbvt − = 0 ro Then: r // R 1 + oc L v r 1 R = t = o ≈ in i 1 g + g t gm + gmb + m mb ro 6.012 Spring 2007 13 Output Resistance + vgs gmvgs gmbvgs ro it - + roc vt - RS + ' vgs gmvgs gmbvgs ro it - + vt' - RS Do KCL on input node: vt ′ + vgs i t′ − gmvgs − gmbvgs − = 0 ro Notice also: vgs = −i t′ Rs Then: ⎛ ⎡ ⎛ 1 ⎞⎤ ⎞ ⎜ ⎟ Rout = roc //⎜ ro⎢1 + Rs⎜ gm + gmb + ⎟⎥ ⎟ ⎝ ⎣ ⎝ ro ⎠⎦ ⎠ Rout ≈ roc //[]ro ()1+ gm Rs ≈ roc //[]()gm ro Rs 6.012 Spring 2007 14 Common-Gate Two-Port Model iin iout 1 − ⎢⎢ iin roc (ro + gmroRS) gm + gmb • The output resistance depends on the source resistance – The CG current buffer is not unilateral • Input resistance << CS Amplifier – We want a small input resistance because the controlled generator is current controlled • Output resistance >> CS Amplifier – We want a large output resistance to deliver most of the output current to the load 6.012 Spring 2007 15 Relationship between circuit figures of merit and device parameters: W g = 2I µ C m D L n ox γ gmb = gm 2 −2φp − VBS 1 ro ≈ λnID Circuit Parameters Device* |Aio|Rin Rout 1 Parameters r //[r (1+ g R )] -1 gm + gmb oc o m s ↓↓ ISUP ↑ - W ↑ - ↓↑ ↓↑ µnCox ↑ - L ↑ - ↑↑ * VBIAS is adjusted so that none of the other parameters change Common Gate amplifier is often used as a current buffer i.e. transform a current source with medium source resistance to an equal current with high source resistance (in multistage amplifiers, other stages provide the current gain). 6.012 Spring 2007 16 What did we learn today? Summary of Key Concepts • Common-source amplifier: good voltage amplifier better transconductance amplifier – Large voltage gain – High input resistance – Medium / high output resistance • Common-drain amplifier: good voltage buffer – Voltage gain ≈ 1 – High input resistance – Low output resistance • Common-gate amplifier: good current buffer – Current gain ≈ 1 – Low input resistance – High output resistance 6.012 Spring 2007 17.
Load more

Recommended publications
  • Common Drain - Wikipedia, the Free Encyclopedia 10-5-17 下午7:07
    Common drain - Wikipedia, the free encyclopedia 10-5-17 下午7:07 Common drain From Wikipedia, the free encyclopedia In electronics, a common-drain amplifier, also known as a source follower, is one of three basic single- stage field effect transistor (FET) amplifier topologies, typically used as a voltage buffer. In this circuit the gate terminal of the transistor serves as the input, the source is the output, and the drain is common to both (input and output), hence its name. The analogous bipolar junction transistor circuit is the common- collector amplifier. In addition, this circuit is used to transform impedances. For example, the Thévenin resistance of a combination of a voltage follower driven by a voltage source with high Thévenin resistance is reduced to only the output resistance of the voltage follower, a small resistance. That resistance reduction makes the combination a more ideal voltage source. Conversely, a voltage follower inserted between a small load resistance and a driving stage presents an infinite load to the driving stage, an advantage in coupling a voltage signal to a small load. Characteristics At low frequencies, the source follower pictured at right has the following small signal characteristics.[1] Voltage gain: Current gain: Input impedance: Basic N-channel JFET source Output impedance: (the parallel notation indicates the impedance follower circuit (neglecting of components A and B that are connected in parallel) biasing details). The variable gm that is not listed in Figure 1 is the transconductance of the device (usually given in units of siemens). References http://en.wikipedia.org/wiki/Common_drain Page 1 of 2 Common drain - Wikipedia, the free encyclopedia 10-5-17 下午7:07 1.
    [Show full text]
  • I. Common Base / Common Gate Amplifiers
    I. Common Base / Common Gate Amplifiers - Current Buffer A. Introduction • A current buffer takes the input current which may have a relatively small Norton resistance and replicates it at the output port, which has a high output resistance • Input signal is applied to the emitter, output is taken from the collector • Current gain is about unity • Input resistance is low • Output resistance is high. V+ V+ i SUP ISUP iOUT IOUT RL R is S IBIAS IBIAS V− V− (a) (b) B. Biasing = /α ≈ • IBIAS ISUP ISUP EECS 6.012 Spring 1998 Lecture 19 II. Small Signal Two Port Parameters A. Common Base Current Gain Ai • Small-signal circuit; apply test current and measure the short circuit output current ib iout + = β v r gmv oib r − o ve roc it • Analysis -- see Chapter 8, pp. 507-509. • Result: –β ---------------o ≅ Ai = β – 1 1 + o • Intuition: iout = ic = (- ie- ib ) = -it - ib and ib is small EECS 6.012 Spring 1998 Lecture 19 B. Common Base Input Resistance Ri • Apply test current, with load resistor RL present at the output + v r gmv r − o roc RL + vt i − t • See pages 509-510 and note that the transconductance generator dominates which yields 1 Ri = ------ gm µ • A typical transconductance is around 4 mS, with IC = 100 A • Typical input resistance is 250 Ω -- very small, as desired for a current amplifier • Ri can be designed arbitrarily small, at the price of current (power dissipation) EECS 6.012 Spring 1998 Lecture 19 C. Common-Base Output Resistance Ro • Apply test current with source resistance of input current source in place • Note roc as is in parallel with rest of circuit g v m ro + vt it r − oc − v r RS + • Analysis is on pp.
    [Show full text]
  • ECE 255, MOSFET Basic Configurations
    ECE 255, MOSFET Basic Configurations 8 March 2018 In this lecture, we will go back to Section 7.3, and the basic configurations of MOSFET amplifiers will be studied similar to that of BJT. Previously, it has been shown that with the transistor DC biased at the appropriate point (Q point or operating point), linear relations can be derived between the small voltage signal and current signal. We will continue this analysis with MOSFETs, starting with the common-source amplifier. 1 Common-Source (CS) Amplifier The common-source (CS) amplifier for MOSFET is the analogue of the common- emitter amplifier for BJT. Its popularity arises from its high gain, and that by cascading a number of them, larger amplification of the signal can be achieved. 1.1 Chararacteristic Parameters of the CS Amplifier Figure 1(a) shows the small-signal model for the common-source amplifier. Here, RD is considered part of the amplifier and is the resistance that one measures between the drain and the ground. The small-signal model can be replaced by its hybrid-π model as shown in Figure 1(b). Then the current induced in the output port is i = −gmvgs as indicated by the current source. Thus vo = −gmvgsRD (1.1) By inspection, one sees that Rin = 1; vi = vsig; vgs = vi (1.2) Thus the open-circuit voltage gain is vo Avo = = −gmRD (1.3) vi Printed on March 14, 2018 at 10 : 48: W.C. Chew and S.K. Gupta. 1 One can replace a linear circuit driven by a source by its Th´evenin equivalence.
    [Show full text]
  • JFE150 Ultra-Low Noise, Low Gate Current, Audio, N-Channel JFET Datasheet
    JFE150 SLPS732 – JUNE 2021 JFE150 Ultra-Low Noise, Low Gate Current, Audio, N-Channel JFET 1 Features and yields excellent noise performance for currents from 50 μA to 20 mA. When biased at 5 mA, the • Ultra-low noise: device yields 0.8 nV/√Hz of input-referred noise, – Voltage noise: giving ultra-low noise performance with extremely high input impedance (> 1 TΩ). The JFE150 also • 0.8 nV/√Hz at 1 kHz, IDS = 5 mA features integrated diodes connected to separate • 0.9 nV/√Hz at 1 kHz, IDS = 2 mA – Current noise: 1.8 fA/√Hz at 1 kHz clamp nodes to provide protection without the addition • Low gate current: 10 pA (max) of high leakage, nonlinear external diodes. • Low input capacitance: 24 pF at VDS = 5 V The JFE150 can withstand a high drain-to-source • High gate-to-drain and gate-to-source breakdown voltage of 40-V, as well as gate-to-source and gate- voltage: –40 V to-drain voltages down to –40 V. The temperature • High transconductance: 68 mS range is specified from –40°C to +125°C. The device • Packages: Small SC70 and SOT-23 (Preview) is offered in 5-pin SOT-23 and SC-70 packages. 2 Applications Device Information • Microphone inputs PART NUMBER PACKAGE(1) BODY SIZE (NOM) • Hydrophones and marine equipment SOT-23 (5) - Preview 2.90 mm × 1.60 mm JFE150 • DJ controllers, mixers, and other DJ equipment SC-70 (5) 2.00 mm × 1.25 mm • Professional audio mixer or control surface • Guitar amplifier and other music instrument (1) For all available packages, see the package option addendum at the end of the data sheet.
    [Show full text]
  • Lecture 19 Common-Gate Stage
    4/7/2008 Lecture 19 OUTLINE • Common‐gate stage • Source follower • Reading: Chap. 7.3‐7.4 EE105 Spring 2008 Lecture 19, Slide 1Prof. Wu, UC Berkeley Common‐Gate Stage AvmD= gR • Common‐gate stage is similar to common‐base stage: a rise in input causes a rise in output. So the gain is positive. EE105 Spring 2008 Lecture 19, Slide 2Prof. Wu, UC Berkeley EE105 Fall 2007 1 4/7/2008 Signal Levels in CG Stage • In order to maintain M1 in saturation, the signal swing at Vout cannot fall below Vb‐VTH EE105 Spring 2008 Lecture 19, Slide 3Prof. Wu, UC Berkeley I/O Impedances of CG Stage 1 R = in λ =0 RRout= D gm • The input and output impedances of CG stage are similar to those of CB stage. EE105 Spring 2008 Lecture 19, Slide 4Prof. Wu, UC Berkeley EE105 Fall 2007 2 4/7/2008 CG Stage with Source Resistance 1 g vv= m Xin1 + RS gm 1 vv g AgR==out x m vmD1 vvxin + RS gm R gR ==D mD 1 1+ gRmS + RS gm • When a source resistance is present, the voltage gain is equal to that of a CS stage with degeneration, only positive. EE105 Spring 2008 Lecture 19, Slide 5Prof. Wu, UC Berkeley Generalized CG Behavior Rgout= (1++g mrR O) S r O • When a gate resistance is present it does not affect the gain and I/O impedances since there is no potential drop across it (at low frequencies). • The output impedance of a CG stage with source resistance is identical to that of CS stage with degeneration.
    [Show full text]
  • Fundamentals of MOSFET and IGBT Gate Driver Circuits
    Application Report SLUA618A–March 2017–Revised October 2018 Fundamentals of MOSFET and IGBT Gate Driver Circuits Laszlo Balogh ABSTRACT The main purpose of this application report is to demonstrate a systematic approach to design high performance gate drive circuits for high speed switching applications. It is an informative collection of topics offering a “one-stop-shopping” to solve the most common design challenges. Therefore, it should be of interest to power electronics engineers at all levels of experience. The most popular circuit solutions and their performance are analyzed, including the effect of parasitic components, transient and extreme operating conditions. The discussion builds from simple to more complex problems starting with an overview of MOSFET technology and switching operation. Design procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated solutions are described in great details. A special section deals with the gate drive requirements of the MOSFETs in synchronous rectifier applications. For more information, see the Overview for MOSFET and IGBT Gate Drivers product page. Several, step-by-step numerical design examples complement the application report. This document is also available in Chinese: MOSFET 和 IGBT 栅极驱动器电路的基本原理 Contents 1 Introduction ................................................................................................................... 2 2 MOSFET Technology ......................................................................................................
    [Show full text]
  • Tabulation of Published Data on Electron Devices of the U.S.S.R. Through December 1976
    NAT'L INST. OF STAND ms & TECH R.I.C. Pubii - cations A111D4 4 Tfi 3 4 4 NBSIR 78-1564 Tabulation of Published Data on Electron Devices of the U.S.S.R. Through December 1976 Charles P. Marsden Electron Devices Division Center for Electronics and Electrical Engineering National Bureau of Standards Washington, DC 20234 December 1978 Final QC— U.S. DEPARTMENT OF COMMERCE 100 NATIONAL BUREAU OF STANDARDS U56 73-1564 Buraev of Standard! NBSIR 78-1564 1 4 ^79 fyr *'• 1 f TABULATION OF PUBLISHED DATA ON ELECTRON DEVICES OF THE U.S.S.R. THROUGH DECEMBER 1976 Charles P. Marsden Electron Devices Division Center for Electronics and Electrical Engineering National Bureau of Standards Washington, DC 20234 December 1978 Final U.S. DEPARTMENT OF COMMERCE, Juanita M. Kreps, Secretary / Dr. Sidney Harman, Under Secretary Jordan J. Baruch, Assistant Secretary for Science and Technology NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Director - 1 TABLE OF CONTENTS Page Preface i v 1. Introduction 2. Description of the Tabulation ^ 1 3. Organization of the Tabulation ’ [[ ] in ’ 4. Terminology Used the Tabulation 3 5. Groups: I. Numerical 7 II. Receiving Tubes 42 III . Power Tubes 49 IV. Rectifier Tubes 53 IV-A. Mechanotrons , Two-Anode Diode 54 V. Voltage Regulator Tubes 55 VI. Current Regulator Tubes 55 VII. Thyratrons 56 VIII. Cathode Ray Tubes 58 VIII-A. Vidicons 61 IX. Microwave Tubes 62 X. Transistors 64 X-A-l . Integrated Circuits 75 X-A-2. Integrated Circuits (Computer) 80 X-A-3. Integrated Circuits (Driver) 39 X-A-4. Integrated Circuits (Linear) 89 X- B.
    [Show full text]
  • Experiment #6- Part-1 the FET Common Source Amplifier
    University of Anbar Lab. Name: Electronic I Experiment no.: 7 College of Engineering Lab. Supervisor: Munther N. Thiyab Dept. of Electrical Engineering Experiment #6- Part-1 The FET Common Source Amplifier Object The purpose of this experiment is to test the performance of the common source amplifier using the self-bias circuit. Required Parts and Equipment's 1. Electronic Test Board. (M110) 2. Dual Polarity Variable DC Power Supply 3. Digital Multimeters. 4. Dual-Channel Oscilloscope. 5. Function Generator. 6. N-Channel JFET 2N3823 7. Resistors, R5=100KΩ, R6=10KΩ, R8=1KΩ, R7=2.2KΩ Theory The common source amplifier configuration is widely used amongst other JFET configurations and can provide both high voltages gain and large input impedance. In this configuration, the input signal is applied to the gate and the output signal is taken from the drain, while the source terminal being the reference or common. In order to work as an amplifier, the JFET should be properly biased by setting the gate-source voltage which results in the required drain current. The N-channel JFET requires that the gate-source voltage always be less negative than the pinch-off voltage, but less than zero. Since virtually no gate current flows due to the JFET’s high input impedance, the gate voltage is essentially at ground level. Consequently, using only a drain-supply voltage, the required negative quiescent gate-source voltage is developed by the voltage drop across the source resistor of the self-bias circuit shown in Fig.1. This circuit is one of the simplest and practical bias circuits for JFET amplifiers in which a single power supply is used.
    [Show full text]
  • Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER
    Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline 1. Introduction 2. CMOS multi-stage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier stages Reading Assignment: Howe and Sodini, Chapter 9, Sections 9-1-9.3 6.012 Spring 2007 Lecture 24 1 1. Introduction Most often, single stage amplifier does not accomplish design goals: • Need more gain than could be provided by a single stage • Need to adapt to specified RS and RL to maximize efficiency ⇒ Multistage amplifier VBIAS Issues: • What amplifying stages should be used and in what order? • What devices should be used, BJT or MOSFET? • How is biasing to be done? 6.012 Spring 2007 Lecture 24 2 Summary of single stage amplifier characteristics Key Stage A , A R R vo io in out Function Common Transcon- ∞ ro // roc ductance Source Avo =−gm(ro //roc) amplifier Common gm 1 Voltage Avo ≈ ∞ Drain gm + gmb gm + gmb Buffer Current Common A ≈ −1 1 r //[r (1+ g R )] io oc o m S buffer Gate gm + gmb Common Transcon- Avo=−gm(ro//roc) r Emitter π ro // roc ductance amplifier Common 1 RS Voltage Avo ≈1 rπ + βo (ro // roc // RL ) + Collector gm βo buffer Common Current Aio ≈ −1 1 r //[r (1+ g ()r // R )] oc o m π S buffer Base gm Differences between BJT’s and MOSFETs BJT MOSFET βo rπ = gmb ∝ gm gm IC W gm = > gm = 2 µCox ID Vth L VA 1 ro = > ro = IC λI D 6.012 Spring 2007 Lecture 24 3 2. CMOS Multistage Voltage Amplifier Goals: • High voltage gain, Avo • High input resistance, Rin • Low output resistance, Rout Good starting point: Common-Source stage: •Rin=∞ •Avo=-gm(ro//roc), probably insufficient •Rout= (ro//roc), too high 6.012 Spring 2007 Lecture 24 4 CMOS Multistage Voltage Amplifier (contd.) Add second CS stage to get more gain: •Rin=∞ •Avo=gm1(ro1//roc1) gm2(ro2//roc2) •Rout= (ro2//roc2), still too high Add CD stage at output (to reduce Rout): •Rin=∞ gm3 • Avo = gm1()ro1 || roc1 gm2()ro2 || roc2 1 gm3 + gmb3 • Rout = gm3 + gmb3 6.012 Spring 2007 Lecture 24 5 3.
    [Show full text]
  • Lecture 33 Multistage Amplifiers (Cont.)
    Lecture 33 Multistage Amplifiers (Cont.) DC Coupling: General Trends * Goal: want both input and output to be “centered” at halfway between the positive and negative supplies (or ground, for a single supply) -- in order to have maximum possible swing at the input and at the output. Summary of DC shifts through the single stages: BJT Amp. npn version Type CE positive CB positive CC negative* MOS Amp. n-channel p-channel Type version version CS positive negative CG positive negative CD negative* positive* The DC voltage shifts for CC/CD stages are set by the VBE = 0.7 V drop or by the VGS of the transistor and can be specified by the designer. EE 105 Fall 2001 Lecture 33 DC Coupling Example * Common drain - common collector cascade (infinite input resistance, fairly low output resistance, unity voltage gain ... reasonable voltage buffer) For CC stage, the optimum output voltage of 2.5 V (centered between + 5 V and ground for maximum swing) --> VIN2 = DC input of CC amp = 2.5 + 0.7 V = 3.2 V The DC of the n-channel CD amplifier is then: VIN = DC input of CD amp = VIN2 + VGS1 = 3.2 V + 1.5 V = 4.7 V where we have assumed that VGS1 = 1.5 V as a typical gate-source voltage (actual number comes from ISUP1and (W/L)). * too close to the supply voltage -- input DC level should be centered at or near 2.5 V. EE 105 Fall 2001 Lecture 33 DC Biasing Example (Cont.) * Solution: use p-channel CD amplifier since it shifts the DC level in the positive direction from input to output Selection of large (W/L) for the p-channel --> input DC level can be adjusted closer to 2.5 V.
    [Show full text]
  • Common Gate Amplifier
    © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company COMMON GATE AMPLIFIER • ACTIVATE solidThinking © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company Common Gate Amplifier A common-gate amplifier is one of three basic single-stage field-effect transistor (FET) amplifier topologies, typically used as a current buffer or voltage amplifier. In the circuit the source terminal of the transistor serves as the input, the drain is the output and the gate is connected to ground, or common, hence its name. The analogous bipolar junction transistor circuit is the common-base amplifier. Input signal is applied to the source, output is taken from the drain. current gain is about unity, input resistance is low, output resistance is high a CG stage is a current buffer. It takes a current at the input that may have a relatively small Norton equivalent resistance and replicates it at the output port, which is a good current source due to the high output resistance. • ACTIVATE solidThinking © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company Circuit Topology • ACTIVATE solidThinking © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company Waveforms Input Voltage Output Voltage • ACTIVATE solidThinking © 2017 solidThinking, Inc. Proprietary and Confidential. All rights reserved. An Altair Company The common-source and common-drain configurations have extremely high input resistances because the gate is the input terminal. In contrast, the common-gate configuration where the source is the input terminal has a low input resistance. Common gate FET configuration provides a low input impedance while offering a high output impedance.
    [Show full text]
  • The Bipolar Junction Transistor (BJT)
    The Bipolar Junction Transistor (BJT) Introduction he transistor, derived from transfer resistor, is a three terminal device whose resistance between two terminals is controlled by the third. The term bipolar reflects the fact that T there are two types of carriers, holes and electrons which form the currents in the transistor. If only one carrier is employed (electron or hole), it is considered a unipolar device like field effect transistor (FET). The transistor is constructed with three doped semiconductor regions separated by two pn junctions. The three regions are called Emitter (E), Base (B), and Collector (C). Physical representations of the two types of BJTs are shown in Figure (1–1). One type consists of two n -regions separated by a p-region (npn), and the other type consists of two p-regions separated by an n- region (pnp). Figure (1-1) Transistor Basic Structure The outer layers have widths much greater than the sandwiched p– or n–type layer. The doping of the sandwiched layer is also considerably less than that of the outer layers (typically, 10:1 or less). This lower doping level decreases the conductivity of the base (increases the resistance) due to the limited number of “free” carriers. Figure (1-2) shows the schematic symbols for the npn and pnp transistors 1 College of Electronics Engineering - Communication Engineering Dept. Figure (1-2) standard transistor symbol Transistor operation Objective: understanding the basic operation of the transistor and its naming In order for the transistor to operate properly as an amplifier, the two pn junctions must be correctly biased with external voltages.
    [Show full text]