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Lecture20-(140624) Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-1 LECTURE 20 – LOW INPUT RESISTANCE AMPLIFIERS – THE COMMON GATE, CASCODE AND CURRENT AMPLIFIERS LECTURE ORGANIZATION Outline • Voltage driven common gate amplifiers • Voltage driven cascode amplifier • Non-voltage driven cascode amplifier – the Miller effect • Further considerations of cascode amplifiers • Current amplifiers • Summary CMOS Analog Circuit Design, 3rd Edition Reference Pages 218-236 CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-2 VOLTAGE-DRIVEN COMMON GATE AMPLIFIER Common Gate Amplifier VDD VDD Circuit: VPBias1 RL M3 vOUT vOUT VNBias2 VNBias2 M2 V I NBias1 vIN Bias vIN M1 060609-01 Large Signal Characteristics: vOUT V (max) ≈ V – V (sat) VDD OUT DD DS3 VON3 VOUT(min) ≈ VDS1(sat) + VDS2(sat) Note VDS1(sat) = VON1 V ON2 VON1+VON2 VT2 vIN VNBias2 VON1 060609-02 CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-3 Small Signal Performance of the Common Gate Amplifier Small signal model: rds2 rds2 Rin R Rin R out i1 out - + g v g v v rds1 v m2 gs2 v v rds1 v m2 s2 v in gs2 r out in s2 r out + ds3 - ds3 060609-03 rds2 gm2rds2rds3 vout gm2rds2rds3 vout = gm2vs2 rds3 = vin Av = = + rds2+rds3 rds2+rds3 vin rds2+rds3 Rin = Rin’||rds1, Rin’ is found as follows vs2 = (i1 - gm2vs2)rds2 + i1rds3 = i1(rds2 + rds3) - gm2 rds2vs2 vs2 rds2 + rds3 rds2 + rds3 Rin' = = Rin = rds1|| i1 1 + gm2rds2 1 + gm2rds2 Rout ≈ rds2||rds3 CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-4 Influence of the Load on the Input Resistance of a Common Gate Amplifier Consider a common gate amplifier with a general load: V DD V V VDD DD DD VPBias1 M4 Load VPBias1 M3 VPBias2 M3 vOUT vOUT vOUT vOUT VNBias2 VNBias2 M2 VNBias2 M2 VNBias2 M2 M2 Rin1 Rin2 Rin3 VNBias1 VNBias1 VNBias1 VNBias1 vIN M1 vIN M1 vIN M1 vIN M1 070420-01 From the previous page, the input resistance to the common gate configuration is, rds2 + RLoad Rin = 1 + gm2rds2 For the various loads shown, Rin becomes: rds2 1 rds2+rds3 2 rds2+rds4gm3rds3 Rin1 = ≈ Rin2 = ≈ Rin3 = ≈ rds!!! 1+gm2rds2 gm2 1+ gm2rds2 gm2 1+ gm2rds2 The input resistance of the common gate configuration depends on the load at the drain. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-5 VOLTAGE-DRIVEN CASCODE AMPLIFIER Cascode† Amplifier VDD VPBias1 M3 vOUT VNBias2 M2 M1 vIN 060609-05 Advantages of the cascode amplifier: • Increases the output resistance and gain (if M3 is cascoded also) • Eliminates the Miller effect when the input source resistance is large † “Cascode” = “Cascaded triode” see H. Wallman, A.B. Macnee, and C.P. Gadsden, “A Low-Noise Amplifier, Proc. IRE, vol. 36, pp. 700-708, June 1948. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-6 Large-Signal Characteristics of the Cascode Amplifier v =5.0V vIN=4.5V IN 5V 0.5 vIN=4.0V M3 W3 2mm vIN=3.5V = L3 1mm 0.4 vIN=3.0V 2.3V ID ) v =2.5V 0.3 IN M2 + A W2 2mm m K G F ( = L2 1mm D JIH E I v =2.0V 0.2 IN 3.4V v M3 M1 OUT 0.1 D W1 = 2mm vIN=1.5V + L 1mm C v 1 A,B IN - - 0.0 vIN=1.0V 0 1 2 3 4 5 vOUT 5 ABC D 4 E M3 active 3 M3 saturated M2 saturated T M2 active U O v 2 F 1 G H M1 sat- M1 I J K urated active 0 Fig. 5.3-2 0 1 2 3 4 5 vIN M1 sat. when VGG2-VGS2 VGS1-VT → vIN 0.5(VGG2+VTN) where VGS1=VGS2 M2 sat. when VDS2VGS2-VTN → vOUT-VDS1VGG2-VDS1-VTN → vOUT VGG2-VTN M3 is saturated when VDD-vOUT VDD - VGG3 - |VTP| → vOUT VGG3 + |VTP| CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-7 Large-Signal Voltage Swing Limits of the Cascode Amplifier Maximum output voltage, vOUT(max): vOUT(max) = VDD Minimum output voltage, vOUT(min): Referencing all potentials to the negative power supply (ground in this case), we may express the current through each of the devices, M1 through M3, as 2 vDS1 i = (V - V )v - ≈ (V - V )v D1 1 DD T1 DS1 2 1 DD T1 DS1 (vOUT - vDS1)2 i = (V - v - V )(v - v ) - D2 2 GG2 DS1 T2 OUT DS1 2 2(VGG2 - vDS1 - VT2)(vOUT - vDS1) and 3 2 iD3 = 2 (VDD − VGG3 − VT3) where we have also assumed that both vDS1 and vOUT are small, and vIN = VDD. Solving for vOUT by realizing that iD1 = iD2 = iD3 and 1 = 2 we get, 3 1 1 vOUT(min) = (VDD − VGG3 − VT3)2 + 22 VGG2 − VT2 VDD − VT1 CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-8 Small-Signal Midband Performance of the Cascode Amplifier Small-signal model: gm2vgs2= -gm2v1 G1 D1=S2 D2=D3 + + rds2 + vin = v1 rds3 vout vgs1 gm1vgs1 rds1 - - S1=G2=G3 - Small-signal model of cascode amplifier neglecting the bulk ef fect on M2. C1 r G1 D1=S2 ds2 D2=D3 + + + vin 1 gm1vin C2 v1 gm2v1 rds3 C3 vout rds1 gm2 - - - Using nodal analysis, we can write, Simplified equivalent model of the above circuit. Fig. 5.3-3 [gds1 + gds2 + gm2]v1 − gds2vout = −gm1vin −[gds2 + gm2]v1 + (gds2 + gds3)vout = 0 Solving for vout/vin yields vout −gm1(gds2 + gm2) −gm1 2K'1W1 = = − vin gds1gds2 + gds1gds3 + gds2gds3 + gds3gm2 gds3 L1ID23 The small-signal output resistance is, rout = [rds1 + rds2 + gm2rds1rds2]rds3 rds3 CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-9 Frequency Response of the Cascode Amplifier Small-signal model (RS = 0): C1 rds2 where G1 D1=S2 D2=D3 + + + vin 1 C = C , gm1vin C2 v1 gm2v1 rds3 C3 vout 1 gd1 rds1 gm2 C = C +C +C , and - - - 2 bd1 bs2 gs2 Fig. 5.3-4A C3 = Cbd2+Cbd3+Cgd2+Cgd3+CL The nodal equations now become: (gm2 + gds1 + gds2 + sC1 + sC2)v1 − gds2vout = −(gm1 − sC1)vin and −(gds2 + gm2)v1 + (gds2 + gds3 + sC3)vout = 0 Solving for Vout(s)/Vin(s) gives, Vout(s) 1 −(gm1 − sC1)(gds2 + gm2) = Vin(s) 1 + as + bs2 gds1gds2 + gds3(gm2 + gds1 + gds2) C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) where a = gds1gds2 + gds3(gm2 + gds1 + gds2) C3(C1 + C2) and b = gds1gds2 + gds3(gm2 + gds1 + gds2) CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-10 A Simplified Method of Finding an Algebraic Expression for the Two Poles Assume that a general second-order polynomial can be written as: s s 1 1 s2 P(s) = 1 + as + bs2 = 1 − 1 − = 1 − s + + p1 p2 p1 p2 p1p2 Now if p2 >> p1, then P(s) can be simplified as s s2 P(s) ≈ 1 − + p1 p1p2 Therefore we may write p1 and p2 in terms of a and b as −1 −a p1 = a and p2 = b Applying this to the previous problem gives, −[gds1gds2 + gds3(gm2 + gds1 + gds2)] −gds3 p1 = C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3) C3 The nondominant root p2 is given as −[C3(gds1 + gds2 + gm2) + C2(gds2 + gds3) + C1(gds2 + gds3)] −gm2 p2 = C3(C1 + C2) C1 + C2 Assuming C1, C2, and C3 are the same order of magnitude, and gm2 is greater than gds3, then p1 is smaller than p2. Therefore the approximation of p2 >> p1 is valid. Note that there is a right-half plane zero at z1 = gm1/C1. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-11 Repeating the Previous Example Using Intuitive Approach Circuit: VDD Gain: VPBias1 vout M3 vout ≈ (-gm1vin) rds3 ⇒ ≈ -gm1rds3 p1 vout vin r ≈ r VNBias2 out ds3 Poles: gm1vin M2 p2 1.) Dominant pole (one with the largest resistance to Rin ground): + M1 v -1 vIN in- p ≈ 1 r C 120515-01 ds3 3 -1 2.) Next dominant pole is p2 ≈ Rin(C1+C2) 1 However, in this case, p1 has already shorted the output to ground so that Rin is ≈ gm2 2 -gm2 rather than ≈ . Thus, p2 ≈ . gm2 C1+C2 Much easier!!! CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-12 NON-VOLTAGE DRIVEN CASCODE AMPLIFIER – THE MILLER EFFECT Miller Effect Consider the following inverting amplifier: CM I1 -Av + + Solve for the input impedance: V1 V2 = -AvV1 - - V 1 060610-03 Zin(s) = I1 I1 = sCM(V1 – V2) = sCM(V1 + AvV1) = sCM(1 + Av)V1 Therefore, V1 V1 1 1 Zin(s) = = = = I1 sCM(1 + Av)V1 sCM(1 + Av) sCeq The Miller effect can take Cgd = 5fF and make it look like a 0.5pF capacitor in parallel with the input of the inverting amplifier (Av ≈ -100). If the source resistance is large, this creates a dominant pole at the input. CMOS Analog Circuit Design © P.E. Allen - 2016 Lecture 20 Low Input Resistance Amplifiers (6/24/14) Page 20-13 Simple Inverting Amplifier Driven with a High Source Resistance Examine the frequency response of a current-source load inverter driven from a high resistance source: Assuming the input is Iin, the nodal equations are, [G1 + s(C1 + C2)]V1 − sC2Vout = Iin and (gm1−sC2)V1+[G3+s(C2+C3)]Vout = 0 where G1 = Gs (=1/Rs), G3 = gds1 + gds2, C1 = Cgs1, C2 = Cgd1 and C3 = Cbd1+Cbd2 + Cgd2.
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