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Common Gate Amplifier Figure 1(A) Shows a Common Gate Amplifier with Ideal Current Source Load

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Common Gate Amplifier Figure 1(A) Shows a Common Gate Amplifier with Ideal Current Source Load ” Common Gate Amplifier Figure 1(a) shows a common gate amplifier with ideal current source load. Figure 1(b) shows the ideal current source implemented by PMOS with constant gate to source voltage. VDD VDD V G2 M2 Vo Vo M1 M1 VG1 VG1 Vi Vi (a) (b) Figure 1. Common gate amplifier. 1 1. Low Frequency Small Signal Equivalent Circuit D I2 G1 1 + D2 1 bs1 gs v v 1 V vgs1 g g o m1 ds1 mb ds2 g I1 g + S S V 1 2 i - - (a) D I2 G1 1 + D2 i i V V 1 V m1 vgs1 mb g g o g g ds1 ds2 I1 + S S V 1 2 i - - (b) I1 I2 + + Y V V1 2 YL Zi Zo (c) Figure 2. Common gate amplifier low frequency small signal equivalent circuit. 2 Figure 2(a) and 2(b) show the low frequency small signal equivalent circuit. Figure 2( c) shows the two-port, its port variables assignment are as follows: YL = g ds2 (or ZL = rds2 ); YS = ∞(or ZS = 0) V1 = Vi = −vgs1 , V2 = Vo From Figure 2(b), the current equations are derived to obtain thr Y parameters: I1 = g m1V1 + g mb1V1 + g ds1 (V1 - V2 ) = (g m1 + g mb1 + g ds1 )V1 - g ds1V2 I 2 = −(g m1 + g mb1 )V1 + g ds1 (V2 - V1 ) = −(g m1 + g mb1 + g ds1 )V1 + g ds1V2 The corresponding Y-parameter matrix is, ⎡ (g m1 + g mb1 + g ds1 ) − g ds1 ⎤ Y = ⎢ ⎥ ⎣- (g m1 + g mb1 + g ds1 ) g ds1 ⎦ detY = 0 The input impedance of common gate amplifier is, y 22 + YL g ds1 + g ds2 2g ds 2 Zi = = ≈ = detY + y11YL 0 + (g m1 + g mb1 + g ds1 )g ds2 g m g ds g m This input impedance is low, since gm is large. The output impedance of common gate amplifier is, y11 + YS 1 1 Zo = = = detY + y 22 YS y 22 g ds1 This output impedance is high, since gds1 is very small. A common gate amplifier is primary used as impedance transformer from low to high impedance. The voltage gain of common gate amplifier is, − y 21 g m1 + g mb1 + g ds1 A V0 = = = (g m1 + g mb1 + g ds1 )R out ≈ g m1R out y 22 + YL g ds1 + g ds2 1 where : R out = ZO //ZL = g ds1 + g ds2 This voltage gain is practically the same as the common source amplifier, except for no signal inversion. The current gain of common gate amplifier is, − y 21YL (g m1 + g mb1 + g ds1 )g ds2 A I = = = 1 detY + y11YL 0 + (g m1 + g mb1 + g ds1 )g ds2 3 2. High Frequency Small Signal Equivalent Circuit VDD M2 VG2 Cdb2 Cgd2 Vo Cgd1 Cdb1 M1 CL VG1 C gs1 Cbs1 Vi Figure 3. Common gate amplifier parasitic capacitances. Figure 3 shows all the parasitic capaciatnces needed for high frequency model. Figure 4(a) shows the high frequency small signal equivalent circuit of common gate amplifier. The two-port assignment is shown in Figure 4(b). The network current equation is: I1 = (g m1 + g mb1 )V1 + sCi V1 + g ds1 (V1 - V2 ) = (g m1 + g mb1 + g ds1 + sCi )V1 - g ds1V2 I 2 = −(g m1 + g mb1 )V1 + g ds1 (V2 - V1 ) + sCo V2 = −(g m1 + g mb1 + g ds1 )V1 + (g ds1 + sCo )V The corresponding Y-parameter matrix is: ⎡g m1 + g mb1 + g ds1 + sCi − g ds1 ⎤ Y = ⎢ ⎥ ⎣ - (g m1 + g mb1 + g ds1 ) g ds1 + sCo ⎦ detY = (g m1 + g mb1 + g ds1 + sCi )(g ds1 + sCo ) − g ds1 (g m1 + g mb1 + g ds1 ) 2 = s[g ds1Ci + (g m1 + g mb1 + g ds1 )Co ] + s CoCi 4 G1 D1 D2 + i i + V V 1 + V m1 vgs1 mb g g o g g ds1 ds2 V Vi Co S Ci S1 S2 - Ci=Cgs1+Cbs1 Co=Cgd1+Cdb1+Cgd2+Cdb2+CL (a) I1 I2 + V + + = 1 Y V2 GL VS Zi (b) Figure 4. Common gate amplifier high frequency small signal equivalent circuit. The input impedance is given by: y 22 + YL (g ds1 + sCo ) + g ds2 Zi = = 2 detY + y11YL s[g ds1Ci + (g m1 + g mb1 + g ds1 )Co ] + s Co Ci + (g m1 + g mb1 + g ds1 + sCi )g ds2 (g ds1 + g ds2 ) + sCo = 2 (g m1 + g mb1 + g ds1 )g ds2 + s[(g ds1 + g ds2 )Ci + (g m1 + g mb1 + g ds1 )Co ] + s CoCi The output impedance is given by: 5 y11 + YS 1 1 ZO = = = detY + y 22 YS y 22 g ds1 + sCo The voltage gain is given by: V2 - y 21 g m1 + g mb1 + g ds1 g m1 + g mb1 + g ds1 A V = = = = V1 y 22 + YL (g ds1 + sC o ) +g ds2 (g ds1 +g ds2 ) + sC o (g + g + g )R A = m1 mb1 ds1 out = V0 1+ sC R s o out 1+ p1 The bandwidth is defined by the dominant pole p1. That is, 1 w BW = p1 = R out Co w f = f = f = BW BW -3db p1 2π The gain bandwidth is given by: 1 (g m1 + g mb1 + g ds1 ) w GBW = A V0 w BW = (g m1 + g mb1 + g ds1 )R out = R out Co Co w f = GBW GBW 2π The phase margin PM for the non-inverting amplifier , which the case here, is the distance of the phase angle at the unity gain (or 0db) frequency (fGBW) to –180. That is, 6 ∠A(jw GBW ) = −180 + PM A A(s) = V0 s 1+ p1 ⎛ jw ⎞ ⎜ GBW ⎟ ∠A(s) = ∠A V0 − ∠⎜1+ ⎟ = −180 + PM ⎝ p1 ⎠ ⎛ w ⎞ -1 ⎜ GBW ⎟ -1 = 0 - tan ⎜ ⎟ = −180 + PM = 180 - tan (A V0 ) ⎝ p1 ⎠ ⎛ w ⎞ ⎛ w ⎞ -1 ⎜ GBW ⎟ -1 ⎜ GBW ⎟ -1 PM = 180 - tan ⎜ ⎟ = 180 - tan ⎜ ⎟ = 180 - tan (A V0 ) ⎝ p1 ⎠ ⎝ w BW ⎠ The transfer signal is a single pole with no zero. The PM is always greater 90°. Hence it is stable. Common Gate Amplifier Experiments 3. Common Gate Amplifier Biasing and Low Frequency Small Signal Parameters Determination. The DC or large signal transfer characteristic is difficult to obtain analytically. The reasons are the gate to source voltage and the threshold voltage changes with the input voltage. From Figure 1, these voltages are given by: VGS1 = VG1 - Vi VBS = VSS - Vi Instead of obtaining the complete DC transfer characteristic, only the bias point or operating point is of interest. The operating point should lie in the region when both transistors are in saturation. The goal is to obtain the upper and lower bound of the saturation region. M2, the PMOS transistor in Figure 1 is in saturation when the condition is satisfied. |VGSP|-|VTP|<|VDSP| |VG2-VDD|-|VTP|<|VO-VDD| |0-VDD|-|-1|<|VO-VDD| VDD-1<VDD-VO VO<1 M1, the NMOS transistor in Figure 1 is in saturation when: 7 VGSN-VTN<VDSN VG1-Vi –VTN < VO-Vi VG1<VO+VTN = 1+1=2 VGSN -VTN>0.3 VG1-Vi – VTN >0.3 VG1>0.3+Vi+VTN =0.3+0+1=1.3 ; at bias point Vi=0 That is, 1.3 <VG1<2 this define the range of VG1 when VG2=0 to guarantee that both transistor are in saturation, select say VG1=1.5. With this value selected PSpice simulation is conducted to determine the actual operating point, the bias voltage of the input signal. Initially the PSpice file simply enter a guess value of the bias voltage. This bias will affect the AC response but not the DC response. The bias voltage is obtained by selecting a point at the middle of the steepest slope. The simulation shows that this bias voltage is –1.4903. This information is entered in the PSpice file and re-run to obtain the proper AC response. The operating point and small signal parameters are determined as follows: The threshold voltage is computed at the operating point as follows: VBS = VB - VS = VSS - Vi = −2.5 − (−1.4903) = −1.0097 VTN = VT0 + γ ( φ − VBS − φ ) = 1+1( 0.6 − (−1.0097) − 0.6) = 1.4909 The operating point current is ⎛ W ⎞ ⎛ 9.6E - 6 ⎞ β N = K N ⎜ ⎟ = 40E - 6⎜ ⎟ = 87.27E - 6 ⎝ L ⎠ N ⎝ (5.4 -1)E - 6 ⎠ I DSQ = I N = I1 = I 2 = I P ⎛ βN ⎞ 2 ⎛ βN ⎞ 2 = ⎜ ⎟(VGSN - VTN ) = ⎜ ⎟(VG1 - Vi - VTN ) ⎝ 2 ⎠ ⎝ 2 ⎠ ⎛ 87.27E - 6) ⎞ = ⎜ ⎟(1.5 − (−1.4903) −1.4909) 2 = 98.21uA ⎝ 2 ⎠ The transconductances and resistances are computed: 8 g m1 = g mN = 2β N I DSQ = 2(87.27E - 6)(98.2E - 6) = 130.95E - 6 = 130.95umho γ 1 g mb1 = g m1 = (130.95E - 6) = 51.7625E - 6 = 51.7625umhoA 2 φ − VBS 2 0.6 − (−1.0097) 1 1 rds1 = R ON = = = .509E6 = .509M λ N I DSQ (.02)((98.21E - 6) 1 g ds1 = = 1.9642E - 6 rds1 1 1 rds2 = R OP = = = .509E6 = .509M λP I DSQ (.02)((98.21E - 6) 1 g ds2 = = 1.9642E - 6 rds2 R out = (R ON //R OP ) = .2545E6 = .2545M g ds1 + g ds2 (1.9642 +1.9642)E - 6 Zi = = = 1.08E4 (g m1 + g mb1 + g ds1 )g ds2 (130.95 + 51.7625 +1.9642)E - 6(1.9642E - 6) A V = (g m1 + g mb1 + g ds1 )R out = (130.95 + 51.7625 +1.9642)E - 6(.2545E6) = 47 A Vdb = 20log10 (A V ) = 20log10 (47) = 33.44 db The PSpice simulation shows that 4 Zi=1.032x10 5 Zo=2.543x10 Av=33.756db. *PSpice file for NMOS Common Gate Amplifier with *PMOS Current Load *Filename="Lab3.cir" VIN 1 0 DC -1.4903VOLT AC 1V VDD 3 0 DC 2.5VOLT VSS 4 0 DC -2.5VOLT VG1 5 0 DC 1.5VOLT VG2 6 0 DC 0VOLT M1 2 5 1 4 MN W=9.6U L=5.4U M2 2 6 3 3 MP W=25.8U L=5.4U .MODEL MN NMOS VTO=1 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL MP PMOS VTO=-1 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 9 *Analysis .DC VIN -2.5 2.5 0.05 .TF V(2) VIN .AC DEC 100 1HZ 10GHZ .PROBE .END V(2)/VIN = 4.894E+01 INPUT RESISTANCE AT VIN = 1.032E+04 OUTPUT RESISTANCE AT V(2) = 2.543E+05 10 4.
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