JFET Integration Using a Foundry SOI Photonics Platform

applied sciences

Article JFET Integration Using a Foundry SOI Photonics Platform

Shuxia Li, N. Garry Tarr and Winnie N. Ye * Department of Electronics, Carleton University, Ottawa, ON K1S 5B6, Canada; [email protected] (S.L.); [email protected] (N.G.T.) * Correspondence: [email protected]

Received: 4 June 2019; Accepted: 17 September 2019; Published: 21 September 2019

Abstract: We explore the monolithic integration of conventional electronics with SOI photonics using the commercial silicon photonics foundry technology offered by A*STAR’s Institute of Microelectronics (IME). This process offers optical waveguide modulators and photodetectors, but was not intended to support transistors. We present the implementation of junction field effect transistors (JFETs) integrated with optical waveguides and photodetectors. A simple SPICE model is developed for the JFETs based on the available ion implant parameters, and the geometry feature size allowed by the technology’s layout rules. We have demonstrated the monolithic integration of photonics and electronics circuits. This work could be useful for application in waveguide sensors and optical telecommunications.

Keywords: silicon photonics; junction ﬁeld-eﬀect transistor (JFET); optoelectronics integration

1. Introduction Conventional complementary metal oxide semiconductor (CMOS) technology has been the most important technology for the fabrication of microelectronic circuits for decades. The hybrid (non-monolithic) integration method has been employed during its development. However, monolithic microelectronics integrated with silicon photonics offers advantages in terms of improved signal-to-noise ratio, reduced parasitic capacitance, better reliability, and lower transmission cross-talk. Unfortunately, at the time of project fabrication, there is no public access to commercial foundries for the monolithic integration of full CMOS microelectronics and photonic components, even though several companies including Intel, Luxtera, and IBM have such technologies available for their internal use. For example, IBM developed a silicon photonic transmitter for next-generation short-reach optical interconnects. This is the first demonstration of a fully monolithically integrated silicon photonic four-level pulse amplitude modulation (PAM) transmitter, operating at 56 Gb/s with error-free transmission [1]. Most recently, 45-nm and 32-nm SOI CMOS circuits were fabricated on a “zero-change” silicon photonics platform by the IBM/Global Foundries, demonstrating monolithic silicon photonic platforms in the state-of-the-art CMOS SOI processes [2]. In order to achieve electronic transistors integrated with photonic devices, we have therefore investigated the realization of junction field effect transistors (JFETs) in a foundry SOI photonics technology, which is offered by A*Star’s Institute of Microelectronics (IME) (Singapore). Although the silicon MOSFET is a workhorse device of modern electronic design, JFETs have their unique advantages: very low current noise, high input impedance, insensitivity to temperature, and immunity to radiation. Hence, JFETs are widely used as input amplifiers in oscilloscopes, electronic voltmeters, and other measuring and testing equipment [3]. They are also an excellent choice for monolithic integration with photodetectors on an SOI platform. For example, n-channel JFETs were integrated with silicon PIN detectors for biomedical applications reported in [4–6]. In addition, the epitaxial growth of JFETs was also developed for monolithic

Appl. Sci. 2019, 9, 3964; doi:10.3390/app9193964 www.mdpi.com/journal/applsci Appl. Sci. 2019, 9, x FOR PEER REVIEW 2 of 8 alsoAppl. Sci.developed2019, 9, 3964 for monolithic photoreceiver integration [7,8]. In this work, we have focused2 ofon 8 designing and demonstrating the monolithic integration of electronic transistors (JFETs) with photonic components. We have also concentrated on devices suitable for sensor integration, in part photoreceiver integration [7,8]. In this work, we have focused on designing and demonstrating the because many important applications of SOI-based photonic sensing are under development, but also monolithic integration of electronic transistors (JFETs) with photonic components. We have also because the speed requirements of sensors are usually much more relaxed than those needed in concentrated on devices suitable for sensor integration, in part because many important applications telecommunications. However, with the availability of more advanced lithography than was of SOI-based photonic sensing are under development, but also because the speed requirements of available for this project, the techniques and devices developed in this work could be extended to sensors are usually much more relaxed than those needed in telecommunications. However, with the telecommunications or data communication applications. availability of more advanced lithography than was available for this project, the techniques and devices 2.developed JFET Design in this and work Characteristics could be extended to telecommunications or data communication applications. 2. JFETWe Designuse the andIME Characteristics Silicon Electronic Photonic Integration Circuit (SiEPIC) technology to achieve the photonicWe use the and IME electronic Silicon Electronic integration. Photonic The Integrationprocess is intended Circuit (SiEPIC) for the technology integration to achieveof passive the photonic anddevices electronic (waveguide, integration. grating The couplers, process is mu intendedltiplexer, for etc.) the integration and active of photonic passivephotonic devices (modulators,devices (waveguide, Ge photodiodes, gratingcouplers, resonators multiplexer,, etc.) onto aetc.) monolithic and active chip. photonic Various n devices-type and (modulators, p-type ion implantsGe photodiodes, for pn junction resonators, formation etc.) onto used a monolithicin optical modula chip. Varioustors andn-type epitaxial and pGe-type photodetectors ion implants are for availablepn junction [9]. formation It starts usedwith ina opticalsequence modulators of selective and etching, epitaxial hard Ge photodetectors mask deposition, are available waveguide [9]. formation,It starts with ion a sequenceimplants offor selective modulators etching, and hard photod masketectors, deposition, Ge epitaxy, waveguide Ge formation,top implant, ion and implants ends withfor modulators metal connections and photodetectors, and bond pads. Ge Although epitaxy, Ge the top process implant, was andnot intended ends with to metalcreate connections transistors, itand occurred bond pads. to us Although that these the processimplants was could not intendedbe used toto createcreate transistors, JFETs that it occurredcould be toused us that in transimpedancethese implants could amplifiers be used and to other create circuits. JFETs that We couldestimated be used the indoping transimpedance and dimensions amplifiers for each and activeother circuits.region of We the estimated JFET based the on doping the given and impl dimensionsant dosages for eachand energies, active region the Si of film the JFETthicknesses based offered by the process, and the minimum feature sizes allowed by the design rules. The implants on the given implant dosages and energies, the Si film thicknesses offered by the process, and the could also be used to implement lateral bipolar junction transistors (LBJTs), but our previous minimum feature sizes allowed by the design rules. The implants could also be used to implement experiments indicated the maximum LBJT common-emitter current gain is less than unity, and lateral bipolar junction transistors (LBJTs), but our previous experiments indicated the maximum LBJT therefore, these devices do not provide useful amplification [10]. common-emitter current gain is less than unity, and therefore, these devices do not provide useful The perspective view of the n-JFET structure is shown in Figure 1 [3]. An n-channel device is amplification [10]. used since the electron mobility in silicon is roughly three times that of holes. Two ohmic contacts The perspective view of the n-JFET structure is shown in Figure1[ 3]. An n-channel device is are connected at the ends of the channel, with one acting as the source and the other as the drain. used since the electron mobility in silicon is roughly three times that of holes. Two ohmic contacts When a positive voltage is applied to the drain with respect to the source, electrons flow from the are connected at the ends of the channel, with one acting as the source and the other as the drain. source to the drain. Two electrically connected p+ regions on both sides of the channel form the gate. When a positive voltage is applied to the drain with respect to the source, electrons flow from the Here, the device width Z is 10 µm, and the length L is 18 µm. The gate-channel width 2a is 0.8 µm, source to the drain. Two electrically connected p+ regions on both sides of the channel form the gate. and the depth d is 0.22 µm. A reverse bias applied to the gate channel pn junction widens the junction Here, the device width Z is 10 µm, and the length L is 18 µm. The gate-channel width 2a is 0.8 µm, depletion region, modulating the width of the undepleted channel, and hence controlling the current and the depth d is 0.22 µm. A reverse bias applied to the gate channel pn junction widens the junction flow between the source and drain. depletion region, modulating the width of the undepleted channel, and hence controlling the current flow between the source and drain.

Figure 1. Perspective view of an NJFET. Figure 1. Perspective view of an NJFET. SPICE model parameters were calculated using the theoretical analysis of [11]. The most significant SPICE model parameters were calculated using the theoretical analysis of [11]. The most parameters include the pinch-off voltage Vp and cut-off frequency fT. The Vp is the gate-channel voltage significantat which the parameters depletion include region extendsthe pinch-off completely voltage across Vp and the cut-off channel frequency and the currentfT. The Vp flow is the between gate- channel voltage at which the depletion region extends completely across the channel and the current the source and drain is cut off. The cut-off frequency fT refers to the maximum operating frequency, flow between the source and drain is cut off. The cut-off frequency fT refers to the maximum operating above which the JFET can no longer amplify an input signal. Here, Vp and f T were computed using frequency,Equations (1)above and (2)which [11]. the JFET can no longer amplify an input signal. Here, Vp and fT were 2 computed using Equations (1) and (2) [11]. qNDa Vp = Φ0 (1) − 2εsi Appl. Sci. 2019, 9, x FOR PEER REVIEW 3 of 8

𝑞𝑁𝑎 𝑉 = Φ − (1) 2𝜀

Appl. Sci. 2019, 9, 3964 3 of 8 𝑔 𝑔 2µ 𝑞𝑁 𝑎 (2) 𝑓 = ≤ = 2𝜋𝐶 2𝜋𝜀 𝑍𝐿 𝜋ε 𝐿 2 gm gm 2µnqN Da f = ( ) = (2) T 2𝑎 2πε ZL 2 2πC ≤ si πεsiL 2a Փ0 is the built-in potential voltage, ND is the doping concentration in the n-type channel, ɛsi is siliconϕ0 ispermittivity, the built-in q potential is the electron voltage, charge,ND is and the dopinggm is transconductance. concentration in According the n-type to channel, Equationsi (2),is siliconan n-channel permittivity, JFET isq ispreferred the electron for obtaining charge, and a good gm is frequency transconductance. response Accordingdue to the tohigh Equation mobility (2), of anelectronsn-channel compared JFET is preferredto holes. Frequency for obtaining response a good is frequencyalso improved response by using due a to short the high channel mobility length. of electronsThe compared pinch-off tovoltage holes. Frequencyis typically response in the range is also of improved −1 V to by−5 usingV for an short-type channelJFETs [12]. length. Here, EquationThe pinch-off (1) predicts voltage a value is typically of −7.7 in V the at range the n-type of 1 Vdoping to 5 V level for n -typespecified JFETs by [12 the]. Here,IME Equationprocess. The (1) − − predictschannel a width value ofwas 7.7set Vat atthe the minimum n-type doping value levelof 0.8 speciﬁed µm allowed by the by IMEthe IME process. layout The design channel rules. width The − wassimulated set at the JFET minimum drain current value ofis 0.8demonstratedµm allowed in by Fi thegure IME 2; all layout current design curves rules. are The saturated simulated when JFET VDS drainexceeds current 10 V. is As demonstrated the gate bias V inGS Figure increases,2; all the current channel curves conductance are saturated decreases when until V DS itexceeds becomes 10 zero V. Asat thethe gatepinch-off bias V voltage,GS increases, around the − channel7 V. conductance decreases until it becomes zero at the pinch-oﬀ voltage, around 7 V. −

FigureFigure 2. 2.Simulated Simulated junction junction ﬁeld field e ﬀeffectect transistor transistor (JFET) (JFET) drain drain characteristics. characteristics.

TheThe fabricated fabricated JFET JFET drain drain characteristics characteristics are shown are shown in Figure in 3Figure. Textbook 3. Textbook JFET behavior JFET is behavior observed, is withobserved, ID nearly with constant ID nearly in theconstant saturation in the region. saturation However, region. the However, pinch-off thevoltage pinch-off is much voltage larger is thanmuch thelarger design than value, the atdesign V = value,20 V. at This VGS could = −20 be V. due This to the could variation be due of theto the doping variation concentration of the doping in the GS − fabricationconcentration process in orthe inaccurate fabrication doping process profiles or inaccurate estimated bydoping SUPREM profiles simulations. estimated by SUPREM simulations.We plot the transfer characteristics of JFET at VD = 10 V in Figure4. The intersection points on the x-axis and y-axis indicate that the pinch-off voltage is 20 V and the saturation drain current I is 0.14 − DSS mA at V = 0 V, respectively. The actual channel doping level is estimated to be N = 1.6 1017 cm 3, GS D × − based on the measured Vp using Equation (1), which is a little higher than our proposed doping level of 7 1016 cm 3. This dosage variation can be used to explain the difference of predicted and × − measured pinch-off voltage. Revised SPICE model parameters (see Table1) were extracted from Figures3 and4 in order to support circuit design and simulation. There is a notable di fference in the final measurements and target design performance. We believe that this is due to variations in the doping and photolithography steps during the fabrication process. The cut-off frequency is 5 calculated to be 1 GHz according to Equation (2), with the transconductance gm being 1.2 10 × − A/V. The frequency response limitation is dependent on the dimensions and physical constants of the transistors [3]. To obtain a higher frequency response, we can either decrease the channel length L to reduce the capacitance and increase gm, or enhance the channel doping level. In this work, we do not have an option to vary the implant dosage parameters, since these are pre-defined by the fabrication technology. We also have the design limitation of the layout rules with a fixed minimum feature size. However, with possible reductions in feature size by using a more advanced lithography technology, Appl. Sci. 2019, 9, x FOR PEER REVIEW 4 of 8

Appl. Sci. 2019, 9, 3964 4 of 8

Figure 3. Drain characteristics of JFET fabricated in the Institute of Microelectronics (IME) process. we are conﬁdent that the pinch-oﬀ voltage and frequency response of the design can be improved for futureAppl. Sci.We work. 2019 plot, 9 ,the x FOR transfer PEER REVIEW characteristics of JFET at VD = 10 V in Figure 4. The intersection points4 of on 8 the x-axis and y-axis indicate that the pinch-off voltage is −20 V and the saturation drain current IDSS is 0.14 mA at VGS = 0 V, respectively. The actual channel doping level is estimated to be ND = 1.6 × 1017 cm−3, based on the measured Vp using Equation (1), which is a little higher than our proposed doping level of 7 × 1016 cm−3. This dosage variation can be used to explain the difference of predicted and measured pinch-off voltage. Revised SPICE model parameters (see Table 1) were extracted from Figures 3 and 4 in order to support circuit design and simulation. There is a notable difference in the final measurements and target design performance. We believe that this is due to variations in the doping and photolithography steps during the fabrication process. The cut-off frequency is calculated to be 1 GHz according to Equation (2), with the transconductance gm being 1.2 × 10−5 A/V. The frequency response limitation is dependent on the dimensions and physical constants of the transistors [3]. To obtain a higher frequency response, we can either decrease the channel length L to reduce the capacitance and increase gm, or enhance the channel doping level. In this work, we do not have an option to vary the implant dosage parameters, since these are pre-defined by the fabrication technology. We also have the design limitation of the layout rules with a fixed minimum feature size. However, with possible reductions in feature size by using a more advanced lithography technology, we are confident that the pinch-off voltage and frequency response of the design can be improved for futureFigureFigure work. 3. 3.Drain Drain characteristics characteristics of of JFET JFET fabricated fabricated in in the the Institute Institute of of Microelectronics Microelectronics (IME) (IME) process. process.

We plot the transfer characteristics of JFET at VD = 10 V in Figure 4. The intersection points on the x-axis and y-axis indicate that the pinch-off voltage is −20 V and the saturation drain current IDSS is 0.14 mA at VGS = 0 V, respectively. The actual channel doping level is estimated to be ND = 1.6 × 1017 cm−3, based on the measured Vp using Equation (1), which is a little higher than our proposed doping level of 7 × 1016 cm−3. This dosage variation can be used to explain the difference of predicted and measured pinch-off voltage. Revised SPICE model parameters (see Table 1) were extracted from Figures 3 and 4 in order to support circuit design and simulation. There is a notable difference in the final measurements and target design performance. We believe that this is due to variations in the doping and photolithography steps during the fabrication process. The cut-off frequency is calculated to be 1 GHz according to Equation (2), with the transconductance gm being 1.2 × 10−5 A/V. The frequency response limitation is dependent on the dimensions and physical constants of the transistors [3]. To obtain a higher frequency response, we can either decrease the channel length L to reduce the capacitance and increase gm, or enhance the channel doping level. In this work, we do not have an option to vary the implant dosage parameters, since these are pre-defined by the fabrication technology. We also have the design limitation of the layout rules with a fixed minimum feature size.

However, withFigureFigure possible 4. 4.Transfer Transfer reductions characteristics characteristics in feature of of JFET JFETsize fabricated byfabricated using in a in themore the IME IME advanced process process (V lithography (VD D= =10 10 V). V). technology, we are confident that the pinch-off voltage and frequency response of the design can be improved Table 1. JFET HSPICE model parameters. for future work. Parameters Name (Unites) Design Value Revised Value Transconductance Beta (A/V) 1.5 10 5 1.2 10 5 × − × − Channel length modulation λ (V 1) 5.3 10 3 0.01 − × − Pinch-oﬀ voltage Vp (V) 7.7 20 − − Cut-oﬀ frequency f T (GHz) 0.64 1 Gate junction saturation current Is (A) 7.3 10 5 1.4 10 4 × − × − Gate-drain zero-bias capacitance Cgd (nF) 5.2 10 4 5.1 × − Source (drain) resistance Rs 30 400

3. Optoelectronics Integration In order to demonstrate a full integration of optical components and electronic circuits, we included grating couplers, a strip waveguide, Ge photodiodes, and transimpedance ampliﬁers in the prototype SOI chip. All optical components are selected from the design library oﬀered by the foundry service.

Figure 4. Transfer characteristics of JFET fabricated in the IME process (VD = 10 V). Appl. Sci. 2019, 9, x FOR PEER REVIEW 5 of 8

Table 1. JFET HSPICE model parameters.

Name Parameters Design Value Revised Value (Unites) Transconductance Beta (A/V) 1.5×10 1.2×10 Channel length modulation λ (V−1) 5.3×10 0.01 Pinch-off voltage Vp (V) −7.7 −20 Cut-off frequency fT (GHz) 0.64 1 Gate junction saturation current Is (A) 7.3×10 1.4×10 Gate-drain zero-bias capacitance Cgd (nF) 5.2×10 5.1 Source (drain) resistance Rs 30 400

3. Optoelectronics Integration In order to demonstrate a full integration of optical components and electronic circuits, we includedAppl. Sci. grating2019, 9, 3964 couplers, a strip waveguide, Ge photodiodes, and transimpedance amplifiers in the5 of 8 prototype SOI chip. All optical components are selected from the design library offered by the foundry service. We custom designed the transimpedance amplifiers by using LBJTs and JFETs. FigureWe custom 5 shows designed a block the diagram transimpedance of the integration, ampliﬁers byusing using the LBJTs standard and JFETs.processing Figure parameters5 shows a supportedblock diagram by A*STAR of the integration,IME’s silicon using photonic the standard multi-project processing wafer parametersservice. A waveguide supported byis used A*STAR to carryIME’s and silicon transmit photonic light on multi-project the integrated wafer platform. service. A A500 waveguide nm × 220 isnm used strip to waveguide carry and transmitwas used light to connecton the each integrated optical platform. component. A 500 The nm TE 1550-nm220 nm stripsurface waveguide grating coupler was used and to Ge connect PIN photodiode each optical × werecomponent. selected in The the TE support 1550-nm library surface for input/outp grating couplerut light and coupling Ge PIN and photodiode detection. wereA transimpedance selected in the amplifiersupport (TIA) library is forconnected input/output at the lightback couplingend of th ande Gedetection. photodetector. A transimpedance As we mentioned ampliﬁer previously, (TIA) is theconnected IME silicon at the photonics back end general-purpose of the Ge photodetector. fabrication Asprocess we mentioned does not support previously, the thefabrication IME silicon of MOSphotonics devices general-purpose due to a lack of fabricationpolysilicon process deposition does availability. not support A the MOSFET fabrication would of MOS also devicesneed a high- due to qualitya lack gate of polysilicon oxide. Therefore, deposition we availability.chose to demonstrate A MOSFET the would integrated also needelectronic a high-quality components gate using oxide. anTherefore, n-channel we JFET. chose to demonstrate the integrated electronic components using an n-channel JFET.

FigureFigure 5. 5.BlockBlock diagram diagram of ofa complementary a complementary metal metal oxid oxidee semiconductor semiconductor (CMOS) (CMOS) photonic photonic circuit. circuit.

FigureFigure 66 shows shows a amicroscopic microscopic image image of ofthe the entire entire integrated integrated circuit. circuit. For Forthe optical the optical device, device, we selectedwe selected design design models models from the from PDK the layout PDK library layout that library have that been have verified been by verified other research by other groups. research Thegroups. transimpedance The transimpedance amplifier on amplifier the image on was the constructed image was by constructed using LBJTs, by which using LBJTs,was followed which by was a differentialfollowed by JFET a diff amplifier.erential JFET The amplifier.schematic Thediagram schematic is shown diagram in Figure is shown 7. A photodiode in Figure7. Ais photodiodeillustrated byis D1; illustrated a common-emitter by D1; a common-emitter input (Q1) and an input emitter (Q1) follower and an emitter(Q2) are follower used to create (Q2) are a low-impedance used to create a outputlow-impedance and the feedback output andsource the in feedback the first source stage. inA thedifferential first stage. JFET A diamplifierfferential works JFET amplifieras the second works stage,as the and second provides stage, a andregulated provides output a regulated by adjusting output the by reference adjusting voltage the reference VREF. All voltage the resistors VREF. Allwere the realizedresistors by were an n- realizedtype or p- bytype an n implant-type or onp-type the monolithic implant on silicon the monolithic chip. silicon chip. Figure8 shows the optical testing setup, where a tunable laser, Luna Phoniex 1400, and an HP 4145 semiconductor analyzer were used. Successful rectifying characteristics were demonstrated in Figure9: with an incident light power of 100 µW, the photocurrent of the integrated Ge waveguide photodiode was measured as 10 times higher than the dark current at the 1550-nm wavelength. The photocurrent obtained was intended to be further amplified through the LBJTs and JFETs amplifiers demonstrated in Figure7. Appl. Sci. 2019, 9, x FOR PEER REVIEW 6 of 8

FigureFigure 6. MicroscopicMicroscopic view view of of the the integrated integrated optoelectron optoelectronicic circuit, circuit, showing showing the the grating grating couplers, couplers, Ge Gephotodiodes, photodiodes, and and transimpedance transimpedance amplifier ampliﬁer fabricated fabricated by bythe the IME IME process. process.

Figure 7. Transimpedance amplifier constructed by lateral bipolar junction transistors (LBJTs) and JFETs.

Figure 8 shows the optical testing setup, where a tunable laser, Luna Phoniex 1400, and an HP 4145 semiconductor analyzer were used. Successful rectifying characteristics were demonstrated in Figure 9: with an incident light power of 100 µW, the photocurrent of the integrated Ge waveguide photodiode was measured as 10 times higher than the dark current at the 1550-nm wavelength. The photocurrent obtained was intended to be further amplified through the LBJTs and JFETs amplifiers demonstrated in Figure 7.

Figure 8. A setup for Ge photodiode measurement. Appl. Sci. 2019, 9, x FOR PEER REVIEW 6 of 8

Appl. Sci. 2019, 9, x FOR PEER REVIEW 6 of 8

Figure 6. Microscopic view of the integrated optoelectronic circuit, showing the grating couplers, Ge photodiodes, and transimpedance amplifier fabricated by the IME process.

Appl. Sci.Figure2019 6., 9 ,Microscopic 3964 view of the integrated optoelectronic circuit, showing the grating couplers, Ge 6 of 8 photodiodes, and transimpedance amplifier fabricated by the IME process.

Figure 7. Transimpedance amplifier constructed by lateral bipolar junction transistors (LBJTs) and JFETs.

Appl. Sci. 2019, 9, x FOR PEER REVIEWFigure 8. A setup for Ge photodiode measurement. 7 of 8

Figure 8. A setup for Ge photodiode measurement.

Figure 9. Measured current–voltage characteristics of the Ge photodiode under 1550-nm optical power Figure 9. Measured current–voltage characteristics of the Ge photodiode under 1550-nm optical (100 µW) and dark condition. power (100 µW) and dark condition.

The fabricated JFET behaves well, including the expected drain characteristics (see Figure 3) and transfer characteristics (see Figure 4), with an estimated 1 GHz cut-off frequency. With the revised SPICE model parameters in Table 1, electronic circuitry could be designed and monolithically integrated with the photonic components provided by the IME technology [10,13].

4. Conclusions We have demonstrated the monolithic integration of photonics and electronics components using a commercial foundry SOI photonics technology provided by Singapore’s A*STAR Institute of Microelectronics (IME). In particular, we have investigated the realization of JFETs integrated with standard optical components. Using available implant parameters and Si film thicknesses, doping levels in the film were estimated and used to design our JFETs. The dimensions were designed in accordance with the technology’s layout rules. Working n-channel JFETs were successfully demonstrated, although the measured pinch-off voltage was much higher than expected. The frequency response of the JFET amplifiers should be adequate for many important applications in SOI-based photonic sensing. With the optimization of the bandwidth, gain, and noise of the transimpedance amplifier, our design could be useful for optical receivers in fiber telecommunications and data centers.

Funding: This research was funded by National Science and Engineering Research Council of Canada and Canada Research Chairs Program.

Acknowledgments: This project was fabricated by IME with the support of the Silicon Electronic Photonic Integrated Circuits (SiEPIC) workshop program through CMC Microsystems.

Conflicts of Interest: The authors declare no conflict of interest.

References

The fabricated JFET behaves well, including the expected drain characteristics (see Figure3) and transfer characteristics (see Figure4), with an estimated 1 GHz cut-o ﬀ frequency. With the revised SPICE model parameters in Table1, electronic circuitry could be designed and monolithically integrated with the photonic components provided by the IME technology [10,13].

4. Conclusions We have demonstrated the monolithic integration of photonics and electronics components using a commercial foundry SOI photonics technology provided by Singapore’s A*STAR Institute of Microelectronics (IME). In particular, we have investigated the realization of JFETs integrated with standard optical components. Using available implant parameters and Si film thicknesses, doping levels in the film were estimated and used to design our JFETs. The dimensions were designed in accordance with the technology’s layout rules. Working n-channel JFETs were successfully demonstrated, although the measured pinch-off voltage was much higher than expected. The frequency response of the JFET amplifiers should be adequate for many important applications in SOI-based photonic sensing. With the optimization of the bandwidth, gain, and noise of the transimpedance amplifier, our design could be useful for optical receivers in fiber telecommunications and data centers.

Author Contributions: Conceptualization, S.L. and N.G.T.; methodology, S.L. and N.G.T.; validation, S.L.; formal analysis, S.L., N.G.T., and W.N.Y.; investigation, S.L.; resources, S.L. and W.N.Y.; data curation, S.L. writing—original draft preparation, S.L.; writing—review and editing, N.G.T. and W.N.Y.; visualization, S.L.; supervision, N.G.T. and W.N.Y.; project administration, N.G.T. and W.N.Y. Funding: This research was funded by National Science and Engineering Research Council of Canada and Canada Research Chairs Program. Acknowledgments: This project was fabricated by IME with the support of the Silicon Electronic Photonic Integrated Circuits (SiEPIC) workshop program through CMC Microsystems. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References

1. Xiong, C.; Gill, D.M.; Proesel, J.E.; Orcutt, J.S.; Haensch, W.; Green, W.M.J. Monolithic 56 Gb/s silicon photonic pulse-amplitude modulation transmitter. Optica 2016, 3, 1060–1065. [CrossRef] 2. Stojanovic, V.; Ram, R.J.; Popovic, M.; Lin, S.; Moazeni, S.; Wade, M.; Sun, C.; Alloatti, L.; Atabaki, A.; Pavanello, F.; et al. Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes. Opt. Express 2018, 26, 13106–13121. [CrossRef][PubMed] 3. Kano, K. Semiconductor Devices; Prentice Hall Inc., Simon&Schuster: Upper Saddle River, NJ, USA, 1998. 4. Safavi-Naeini, M.; Franklin, D.R.; Lerch, M.L.F.; Petasecca, M.; Pignatel, G.U.; Reinhard, M.; Dalla Betta, G.-F.D.; Zorzi, N.; Rosenfeld, A.B. Evaluation of silicon detectors with integrated JFET for biomedical applications. IEEE Trans. Nucl. Sci. 2009, 56, 1051–1055. [CrossRef] 5. Betta, G.F.D.; Pignatel, G.U.; Verzellesi, G.; Boscardin, M.; Fazzi, A.; Bosisio, L. Monolithic integration of Si-PIN diodes and n-channel double-gate JFET’s for room temperature X-ray spectroscopy. Nucl. Instrum. Methods Phys. Res. A 2001, 458, 275–280. [CrossRef] 6. Betta, G.-F.D.; Piemonte, C.; Boscardin, M.; Gregori, P.; Zorzi, N.; Fazzi, A.; Pignatel, G.U. An improved PIN photodetector with integrated JFET on high-resistivity silicon. Nucl. Instrum. Methods Phys. Res. A 2006, 567, 368–371. [CrossRef] 7. Renaud, J.-C.; Nguyen, N.L.; Allovon, M.; Blanconnier, P.; Vuye, S.; Scavennec, A. GaInAs monolithic photoreceiver integrating p-i-n/JFET with diﬀused junctions and a resistor. J. Lightwave Technol. 1988, 6, 1507–1511. [CrossRef] 8. Wang, J.; Yu, M.-B.; Lo, G.-Q.; Kwong, D.-L.; Lee, S. Silicon waveguide integrated Germanium JFET photodetector with improved speed performance. IEEE Photonics Technol. Lett. 2011, 23, 765–767. [CrossRef] 9. Liow, T.-Y.; Ang, K.-W.; Fang, Q.; Song, J.-F.; Xiong, Y.-Z.; Yu, M.-B.; Lo, G.-Q.; Kwong, D.-L. Silicon modulators and Germanium photodetectors on SOI: Monolithic integration, compatibility, and performance optimization. IEEE J. Sel. Top. Quantum Electron. 2010, 16, 307–315. [CrossRef] Appl. Sci. 2019, 9, 3964 8 of 8

10. Li, S.-X.; Tarr, N.G.; Ye, W.N. Monolithic integration of SOI waveguide photodetectors and transimpedance ampliﬁers. Int. Soc. Opt. Photonics 2018, 10537, 105371M. 11. Sima, D. Principles of Semiconductor Devices, 2nd ed.; Oxford University Press: Oxford, UK, 2012. 12. Colinge, J.-P.; Colinge, C.A. Physics of Semiconductor Devices; Kluwer Academic Publishers: Boston, MA, USA, 2002. 13. Li, S.-X.; Tarr, N.G.; Ye, W.N. Monolithic integration of Opto-electronics by silicon photonics foundry service. Proc. SPIE OPTO 2019, 10922, 1092217.

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