Field Effect Transistors in Theory and Practice Application Note
Freescale Semiconductor AN211A Application Note Rev. 0, 7/1993
NOTE: The theory in this application note is still applicable, but some of the products referenced may be discontinued. Field Effect Transistors in Theory and Practice
INTRODUCTION increases, the depletion regions again spread into the channel because of the voltage drop in the channel which There are two types of field-effect transistors, the Junction reverse biases the junctions. As VDS is increased, the Field-Effect Transistor (JFET) and the “Metal-Oxide depletion regions grow until they meet, whereby any further Semiconductor” Field-Effect Transistor (MOSFET), or increase in voltage is counterbalanced by an increase in the Insulated-Gate Field-Effect Transistor (IGFET). The depletion region toward the drain. There is an effective principles on which these devices operate (current controlled increase in channel resistance that prevents any further by an electric field) are very similar — the primary difference increase in drain current. The drain-source voltage that being in the methods by which the control element is made. causes this current limiting condition is called the “pinchoff” This difference, however, results in a considerable difference voltage (Vp). A further increase in drain-source voltage in device characteristics and necessitates variances in circuit produces only a slight increase in drain current. design, which are discussed in this note. The variation in drain current (ID) with drain-source DRAIN DRAIN voltage (VDS) at zero gate-source voltage (VGS) is shown in Figure 2a. In the low-current region, the drain current is GATE GATE linearly related to VDS.AsID increases, the “channel” begins to deplete and the slope of the ID curve decreases. When the VDS is equal to Vp,ID “saturates” and stays relatively SOURCE SOURCE constant until drain-to-gate avalanche, VBR(DSS) is reached. N-CHANNEL JFET P-CHANNEL JFET If a reverse voltage is applied to the gates, channel pinch-off occurs at a lower ID level (Figure 2b) because the depletion JUNCTION FIELD-EFFECT TRANSISTOR (JFET) region spread caused by the reverse-biased gates adds to that produced by VDS. Thus reducing the maximum current In its simplest form the junction field-effect transistor starts for any value of VDS. with nothing more than a bar of doped silicon that behaves as a resistor (Figure 1a). By convention, the terminal into which current is injected is called the source terminal, since, SOURCE DRAIN GATE 1 as far as the FET is concerned, current originates from this N terminal. The other terminal is called the drain terminal. P DRAIN Current flow between source and drain is related to the N (a) drain-source voltage by the resistance of the intervening SOURCE P material. In Figure 1b, p-type regions have been diffused into GATE 1 the n-type substrate of Figure 1a leaving an n-type channel (--) DEPLETION ZONES GATE 2 between the source and drain. (A complementary p-type (b) P device is made by reversing all of the material types.) These SOURCE DRAIN p-type regions will be used to control the current flow N between the source and the drain and are thus called gate P regions. GATE 1 As with any p-n junction, a depletion region surrounds (--) GATE 2 (c) the p-n junctions when the junctions are reverse biased P (Figure 1c). As the reverse voltage is increased, the SOURCE (+) DRAIN depletion regions spread into the channel until they meet, I D +V creating an almost infinite resistance between the source and P DS ID the drain. GATE 2 If an external voltage is applied between source and drain (d) (Figure 1d) with zero gate voltage, drain current flow in the Figure 1. Development of Junction channel sets up a reverse bias along the surface of the gate, Field-Effect Transistors parallel to the channel. As the drain-source voltage
Freescale Semiconductor, Inc., 1993, 2009. All rights reserved. AN211A RF Application Information Freescale Semiconductor 1 on the insulation, covering the entire channel region and, VP LOCUS simultaneously, metal contacts to the drain and source are made as shown in Figure 4d. The contact to the metal area VGS =0 VGS =0 covering the channel is the gate terminal. Note that there ID ID is no physical penetration of the metal through the oxide and V =--1V GS nitride into the substrate. Since the drain and source are IP VGS =--2V isolated by the substrate, any drain-to-source current in the absence of gate voltage is extremely low because the structure is analogous to two diodes connected back to back. V P V(BR)DSS The metal area of the gate forms a capacitor with the V V DS DS insulating layers and the semiconductor channel. The metal (a) (b) area is the top plate; the substrate material and channel are Figure 2. Drain Current Characteristics the bottom plate. Due to the difficulty of diffusing impurities into both sides For the structure of Figure 4, consider a positive gate of a semiconductor wafer, a single ended geometry is potential (see Figure 5). Positive charges at the metal side normally used instead of the two-sided structure discussed of the metal-oxide capacitor induce a corresponding negative above. Diffusion for this geometry (Figure 3) is from one side charge at the semiconductor side. As the positive charge only. The substrate is of p-type material onto which an n-type at the gate is increased, the negative charge “induced” in channel is grown epitaxially. A p-type gate is then diffused the semiconductor increases until the region beneath the into the n-type epitaxial channel. Contact metallization oxide effectively becomes an n-type semiconductor region, completes the structure. and current can flow between drain and source through the The substrate, which functions as Gate 2 of Figure 1, is “induced” channel. In other words, drain current flow is of relatively low resistivity material to maximize gain. For the “enhanced” by the gate potential. Thus drain current flow can same purpose, Gate 1 is of very low resistivity material, be modulated by the gate voltage; i.e. the channel resistance allowing the depletion region to spread mostly into the n-type is directly related to the gate voltage. The n-channel structure channel. In most cases the gates are internally connected may be changed to a p-channel device by reversing the together. A tetrode device can be realized by not making material types. this internal connection. SOURCE DRAIN GATE SOURCE DRAIN DRAIN
TYPE C GATE GATE SUBSTRATE SUBSTRATE SOURCE SOURCE P P I DRAIN DRAIN D N TYPE B GATE GATE P L (SUBSTRATE) SUBSTRATE SUBSTRATE CHANNEL SOURCE SOURCE CHANNEL LENGTH N-CHANNEL MOSFET P-CHANNEL MOSFET Figure 3. Junction FET with Single-Ended Geometry
MOS FIELD-EFFECT TRANSISTORS (MOSFET) SOURCE DRAIN The metal-oxide-semiconductor (MOSFET) operates with NN a slightly different control mechanism than the JFET. Figure 4 P P shows the development. The substrate may be high (SUBSTRATE) (SUBSTRATE) resistivity p-type material, as for the 2N4351. This time two separate low-resistivity n-type regions (source and drain) are (a) (b) diffused into the substrate as shown in Figure 4b. Next, the SILICON NITRATE SGMETAL D surface of the structure is covered with an insulating oxide OXIDE Si3N4 layer and a nitride layer. The oxide layer serves as a SiO2 protective coating for the FET surface and to insulate the channel from the gate. However the oxide is subject to NN NN contamination by sodium ions which are found in varying P P quantities in all environments. Such contamination results (SUBSTRATE) (SUBSTRATE) in long term instability and changes in device characteristics. Silicon nitride is impervious to sodium ions and thus is used (c) (d) to shield the oxide layer from contamination. Holes are cut into the oxide and nitride layers allowing metallic contact to Figure 4. Development of Enhancement-Mode the source and drain. Then, the gate metal area is overlaid N-Channel MOSFET
AN211A RF Application Information 2 Freescale Semiconductor SOURCE GATE (+) DRAIN to the increase of carriers in the channel due to application ALUMINUM Si3N4 of gate voltage. A third type of FET that can operate in both SiO2 the depletion and the enhancement modes has also been +++++++++ described. ∓∓∓∓∓∓∓∓∓ The basic differences between these modes can most +++++++++ easily be understood by examining the transfer ------characteristics of Figure 9. The depletion-mode device has considerable drain-current flow for zero gate voltage. Drain N+ N+ current is reduced by applying a reverse voltage to the gate INDUCED terminal. The depletion-type FET is not characterized with CHANNEL forward gate voltage. P (SUBSTRATE) The depletion/enhancement mode type device also has considerable drain current with zero gate voltage. This type device is defined in the forward region and may have usable forward characteristics for quite large gate voltages. Notice Figure 5. Channel Enhancement. Application of that for the junction FET, drain current may be enhanced Positive Gate Voltage Causes Redistribution of Minority by forward gate voltage only until the gate-source p-n Carriers in the Substrate and Results in the Formation junction becomes forward biased. of a Conductive Channel Between Source and Drain The third type of FET operates only in the enhancement mode. This FET has extremely low drain current flow for zero An equivalent circuit for the MOSFET is shown in gate-source voltage. Drain current conduction occurs for a Figure 6. Here, C is the distributed gate-to-channel g(ch) V greater than some threshold value, V . For gate capacitance representing the nitride-oxide capacitance. C GS GS(th) gs voltages greater than the threshold, the transfer is the gate-source capacitance of the metal gate area characteristics are similar to the depletion/enhancement overlapping the source, while C is the gate-drain gd mode FET. capacitance of the metal gate area overlapping the drain. Cd(sub) and Cs(sub) are junction capacitances from drain to SOURCE GATE DRAIN substrate and source to substrate. Yfs is the transadmittance between drain current and gate-source voltage. The modulated channel resistance is rds.RD and RS are the bulk resistances of the drain and source. C C The input resistance of the MOSFET is exceptionally high gs gd because the gate behaves as a capacitor with very low Cg(ch) 14 RS R leakage (rin ≈ 10 ). The output impedance is a function D of rds (which is related to the gate voltage) and the drain and source bulk resistances (RD and RS). rds To turn the MOSFET “on”, the gate-channel capacitance, C , and the Miller capacitance, C , must be charged. CS(sub) CD(sub) g(ch) gd Y V In turning “on”, the drain-substrate capacitance, C ,must fs GS d(sub) P SUBSTRATE be discharged. The resistance of the substrate determines the peak discharge current for this capacitance. Figure 6. Equivalent Circuit of Enhancement- The FET just described is called an enhancement-type Mode MOSFET MOSFET. A depletion-type MOSFET can be made in the following manner: Starting with the basic structure of DIFFUSED Figure 4, a moderate resistivity n-channel is diffused CHANNEL SOURCE GATE DRAIN between the source and drain so that drain current can flow ALUMINUM when the gate potential is at zero volts (Figure 7). In this manner, the MOSFET can be made to exhibit depletion Si3N4 characteristics. For positive gate voltages, the structure SiO2 enhances in the same manner as the device of Figure 4. With negative gate voltage, the enhancement process is reversed and the channel begins to deplete of carriers as N seen in Figure 8. As with the JFET, drain-current flow N+ N+ depletes the channel area nearest the drain first. The structure of Figure 7, therefore, is both a depletion-mode and an enhancement-mode device. P (SUBSTRATE)
MODES OF OPERATION There are two basic modes of operation of FET’s — Figure 7. Depletion Mode MOSFET Structure. depletion and enhancement. Depletion mode, as previously This Type of Device May Be Designed to Operate in mentioned, refers to the decrease of carriers in the channel Both the Enhancement and Depletion Modes due to variation in gate voltage. Enhancement mode refers
AN211A RF Application Information Freescale Semiconductor 3 SOURCE GATE DRAIN and characteristics are necessary to evaluate their (--) SiO2 comparative merits from data-sheet specifications. Si3N4 Static Characteristics ------+++++++++++++ Static characteristics define the operation of an active device under the influence of applied dc operating conditions. +++++++ ++++++ Of primary interest are those specifications that indicate the +++ effect of a control signal on the output current. The V -- N+ N N+ GS ID transfer characteristics curves are illustrated in Figure 9 for the three types of FETs. Figure 10 lists the data-sheet P (SUBSTRATE) specifications normally employed to describe these curves, as well as the test circuits that yield the indicated specifications. Figure 8. Channel Depletion Phenomenon. Of additional interest is the special case of Application of Negative Gate Voltage Causes tetrode-connected devices in which the two gates are Redistribution of Minority Carriers in Diffused Channel separately accessible for the application of a control signal. and Reduces Effective Channel Thickness. This Results The pertinent specifications for a junction tetrode are those in Increased Channel Resistance. which define drain-current cutoff when one of the gates is connected to the source and the bias voltage is applied to the second gate. These are usually specified as VG1S(off), ELECTRICAL CHARACTERISTICS Gate 1 — source cutoff voltage (with Gate 2 connected to Because the basic mode of operation for field-effect source), and VG2S(off), Gate 2 — source cutoff voltage (with devices differs greatly from that of conventional junction Gate 1 connected to source). The gate voltage required for transistors, the terminology and specifications are drain current cutoff with one of the gates connected to the necessarily different. An understanding of FET terminology source is always higher than that for the triode-connected case where both gates are tied together.
N-CHANNEL N-CHANNEL JUNCTION FET
ID VGS = 1 V/STEP DEPLETION ENHANCEMENT VGS =0
DEPLETION ONLY -- 1 V NOT DEFINED = 1 mA/DIV DS
IN THIS AREA I -- 2 V
(--) VGS (+) 0 VDS =2V/DIV N-CHANNEL MOS 2N3797 ID VGS = 1 V/STEP DEPLETION ENHANCEMENT VGS =2V
DEPLETION AND ENHANCEMENT MODE 1V = 1 mA/DIV
DS 0 I -- 1 V -- 2 V
0 VDS =2V/DIV (--) VGS (+) N-CHANNEL MOS 2N4351
ID VGS = 1 V/STEP DEPLETION ENHANCEMENT VGS =4V
ENHANCEMENT ONLY 3V = 1 mA/DIV DS I 2V
0 V =2V/DIV (-- ) VGS VGS(th) (+) DS Figure 9. Transfer Characteristics and Associated Scope Traces for the Three FET Types AN211A RF Application Information 4 Freescale Semiconductor DRAIN DC GATE* mA
SOURCE VDS DEPLETION MODE JFETs ID TEST CIRCUIT FOR IDSS CHARACTERISTIC DESCRIPTION
I @V =0, Zero-gate-voltage drain current. DRAIN DEPLETION MODE IDSS DSS GS DC VP 0.1 IDSS VGS(off) @ID = 0.001 IDSS, Gate voltage necessary to reduce VGS† VDS V DEPLETION/ENHANCEMENT MODE MOSFETs DRAIN ID ENHANCEMENT MODE CHARACTERISTIC DESCRIPTION DC I GATE D(on) An arbitrary current value (usually near mA DEPLETION MODE ID(on) @VGS >0, max rated current) that locates a point VP ENHANCEMENT MODE MOSFETs I TEST CIRCUIT ENHANCEMENT MODE D(on) SAME AS FOR DEPLETION/ ID CHARACTERISTIC DESCRIPTION I ENHANCEMENT D(on) An arbitrary current value (usually near I @V >0, D(on) GS max rated current) that locates a point VGS TEST CIRCUIT V Figure 10. Static Characteristics for the Three FET Types Are Defined by the Above Curves, Tables, and Test Circuits Reach-through voltage is another specification uniquely gate-to-source current with the drain shorted to the source applicable to tetrode-connected devices. This defines the (Figure 11). As might be expected, because the leakage amount of difference voltage that may be applied to the two current across a reverse-biased p-n junction (in the case of gates before the depletion region of one spreads into the a JFET) and across a capacitor (in the case of a MOSFET) junction of the other — causing an increase in gate current is very small, the input resistance is extremely high. At a to some small specified value. Obviously, reach-through is temperature of 25C, the JFET input resistance is hundreds an undesirable condition since it causes a decrease in input of megohms while that of a MOSFET is even greater. For resistance as a result of an increased gate current, and large junction devices, however, input resistance may decrease amounts of reach-through current can destroy the FET. by several orders of magnitude as temperature is raised to 150C. Such devices, therefore, have gate-leakage current Gate Leakage Current specified at two temperatures. Insulated-gate FETs are not Of interest to circuit designers is the input resistance of drastically affected by temperature, and their input resistance an active component. For FETs, this characteristic is remains extremely high even at elevated temperatures. specified in the form of IGSS — the reverse-bias AN211A RF Application Information Freescale Semiconductor 5 VGS(off) AN211A RF Application Information 6 Freescale Semiconductor Dynamic Characteristics voltage conditions as those used for ID(on) or IDSS. Because of the importance of the imaginary component at radio Unlike the static characteristics, the dynamic frequencies, the high frequency y specification should be characteristics of field-effect transistors apply equally to all fs a complex representation, and should be given either in the FETs. The conditions and presentation of the dynamic specifications table or by means of curves showing typical characteristics, however, depend largely upon the intended variations, as in Figure 15 for the MPF102 JFET. application. For example, the following table indicates the The real portion of this high-frequency y ,Re(y )orG , dynamic characteristics needed to adequately describe a fs fs 21 is usually considered a significant figure of merit. FET for various applications. y Another FET parameter that offers a direct vacuum Audio RF-IF Switching Chopper os tube analogy is yos, the output admittance: yfs (1 kHz) yfs (1 kHz) yos = ID/VDS Ciss Ciss Ciss Ciss VGS =K Crss Crss Crss Crss In this case, the analogous tube parameter is rp — i.e., y (1 kHz) GP Cd Cd os (sub) (sub) yos =1/rp. For depletion mode devices, yos is measured with gate and source grounded (see Figure 16). For enhancement NF Re(yis)(HF) rds(on) rds(on) mode units, it is measured at some specified VGS that Re(yos)(HF) td1,td2 permits substantial drain-current flow. NF tr,tf As with yfs, many expressions are used for yos. In addition to the obvious parallels such as y22,gos, and g22,itisalso yfs The forward transadmittance is a key dynamic sometimes specified as rd, where rd =1/yos. characteristic for field-effect transistors. It serves as a basic design parameter in audio and rf circuits and is a widely VDD accepted figure of merit for devices. Because field-effect transistors have many characteristics similar to those of vacuum tubes, and because many engineers still are more comfortable with tube parameters, BYPASS RL the symbol gm used for tube transconductance is often Vout specified instead of yfs. To further confuse things, the “g” D Vin GI school also uses a variety of subscripts. In addition to gm, some data sheets show gfs while others even show g21. AC AC Regardless of the symbol used, yfs defines the relation between an input signal voltage and an output signal current: VTVM Rg VTVM S yfs = ID/VGS VDS =K The unit is the mho — current divided by voltage. Vout Rg TYPICALLY 1 M Yfsl = Figure 13 is a typical yfs test circuit for a junction FET. Vin RL RL OF SUCH VALUE AS TO CAUSE As a characteristic of all field-effect devices, yfs is NEGLIGIBLE DC DROP AT IDSS specified at 1 kHz with a VDS the same as that for which ID(on) or IDSS is characterized. Since yfs has both real and Figure 13. Typical yfs Test Circuit imaginary components, but is dominated by the real component at low frequency, the 1 kHz characteristic is given as an absolute magnitude and indicated as y . 6000 fs 5000 2N4222, A V =15V It is interesting to note that yfs varies considerably with DS ID due to nonlinearity in the ID -- V GS characteristics. This TA =25C 2N4221, A variation, for a typical n-channel, JFET is illustrated in f=1.0kHz 3000 Figure 14. Obviously, the operating point must be carefully selected to provide the desired yfs and signal swing. 2000 2N4220, A For tetrode-connected FETs, three yfs measurements are usually specified on data-sheet tables. One of these, with 1000 the two gates tied together, provides a yfs value for the condition where a signal is applied to both gates 700 simultaneously; the others provide the y for the two gates fs 500 individually. Generally, with the two gates tied together, yfs is higher and more gain may be realized in a given circuit. , FORWARD TRANSFER ADMITTANCE (300 mhos) Because of the increased capacitance, however, fs 0.1 0.2 0.5 1.0 2.0 5.0 10 y gain-bandwidth product is much lower. ID, DRAIN CURRENT (mA) For rf field-effect transistors, an additional value of yfs is sometimes specified at or near the highest frequency of Figure 14. Forward Transfer Admittance versus Drain operation. This value should also be measured at the same Current for Typical JFETs AN211A RF Application Information Freescale Semiconductor 7 5.0 In switching applications Ciss is of major importance since gfs a large voltage swing at the gate must appear across Ciss. y fs Thus, C must be charged by the input voltage before 4.0 V =15Vdc iss DS turn-on effectively begins. VGS =0 3.0 Crss Reverse transfer admittance (yrs) does not appear on FET data sheets. Instead Crss, the reverse transfer capacitance, is specified at low frequency. Since yrs for a 2.0 field-effect transistor remains almost completely capacitive -- b fs and relatively constant over the entire usable FET frequency spectrum, the low-frequency capacitance is an adequate 1.0 specification. Crss is measured by the circuit of Figure 18. For tetrode FETs, values should be specified for Gate 1 and for FORWARD TRANSFER ADMITTANCE (mmhos) 0 both gates tied together. 10 20 30 50 100 200 300 500 1000 Again, for switching applications Crss is a critical f, FREQUENCY (MHz) characteristic. Similar to the Cob of a junction transistor, Crss must be charged and discharged during the switching Figure 15. Forward Transfer Admittance versus interval. For a chopper application, Crss is the feedthrough Frequency capacitance for the chopper drive. VDS Vout Cd(sub) For the MOSFET, the drain-substrate junction VDD capacitance becomes an important characteristic affecting D RS the switching behavior. Cd(sub) appears in parallel with the AC AC load in a switching circuit and must be charged and GI BYPASS VTVM VTVM discharged between the two logic levels during the switching S interval. Vout RS OF SUCH VALUE AS TO CAUSE VGS YOS = NEGLIGIBLE DC DROP. VDS RS RS SENSES AC DRAIN CURRENT RFC Figure 16. yos Measurement Circuit for Depletion FETs D Voltages and frequencies for measuring yos should be GI BYPASS exactly the same as those for measuring y .Likey ,itis fs fs S a complex number and should be specified as a magnitude CAPACI- at 1 kHz and in complex form at high frequencies. TANCE METER Yis Closely related to yos and yfs is the amplification fac- Ciss or tor, : Figure 17. C Measurement Circuit = VDS/VGS iss ID =K The amplification factor does not appear on the field-effect transistor registration format but can be calculated as yfs/yos. For most small-signal applications, has little circuit significance. It does, however, serve as a general indication D of the quality of the field-effect manufacturing process. CAPACI- TANCE GI METER Ciss The common-source-circuit input capacitance, Ciss, S takes the place of yis in low-frequency field-effect transistors. R This is because yis is entirely capacitive at low frequencies. g Ciss is conveniently measured in the circuit of Figure 17 for GUARD Y the tetrode JFET. As with yfs, two measurements are V Cc rs GD Crss or necessary for tetrode-connected devices. At very high frequencies, the real component of yis (a) VGD =--VDS becomes important so that rf field-effect transistors should Rg TYPICALLY 1 M Cc AC SOURCE TO GUARD SIGNAL. have yis specified as a complex number at the same conditions as other high-frequency parameters. For Figure 18. Recommended C Test Circuit tetrode-connected rf FETs, reading of both Gate 2 to source rss andGate1tiedtoGate2arenecessary. AN211A RF Application Information 8 Freescale Semiconductor NoiseFigure(NF) Like all other active components, APPLICATIONS field-effect transistors generate a certain amount of noise. The noise figure for field-effect transistors is normally Device Selection specified on the data sheet as “spot noise”, referring to the Obviously, different applications call for special emphasis noise at a particular frequency. The noise figure will vary with on specific characteristics so that a simple figure of merit frequency and also with the resistance at the input of the that compares devices for all potential uses would be hard device. Typical graphs of such variations are illustrated in to formulate. Nevertheless, an attempt to pinpoint the Figure 19 for the 2N5458. From graphs of this kind the characteristics that are most significant for various designer can anticipate the noise level inherent in his design. applications has been made* to permit a rapid, first-order evaluation of competitive devices. rds(on) Channel resistance describes the bulk resistance of The most important single FET parameter, one that the channel in series with the drain and source. From an applies for any amplifier application, is yfs. This parameter, applications standpoint, it is important primarily for switching or one of its many variations, is specified on most data and chopper circuits since it affects the switching speed and sheets, yet some evaluation is required to come up with a determines the output level. To complete the confusion of reasonable comparison. For example, in the table of multiple symbols for FET parameters, channel resistance is electrical characteristics on most JFET data sheets, yfs is sometimes indicated as rd(on) and also as rDS and rds.In specified at IDSS (VGS = 0) where, for JFETs devices, yfs either case, however, it is measured, for JFETs, by tying the is maximum. This is illustrated in Figure 14, where typical gates to the source, setting all terminals equal to 0 Vdc, and variations of yfs as a function of ID are plotted. For some applying an ac voltage from drain to source (see Figure 20). small-signal applications, the IDSS (VGS = 0) point can The magnitude of the ac voltage should be kept low so that actually be used as a dc operating point because there will be no pinchoff in the channel. Insulated-gate FETs small-signal excursions into the forward bias region will not may be measured with dc gate bias in the enhancement actually cause the gate-source junction to become mode. forward-biased. However, in most practical uses, some bias is necessary to allow for the anticipated signal swing; and Rg, SOURCE RESISTANCE (MEGOHMS) — — it must be recognized the y goes down as the bias is 0.2 0.5 1.0 2 5 10 20 50 100 fs 12 increased. VDS =15V It is seen, also, that maximum yfs increases as IDSS increases so that, where maximum y is important, a device 10 Rg =1M ID =IDSS fs TA =25C withahighIDSS specification is normally desirable. 8 On the other hand, where power dissipation is a factor to be considered, the figure of merit yfs/VGS(off) IDSS has been proposed. This term factors in not only I ,which 6 DSS should be low if power dissipation is to be low, but also f=1kHz VGS(off), which indicates maximum input voltage swing. 4 NF, NOISE FIGURE (dB) Since the signal peaks are represented by VGS =VGS(off) and VGS =0,thelowerVGS(off), the higher the figure of merit. 2 And, for amplifier applications requiring a large signal swing, V(BR)GSS/VGS(off) (assuming that VGS(off) is the “pinch-off” 0 voltage) is a satisfactory merit figure because it indicates 10 100 1kHz 10kHz the ratio of maximum and minimum drain voltages. f, FREQUENCY (Hz) For high-frequency circuits, the input capacitance (Ciss) Figure 19. Typical Variations of FET Noise Figure with and the Miller-effect capacitance (Crss) become important, Frequency and Source Resistance so yfs/(Ciss +Crss) indicates a relative measure of device performance. For switching and chopper circuits, a figure of merit is not often useful. Here the magnitudes of Ciss,Crrs, V i AC AM- Cd(sub) and rds are of primary interest. METER Circuits D The types of circuits that can utilize FETs are practically AC unlimited. In fact, many circuits designed to utilize VTVM small--signal pentode tubes can utilize FETs with only minor G S modifications. For example, the circuit in Figure 21 shows a typical rf stage for a broadcast-band auto radio. In this circuit, a MPF102 n-channel JFET has replaced the 12BL6 pentode normally employed. The specifications for the two v devices, including the AGC characteristics, are similar Vds(on) r = ds(on) i enough to perform adequately in the circuit of Figure 21. Figure 20. Circuit for Measuring JFET Channel Resistance * Christiansen, Donald, “Semiconductors: The New Figures of Merit,” EEE, October, 1965. AN211A RF Application Information Freescale Semiconductor 9 MFE4007 D G +12V S VOLUME TO MIXER BIAS TONE TUNING MPF102 D ADJUST S G I -- 120 V -- 3 0 V AGC Figure 21. RF Stage of Broadcast Auto Radio Figure 22. Line Operated Phono Amplifiers In an audio application, a field-effect transistor such as Figure 23 shows three basic chopper circuits. The the 2N5460 can be combined with a high voltage bipolar advantage of the more complex series-shunt circuit (Figure 24c) transistor to make a simple line-operated phonograph is that it balances out the leakage currents of the FETs in amplifier such as that shown in Figure 22. The ceramic order to reduce voltage error and is used to attain high pickup is connected through a potentiometer volume control chopping frequencies. From an applications standpoint, the to the field-effect transistor. Collector current of the transistor, FET circuit is superior to a junction transistor circuit in that in turn, is set by the potentiometer in the source of the FET. there is no offset voltage with the FET turned on. On the With the proper bipolar output transistor, the circuit can be minus side, however, the field-effect-transistor chopper driven directly from the rectified line voltage, while the low generally has a higher series resistance (rds(on)) than the voltage for the FET can be derived from a voltage divider junction transistor. in the power supply line. As newer and better FETs are introduced and as a larger number of designers learn to use them, the range of applications of FETs should broaden considerably. With its high input impedance, the field-effect transistor will play an important role in input circuitry for instrumentation and audio applications where low-impedance junction transistors have generally been least successful. MFE2012 eout RS MFE2012 MFE2012 R es L ec RS ec (a) SERIES CHOPPER CIRCUIT es ec RL Re RS MFE2012 (c) SERIES-SHUNT CHOPPER ec es RL Re (b) SHUNT CHOPPER Figure 23. FET Chopper Circuits AN211A RF Application Information 10 Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright Home Page: licenses granted hereunder to design or fabricate any integrated circuits based on the freescale.com information in this document. Web Support: Freescale reserves the right to make changes without further notice to any products freescale.com/support herein. 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U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. E 1993, 2009 Freescale Semiconductor, Inc. AN211A RFAN211A Application Information FreescaleRev. 0, 7/1993 Semiconductor 11