AN-1206 Application Note

AN-1206 APPLICATION NOTE One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Variable Gain Inverting Amplifier Using the AD5292 Digital Potentiometer and the OP184 Op Amp VDD CIRCUIT FUNCTION AND BENEFITS R3 1kΩ +15V/+30V This circuit provides a low cost, high voltage, variable gain V+ OP184 VOUT inverting amplifier using the AD5292 digital potentiometer V V– IN –15V/GND R2 in conjunction with the OP184 operational amplifier. 4.99kΩ ± 1% C1 V 10pF SS The circuit offers 1024 different gains, controllable through an SPI-compatible serial digital interface. The ±1% resistor tolerance VDD R +15V/+30V AW performance of the AD5292 provides low gain error over the RAB 20kΩ full resistor range, as shown in Figure 2. AD5292 SERIAL INTERFACE VSS The circuit supports input and output rail to rail for both single –15V/GND 08426-001 supply operation at +30 V and dual supply operation at ±15 V; Figure 1. Variable Gain Inverting Amplifier (Simplified Schematic: and is capable of delivering up to ±6.5 mA output current. Decoupling and All Connections Not Shown) In addition, the AD5292 has an internal 20-times programmable The circuit gain equation is memory that allows a customized gain setting at power-up. The (1024 − D)× RAB circuit provides accuracy, low noise, low THD, and is well suited G = − 1024 (3) for signal instrumentation conditioning. R2 CIRCUIT DESCRIPTION where D is the code loaded in the digital potentiometer. Table 1. Devices Connected/Referenced When the circuit input is an ac signal, the parasitic capacitances Product Description of the digital potentiometer can cause undesirable oscillation in AD5292 10-bit, 1% resistor tolerance digital potentiometer the output. This can be avoided, however, by connecting a small Rail-to-rail input and output, low noise, high slew capacitor, C1, between the inverter input and its output. A value OP184 rate operational amplifier of 10 pF was used for the gain and phase plots shown in Figure 3. This circuit employs the AD5292 digital potentiometer in con- A simple modification of the circuit provides a logarithmic junction with the OP184 operational amplifier, providing a low gain function, as shown in Figure 4. In this case, the digital cost variable gain noninverting amplifier. potentiometer is configured in the ratiometric mode. 1024 – D The input signal VIN is amplified by the OP184. The op amp G = (4) offers low noise, high slew rate, and rail-to-rail input and output. D The maximum circuit gain is defined in Equation 1. where D is the code loaded in the digital potentiometer. A gain plot versus code is shown in Figure 5. R R = − AB ⇒ = − AB G R2 (1) The circuit gain is defined in Equation 4. R2 G The maximum current through the AD5292 is ±3 mA, which The AD5292 has a 20-times programmable memory, which allows presetting the output voltage in a specific value at power-up. limits the maximum input voltage, VIN, based on the circuit gain, as Equation 2 describes. Excellent layout, grounding, and decoupling techniques must be utilized in order to achieve the desired performance from the VIN ≤ 0.003 × R2 (2) circuits discussed in this note (see MT-031 Tutorial and When the input signal connected to VIN is higher than the MT-101 Tutorial). As a minimum, a 4-layer PCB should be theoretical maximum value from Equation 2, R2 should be used with one ground plane layer, one power plane layer, increased, and the new gain can be recalculated using Equation 1. and two signal layers. The ±1% internal resistor tolerance of the AD5292 ensures a low gain error, as shown in Figure 2. Rev. C | Page 1 of 2 AN-1206 Application Note Excellent layout, grounding, and decoupling techniques must be 10k utilized in order to achieve the desired performance from the circuits discussed in this note (see MT-031 Tutorial and MT-101 100 Tutorial). As a minimum, a 4-layer PCB should be used with one ground plane layer, one power plane layer, and two signal layers. 1 COMMON VARIATIONS GAIN The AD5291 (8-bits with 20-times programmable power-up 0.01 memory) and the AD5293 (10-bits, no power-up memory) are both ±1% tolerance digital potentiometers that are suitable for this application. 0.0001 0 500 1000 CODE (Decimal) 3 3 08426-005 Figure 5. Logarithmic Gain Function 2 2 LEARN MORE 1 GAIN 1 ERROR (%) MT-031 Tutorial, Grounding Data Converters and Solving the 0 0 Mystery of "AGND" and "DGND", Analog Devices. GAIN –1 –1 ERROR (%) MT-032 Tutorial, Ideal Voltage Feedback (VFB) Op Amp, Analog GAIN –2 –2 Devices. –3 –3 MT-087 Tutorial, Voltage References, Analog Devices. –4 –4 MT-091 Tutorial, Digital Potentiometers, Analog Devices. 0 200 400 600 800 1000 CODE (Decimal) 08426-002 MT-101 Tutorial, Decoupling Techniques, Analog Devices. Figure 2. Gain and Gain Error vs. Decimal Code Data Sheets and Evaluation Boards 400 PHASE, R = 20kΩ 20 AW 375 PHASE, R = 100Ω AD5291 Data Sheet. AW 350 10 PHASE, RAW = 10kΩ 325 300 AD5292 Data Sheet. 0 275 GAIN, R = 10kΩ AW 250 AD5292 Evaluation Board. GAIN, R = 20kΩ –10 AW 225 200 AD5293 Data Sheet. –20 175 GAIN (dBV) GAIN 150 OP184 Data Sheet. –30 125 PHASE (Degrees) GAIN, RAW = 100Ω –40 100 75 REVISION HISTORY –50 50 25 4/13—Rev. B to Rev. C –60 0 6001k10k 100k 200k FREQUENCY (Hz) Changed Document Name from CN-0113 to 08426-003 Figure 3. Gain and Phase vs Frequency for AC Input Signal AN-1206 .............................................................................. Universal V 4/10—Rev. A to Rev. B R3 DD 1kΩ Changes to Circuit Function and Benefits Section ....................... 1 OP184 V OUT 12/09—Rev. 0 to Rev. A Corrected trademark ......................................................................... 1 C1 VSS 10pF 8/09—Revision 0: Initial Version SERIAL INTERFACE RAB 20kΩ VIN AD5292 D × RAB (1024 – D) × RAB 1024 1024 8426-004 0 Figure 4. Logarithmic Gain Circuit ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN08432-0-4/13(C) Rev. C | Page 2 of 2 .

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