SIC JFET DEVICE MODELING
by
DAVID TIAN
Submitted in partial fulfillment of the requirements
For the degree of Master of Science
Thesis Adviser: Dr. Steven L. Garverick
Department of Electrical Engineering and Computer Science
CASE WESTERN RESERVE UNIVERSITY
January, 2011
CASE WESTERN RESERVE UNIVERSITY
SCHOOL OF GRADUATE STUDIES
We hereby approve the thesis/dissertation of
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candidate for the ______degree *.
(signed)______(chair of the committee)
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(date) ______
*We also certify that written approval has been obtained for any proprietary material contained therein. Table of Contents
List of Figures ...... ii
List of Tables ...... iv
Abstract ...... viii
Chapter 1. Introduction ...... 1
1.1 Silicon Carbide Integrated Circuits ...... 1
1.2 Review of High Temperature Electronics ...... 3
1.3 SiC JFET ...... 13
1.4 SPICE Modeling ...... 14
1.5 Objectives ...... 16
Chapter 2. Enhancements to DC Modeling ...... 18
2.1 Introduction ...... 18
2.2 Semi-empirical Model for Carrier Mobility ...... 19
2.3 Fermi Level and Ionized Carrier Concentration ...... 27
2.4 Optimized Parameter Set for 6H-SiC n-JFETs ...... 36
Chapter 3. SPICE and Convergence ...... 38
3.1 Introduction ...... 38
3.2 SPICE and Verilog-A ...... 40
3.3 Formation of the SPICE Matrix ...... 45
i
3.4 SPICE Solution Algorithms ...... 50
3.5 Convergence and an Updated SiC JFET Model ...... 55
Chapter 4. Capacitance Modeling in the Transimpedance Amplifier ...... 62
4.1 Introduction ...... 62
4.2 SiC JFET Small Signal Model ...... 62
4.3 Transimpedance Amplifier Small Signal Model ...... 68
4.4 Small Signal Open Loop Gain ...... 70
4.5 Closed Loop Transfer Function...... 72
4.6 Capacitance Modeling and Extraction of Fit Parameters ...... 77
Chapter 5. Conclusion ...... 83
Appendix A: Summary of Model Parameters ...... 85
Appendix B: MATLAB Code for Deriving Transimpedance Amplifier Transfer
Function ...... 88
Bibliography ...... 89
ii
List of Figures
Figure 1-1: Die photograph of CWRU SiC JFET integrated circuits...... 2
Figure 1-2: Illustration of intrinsic range in Si (from [10])...... 5
Figure 1-3: Simplified view of leakage paths in bulk CMOS (from [12]...... 7
Figure 1-4: Detailed view of leakage paths in bulk CMOS (from [9])...... 7
Figure 1-5: Constant-gm bias circuit (from [16])...... 10
Figure 1-6: Comparison between standard bulk CMOS and SOI CMOS device structures
(from [17])...... 11
Figure 1-7: Intrinsic carrier concentration vs. temperature for Si, SiC, and GaN (from
[11])...... 12
Figure 1-8: Comparison of 3/2-power vs. square law model for various gate overdrives
[24]...... 14
Figure 1-9: Four terminal SiC JFET...... 15
Figure 1-10: Graphical representation of Verilog-A implementation of SiC JFET...... 15
Figure 1-11: Peaking in the frequency response of the single-stage, single-ended
transimpedance amplifier [7]...... 16
Figure 2-1: Scattering mechanisms in semiconductors (from [28])...... 20
Figure 2-2: Calculated electron mobility as a function of temperature (Version 1 model).
...... 24
Figure 2-3: Electron mobility as a function of temperature (Version 2 model)...... 26
Figure 2-4: Energy band diagram for SiC showing multiple donor levels (from [7])...... 30
Figure 2-5: Temperature sweep of drain saturation current showing effects of incorrect
ionization rate (measured results vs. Version 1 simulation)...... 33
iii
Figure 2-6: Calculated ionization rate vs. temperature...... 33
Figure 2-7: Graphical method for determining Fermi level (from [10])...... 34
Figure 2-8: Donor ionization rate vs. temperature...... 35
Figure 2-9: Drain saturation current temperature sweep...... 36
Figure 2-10: IDS vs. VDS sweep using Version 2 SiC JFET model default parameter set, and comparison to measured data...... 37
Figure 3-1: SPICE small signal AC analysis flow...... 43
Figure 3-2: SPICE DC analysis flow...... 44
Figure 3-3: Linear resistive circuit...... 47
Figure 3-4: Resistor to be stamped ...... 49
Figure 3-5: Gauss’ algorithm for LU decomposition...... 52
Figure 3-6: Linearization of a diode (from [45])...... 54
Figure 3-7: Linear equivalent model for a diode...... 55
Figure 3-8: Screenshot showing adjustment of convergence parameters in PSPICE...... 58
Figure 3-9: Screenshot showing nonconvergence in the Version 3 Verilog-A SiC JFET
model...... 59
Figure 3-10: Screenshot showing convergence in the Version 3 Verilog-A SiC JFET
model...... 60
Figure 3-11: Screenshot showing DC sweep of a SiC JFET in the Version 3 model...... 61
Figure 3-12: Simulation of the transimpedance amplifier using the Version 3 SiC JFET
Verilog-A model...... 61
Figure 4-1: SiC JFET low-frequency small-signal model...... 62
Figure 4-2: SiC JFET high-frequency small-signal model with capacitors...... 63
iv
Figure 4-3: Separation of charge in a pn junction depletion region (from [46])...... 64
Figure 4-4: Plot of qj in a pn junction [46]...... 65
Figure 4-5: SiC JFET cross section and internal capacitances...... 66
Figure 4-6: Circuit model showing equal splitting of gate-channel capacitance...... 68
Figure 4-7: Transimpedance amplifier – block view...... 68
Figure 4-8: Transimpedance amplifier schematic...... 69
Figure 4-9: Open-loop transimpedance amplifier – block level view...... 70
Figure 4-10: Open-loop transimpedance amplifier – transistor level view...... 71
Figure 4-11: Small signal open loop gain simulation schematic...... 72
Figure 4-12: Closed-loop transimpedance amplifier – block level view...... 72
Figure 4-13: Closed-loop transimpedance amplifier – transistor level view...... 73
Figure 4-14: Simplified closed-loop small-signal model of the transimpedance amplifier.
...... 74
Figure 4-15: Bode plot of closed-loop transfer function...... 77
Figure 4-16: Illustration showing bottom-plate and sidewall capacitances in a FET [48].
...... 78
Figure 4-17: Transimpedance amplifier test setup...... 79
Figure 4-18: Measured and simulated (SPICE) transimpedance gain using abrupt-junction model...... 80
Figure 4-19: Measured and simulated (SPICE) transimpedance gain using linear-junction
model...... 80
Figure 4-20: Measured and simulated (SPICE) transimpedance gain using linear-junction model and including sidewall and gate overlap capacitance...... 81
v
Figure 4-21: Measured and simulated (SPICE) transimpedance gain using linear-junction model and including parasitics...... 82
vi
List of Tables
Table 1: Comparison of electronic properties of Si, Si, and GaN (from [18])...... 11
Table 2: Summary of JFET current voltage relationships (from [19], [20], [22], [10]). .. 13
Table 3: Comparison of Version 1 and Version 2 SiC JFET models...... 19
Table 4: Comparison of Version 2 and Version 3 SiC JFET models...... 39
vii
SiC JFET Device Modeling
Abstract
By
DAVID TIAN
This work involves modeling the SiC JFET developed at Case Western Reserve
University. First, a primer and background to the topic are given. Next, enhancements to
DC modeling are described, including the implementation of a more accurate mobility model and a parameter set optimized for the Case Western SiC JFETs. The issue of convergence in SPICE simulation is addressed and a new square-law Verilog-A model is described. Finally, capacitance models for the SiC JFET are verified in SPICE.
viii
Chapter 1. Introduction
1.1 Silicon Carbide Integrated Circuits
Silicon carbide (SiC) is a semiconductor material that is well suited for implementing high-temperature harsh environment electronics due to its outstanding electrical and physical properties: wide bandgap (2.9 eV for 6H-SiC), high-thermal conductivity, mechanical strength, chemical stability, and availability of high-quality wafers. Competing technologies are either incapable of operating at high-temperature
(Si, SOI), are significantly less developed than SiC (GaN, diamond, etc).
In particular, traditional electronic devices built on silicon substrates are inherently unsuitable for high-temperature operation, due to the narrow bandgap [1].
Recent studies show that traditional CMOS technology, utilizing the latest high- temperature circuit design principles and temperature-hardened packaging, can operate at temperatures up to 300°C, which is still insufficient for many desired applications [2].
Furthermore, silicon’s physical properties, such as a low Young’s modulus, make long- term operation and survival in the high pressure and harsh chemical environments that often accompany high-temperature operation impractical or impossible.
Past research has shown that JFET technology, which does not require a gate insulator, is promising for high-temperature operation in SiC. Technologies based on
MESFET or MOSFET devices tend to suffer excessive gate leakage or unstable threshold voltages, respectively [1]. Researchers at CWRU have successfully designed, fabricated, and tested a SiC JFET operational amplifier at 450°C [3].
1
As part of this effort, researchers at CWRU have developed a family of SiC JFET amplifiers for high-temperature sensor interface applications, as seen in Figure 1-1.
Included are differential amplifiers for use with sensors that produce a differential output
(such as a Wheatstone bridge type sensor) and transimpedaance amplifiers for use with sensors that produce a single-ended output (such as capacitiive or resonant type sensors).
The short-term operation of these amplifiers has been verified at temperatures of up to
600°C [4].
Figuure 1-1: Die photograph of CWRU SiC JFET integrated circuits. In the MEMS sensors area, researchers at CWRU and collaborators at UC
Berkeley have demonstrated MEMS strain sensors capable of extended operation at
300°C [5]. These sensors have been shown to function independently, but their functionality as part of an integrated microsystem has not yet been demonstrated.
SiC integrated circuit process technology is still in its infancy and control of process variations in key parameters, especially in epitaxial layer thicknesses (±10%
2
variation) and doping levels (±50% variation), is lacking [6]. An evaluation of forty SiC
JFET transistors found a mean pinch-off current of 0.41 mA with 0.1 mA standard deviation and a mean threshold voltage of 8.5 V with 1.0 V standard deviation [7].
A challenge in SiC circuit design then, is to design circuits that have high process variation tolerance. For example, the precise device matching that is desired in many modern analog circuit designs is difficult to achieve in SiC. Additionally, the SiC circuit designer is severely limited in currently available technologies due to lack of p-channel
SiC devices; at present, only n-channel SiC devices are available. Finally, the wide intended device operating temperature range (< 0°C to 600°C) and resulting changes to device characteristics further complicate circuit design [7]. By characterizing and modeling these challenges, this project will address fundamental issues in electronic device, process, and material design, in addition to the practical issues associated with high-temperature SiC sensor-circuit integration.
1.2 Review of High Temperature Electronics
Challenges facing transistor performance at high-temperature
A study of semiconductor device physics shows that three critical phenomena
affect transistor performance at elevated temperatures. These are i) increased junction
leakage current resulting from increased intrinsic carrier concentration, ii) variations in
threshold voltage, and iii) degradation of carrier mobility [8]. Understanding and
modeling these effects is critical towards the successful design of high-temperature
electronics.
3
The fundamental challenge to the operation of electronics at high-temperature is
excessive intrinsic carrier concentration generation. As temperature increases, electrons
gain more thermal energy and intrinsic carrier concentration will increase exponentially:
Eg nNNiCV exp 2kT 3/2 Eq. 1-1 2mmm0 de dh 23/2 Eg 2exp22MTC hm0 2 kT
3/2 15m 2 3/2 Eg 4.9 102 MTC exp mkT0 2
where NC is the effective density of states in the conduction band, NV is the effective
density of states in the valence band, Eg is the bandgap voltage, k is the Boltzmann constant, T is the temperature, m0 is the free-electron mass, h is Planch’s constant, mde and mdh are the density-of-state effective masses for electrons and holes, respectively, MC is the number of equivalent minima in the conduction band, and m is the density-of-
state average effective mass, given by [9]
1/2 mmm de dh Eq. 1-2
From Eq. 1-1, the temperature dependence of intrinsic carrier concentration can be
derived as [9]
3/2 3/2 Eg nmTi exp 2kT Eq. 1-3
or
4
3 3 E log e log n log m log T g i 2 2 2kT Eq. 1-4
The intrinsic temperature, Ti , of a semiconductor is defined as the temperature at which the concentration of thermally generated intrinsic carriers equals, and eventually exceeds, the concentration of dopant carriers; the range of temperatures over which this occurs is called the “intrinsic range” and has a slope of Eg (Figure 1-2)).
Figure 1-2: Illustration of intrinsic range in Si (from [10]). Field effect transistors, such as the JFET and MOSFET, have p-n junctions whose doping levels and biasing are varied to control flow of current in the device. In a p-n junction, current is described by [11]:
n D W i p qVA /kT qVA /2 kT Eq. 1-5 I qAni e 1 e 1 N 2 D
2 here A is the area of the p-n junction (cm ), VA is the voltage applied, ND is the n-type
-3 doping concentration (cm ), W is the width of the junction depletion region (cm) at VA,
5
2 Dp is the hole diffusion constant (cm /s), and τ is the effective minority carrier lifetime
(seconds). Under reverse bias (i.e. negative VA), and at temperatures below 1000°C, the
qV/ kT exponential e A 1 terms are dominated by -1, since eqVA / kT is much less than 1 .
This results in the following expression for current through a reverse-biased p-n junction
[11]:
n D W IqAn i p i N 2 Eq. 1-6 D
where A, VA, ND, W, Dp, and τ are the same as in Eq. 1-5. Because this expression describes the current through a reverse-biased p-n junction, it is said to describe the leakage current of the p-n junction. Eq. 1-6 shows that p-n junction leakage current is tied to intrinsic carrier concentration, which increases exponentially with temperature.
A simplified view of silicon CMOS technology, shown in Figure 1-3, shows that p-n junction leakage occurs primarily along two paths: drain-to-substrate and drain-to- source. A more detailed analysis, such as that shown in Figure 1-4, shows subthreshold current Isubth dominates the drain-to-substrate path, while generation current Igen and diffusion current Idiff dominate the drain-to-substrate path.
2 WkTni expkT S / q Iqsubth n 1exp kTVq D / LqN Eq. 1-7 A S x S where ni is the intrinsic carrier concentration, μn is the mobility, W is the width, L is the length, NA is the doping concentration, VD is the drain voltage, and ψS is the surface potential.
6
qn i Eq. 1-8 Igen volume( depletionregion) e where ni is the intrinsic carrier concentration and τe is the generation lifetime.
2 De ni Eq. 1-9 Idiff area (device) e NA where De is the diffusion constant, τe is the generation lifetime, ni is the intrinsic carrier concentration, and NA is the doping concentration.
For temperatures exceeding approximately 200°C, eenough intrinsic carriers are generated to cause p-n junction leakage currents to becomme large enough to disrupt device performance. In particular, channel (drain-to-source) current in the transistor can no longer be controlled by voltage applied to the gate. Since this violates the defining principle of the field effect transistor, temperature induced device failure is considered to have occurred [1].
Figure 1-3: Simplified view of leakage paths in bulk CMOS (from [12].
Figuure 1-4: Detailed view of leakage paaths in bulk CMOS (from [9]).
7
In MOS devices that dominate the modern electronics industry, the temperature dependence of the surface inversion potential causes threshold voltage to decrease as temperature increases:
dV d 1 qN TB2 sA Eq. 1-10 dT dT CiB
ET 0 d B 1 g Eq. 1-11 B T dT T 2 q
For integrated MOS transistors, threshold voltage variation with temperature is between -
2 mV/°C and -4 mv/°C, depending on gate oxide and doping [12].
Extended operation at high-temperature can also cause threshold voltage instability. At high-temperature and sufficient applied gate voltage, mobile carriers that enter the gate oxide can leave behind trapped charges and damage the oxide- semiconductor interface. Over time, this damage to the gate oxide can induce changes in threshold voltage [5].
Changes in temperature also influence the mobility of charge carriers in a semiconductor. At high-temperatures, scattering caused by increased phonon concentrations in the semiconductor results in decreased electron and hole mobility.
Measurements of mobility by Hall Effect sensing and infrared photocarrier radiometry indicate the following expression for temperature dependence of electron and hole mobility in silicon [13]:
8
cm 2 (TT ) (2.1 0.2) 1092.50.1 , for electrons Eq. 1-12 n Vs
cm 2 ()TT (2.30.1)1092.70.1 , for holes Eq. 1-13 p Vs
Approaches to high-temperature electronics
Approaches to high-temperature electronics attempt to address the above three phenomena through various means. Each approach has its advantages and disadvantages, depending on the temperature range of operation.
The most desirable high-temperature electronics solution is to use circuit techniques to compensate for the semiconductor/device effects described above, while still using silicon CMOS technology. Ideally, this would allow the use of familiar and relatively low cost fabrication processes, while retaining circuit performance at high- temperature. These techniques include zero-temperature coefficient gate biasing [14], leakage current cancellation [8], substrate bias feedback [15], and constant-gm biasing
[2]. Jackson Harvey, a MS student at CWRU, found complementary diode leakage current cancellation to be ineffective in a MOSIS/Orbit 2μm CMOS process, but successfully implemented temperature adaptive biasing in single-ended operation amplifier operational from 25°C to 250°C [8]. More recently, Xinyu Yu, a PhD student at CWRU, successfully designed high-temperature data acquisition electronics in an AMI
1.5μm bulk CMOS process functional up to 300°C using many of the techniques described above [16]. Some of these techniques, such as the constant-gm biasing circuit shown in Figure 1-5 that generates a bias current that is inversely proportional to
9 mobility, have applications beyond Si CMOS. Circuit techniques geneerally only enable high-temperature electronics to operate up to 200°C; in limited cases though, 300°C operation can be achieved [1].
Figure 1-5: Constant-gm bias circuit (from [16]). In silicon on insulator (SOI) technology, silicon circuits are built on top of an insulating buried oxide layer (BOX), which provides electrical isolation that reduces junction leakage current by about one hundred times vs. conventional Si technology. SOI device also experience smaller threshold voltage shifts due to changes in temperature.
However, because it is still silicon, SOI still suuffers from the problems associated with intrinsic carrier concentration and gate oxide reliability at high-temperature. Therefore, the maximum operating limit of SOI MOSFET technology is still only about 300°C. SOI and CMOS technologies are already used to fulfill electrronics needs at temperatures below 300°C, with CMOS dominating the lower range [9].
10
Figure 1-6: Comparison between standard bbulk CMOS and SOI CMOS device structures (from [17]). Wide bandgap semiconductors, such as silicon carbide, have promising applications for temperatures greater than 300°C. Table 1 compares the electronic properties of Si with those of two leading wide bandgap semiconductors, SiC and
AlGaN. Fundamentally, the larger bandgap of SiC meanss that fewer intrinsic carriers will be generated as temperature increases, meaning that junction leakage currents will not cause device failure at high-temperatures.
Table 1: Comparison of electronic properrties of Si, Si, and GaN (from [18]).
11
Figure 1-7: Comparison between standard bbulk CMOS and SOI CMOS device structures (from [17]).
Figure 1-7: Intrinsic carrier concentration vs. temperature for Si, SiC, and GaN (from [11]]).
12
1.3 SiC JFET
Silicon carbide (SiC) is considered the most promising semiconductor for implementing electronics for operation in the 3000°C to 600°C range. The wide bandgap of SiC (3.3eV for SiC vs. 1eV for Si) mitigates the detrimental high-temperature effects described in section 1.2 that would cause connventional Si CMOS electronics to fail.
Furthermore, the excellent mechanical properties of SiC make it capable of withstanding the harsh environments that often accompany high-temperaature electronics applications.
Recently, advances in SiC crystal quality and Ti//TaSi2/Pt ohmic contacts that are stable at high-temperature have enabled n-channel SiC JFET prototyppe circuits to be realized [1].
Modeling of the SiC JFET has been carried out by Zappe [19], McLean [20], Ruff
[21], and Taki [22] using the square-law model (“Schichman-Hodges”), 3/2-power law, and hyperbolic tangent function (“empirical model”), respectively. A comparison of all three models is shown in Table 2. The empirical model relies heavily on curve fitting and is difficult to implement accurately for a technology wiith as much process variation as the SiC JFET process.
Table 2: Summary of JFET current voltage relationships (from [19], [20], [22], [10]).
13
The 3/2-power law model is preferred because it is accurate for both large and small gate overdrives, and therefore is suitable for both analog and digital circuit designs.
Analog circuits typically operate with a low VGS-VT, and as shown in Figure 1-8, the choice of square-law or 3/2-power law does not have a significant impact for gate voltages close to threshold. Digital circuits, however, can operate with VGS-VT varying from zero to maximum, and therefore benefit from the improved accuracy of the 3/2- power model [23]. Figure 1-8 shows a comparison of the 3/2-power law and square law models for various gate overdrives.
Idsat vs. VGS
8.0E-05
7.0E-05
6.0E-05
5.0E-05
4.0E-05 IDSAT 3.0E-05
2.0E-05
1.0E-05
0.0E+00 -6 -5 -4 -3 -2 -1 0 1 2 VGS 3/2-power
Figure 1-8: Comparison of 3/2-power vs. square law model for various gate overdrives [24].
1.4 SPICE Modeling
Another model by Chompoonoot Anupongongarch at CWRU emphasized implementing the 3/2 power model in SPICE, characterizing the temperature dependence of key device parameters, and adding the body terminal to account for the body effect
[24].
14
The four-terminal SiC JFET, shown in Figure 1-9, has been implemented in
Verilog-A as a set of nodes and branches, with equations describing the relationships between them. These equations, for instance, can be used to describe current-voltage and capacitance-voltage relationships. Cadence Virtuoso is then used to link the Verilog-A model to the Spectre circuit simulator, which is a proprietary version of SPICE. Figure
1-10 shows a graphical representation of the nodes and branches in the Verilog-A model.
D
RD
IDS
G B VDS VDS, external
VGSG VBS
RS VGS, external
S
Figure 1-9: Four terminal SiC JFET.
Figure 1-10: Graphical representation of Verilog-A implementation of SiC JFET.
15
The Verilog-A code summarized in Figure 1-10 provides the general framework for which 3/2-power model equations, among others, are implemented. A variety of physics, device, process, and geometric parameters are computed for use in the model equations. A key consideration in earlier work was the accurate calculation of these parameters with respect to variation in tempperature. A complete listing of these parameters and formulas for calculating them can be found in Appendix A.
1.5 Objectives
The present SiC JFET Verilog-A model suffers from convergence problems and inaccuracy in AC and transient simulations, stemming from the lack of accurate capacitance models. The frequency response of the single-stage, single-ended transimpedance amplifier, for example, shows peaking that is unaccounted for in the current JFET model (Figure 1-11). Issues with modeling the transient response of logic gates have also been documented.
Figure 1-11: Peaking in the frequency response of the single-stage, single-ended transimpedance amplifier [7].
16
This thesis builds upon the work referenced, and will emphasize 1) characterizing the
C-V characteristics of the SiC JFET, 2) verifying capacitance models, 3) refining the
SPICE implementation, and 4) verifying the accuracy of AC and transient simulations.
17
Chapter 2. Enhancements to DC Modeling
2.1 Introduction
The primary application for SiC integrated circuits is in environments that experience large temperature variations, such as inside an aircraft turbine engine or an automobile engine compartment. To enable accurate simulation, a SiC circuit simulator and accompanying device models must accurately model devices and circuits across the entire intended temperature range of operation. For SiC integrated circuits, temperature can vary from below 0°C to as high as 600°C.
This section presents the theory, implementation, and simulation results of three enhancements to the DC modeling abilities of the Verilog-A SiC JFET model, first presented in [24]. The first enhancement is the implementation of a semi-empirical model for carrier mobility that better matches mobility data from literature. The second is a method for approximating carrier concentrations in Verilog-A. Finally, the third enhancement is a default parameter set that is optimized for a typical SiC JFET, producted at CWRU [7]. These enhancements are included in “Version 2” of the SiC
JFET model and summarized in Table 3.
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Version 1 Version 2
3/2-power law 3/2-power law IDS vs. VGS equation
Verilog-A Verilog-A Implementation
Four (drain, gate, Four (drain, gate, source, bulk) Number of terminals source, bulk)
Empirical Semi-empirical (Mnatsakanov [26]) Mobility model (Caughey-
Thomas [25])
None (user input; Calculated - based on polynomial fit Carrier concentration does not vary to Matlab data calculation with temperature)
None Optimized for fit to typical JFET Default parameter set from DARPA TAPS Phase III
Table 3: Comparison of Version 1 and Version 2 SiC JFET models.
2.2 Semi-empirical Model for Carrier Mobility
Carrier mobility in a semiconductor changes with temperature and is determined by the interaction of carriers (holes and electrons) with a number of obstacles, summarized in Figure 2-1 [27]:
Phonons: acoustical and optical
Ionized impurities
Neutral defects
Surface and interfaces
Other carriers
19
Due to the complexity in modeling all of these effects together, mobility modeling is typically divided into four regions: 1) low-field bulk behavior, 2) high-field bulk behavior, and 3) inversion layers [28]. Low-field behavior is based on the assumption that the electric field applied is weak enough for the electron drift velocity to be proportional to electrical field and mobility:
E. Eq. 2-1
At high electric fields, electron velocity is no longer directly proportional to applied electric field, and the expression for mobility must adjust aaccordingly [29]. Likewise, mobility is strongly affected by the additional scattering that occurs in an inversion layer.
Figure 2-1: Scattering mechanisms in semiconductors (from [28]).
Models for carrier mobility are generally grouped into one of three categories: physics-based, semi-empirical, and empirical. Physics-based models are based entirely on fundamental physical parameters. A weaknesss of physics-based models is that they often do not correlate well with measured data, dduue to the fact that it is typically not possible to account accurately for all practical effects. At the other end of the modeling spectrum lie empirical models, such as the Caughey-Thomas equation, which are able to 20 correlate well with measured data because they are explicitly fit to data. A weakness of empirical models, though, is that because they have no grounding in fundamental physics, they do not account for effects that are not fit. Semi-empirical models, such as the Mnatsakanaov equation, aim to reconcile physics-based models with empirical models by allowing more leeway in physics-based parameters to provide better correlation with measured data.
A common physics-based expression for mobility is [30]:
qnn n q , Eq. 2-2 me 3kTme where τn is the relaxation time, λn is the mean free path, and me is the conductivity effective mass. As temperature increases, so do the number of lattice vibrations (i.e., increased phonons). This results in lower relaxation times and lower mean free paths, thereby causing decreased mobility.
A more complete expression for mobility can be obtained by independently analyzing excitations resulting from phonon and ionized impurity interactions and combining their effects with the Matthiessen rule:
1 11 . Eq. 2-3 phonon ion
The mobility dependence on interactions with phonons in the lattice is given by
81 qC 1 phonon 2*5/2 3/2 *5/23/2, Eq. 2-4 3()Emds c kT m c T and the mobility dependence on interactions with ionized impurities is given by [10]
21
2 1 6423/2 (2kT ) 12 kT T 3/2 ss phonon 3 *1/2ln 1 2 1/3 *1/2 . Eq. 2-5 Nqm qN Nm Ic I Ic
Past work in empirical SiC carrier mobility modeling has been focused primarily on the effects of changing doping concentration. In the Caughey-Thomas mobility model, data is fitted to an equation of the form
0 min , N Eq. 2-6 1 Nref where µ0 is the difference between the maximum and minimum expected mobility, Nref is a reference doping concentration, and α is an empirically determined parameter [25].
Mobility modeling has however, been overwhelmingly slanted towards Si, the dominant material in modern electronics. A challenge in SiC device modeling is to combine established techniques developed in Si research with empirical results for SiC. The need for mobility modeling through a wide temperature range, necessary for intended SiC
JFET applications, presents an additional challenge, because the dominant scattering mechanism may vary with large changes in temperature.
Ruff, et al published a comprehensive effort in SiC modeling, including a SiC carrier mobility model based on the Caughey-Thomas equation [21]. The temperature dependence of the mobility parameter is modeled by
T (TK ) (300 ) , Eq. 2-7 300K
22 where γ is chosen to provide the best fit to empirical data. The complete expression for mobility as a function of both doping concentration and temperature is essentially the
Caughey-Thomas equation extended to SiC [21]:
max min T nn min . nn n Tnom N Eq. 2-8 1 D Ng
More recent work in SiC carrier mobility modeling by Roschke, et al incorporated the Caughy-Thomas equation of Eq. 2-6 to experimental data for the 4H, 6H and SiC polytypes [29]. Based on measurements done by Muench and Pettenpaul [31] and by
Khan and Cooper [32], Roschke was able to determine the temperature dependence of the key parameters used in the empirical method of calculating mobility, as follows:
2.5 T Eq. 2-9 max 420 300K
0.5 T Eq. 2-10 min 30 300K
2.5 17 T Eq. 2-11 NNref g 610 300K
0.5 T 0.8 , Eq. 2-12 300K where µmax, µmin, Nref, and α are all fitting parameters for the Caughey-Thomas equation.
23
In Version 1 of the SiC JFET Verilog-A model, the modified Caughey-Thomas from Ruff’s work (Eq. 2-8) was implemented. Results from this calculation are used to calculate a number of material and device parameeters, including the pinch-off current and sheet resistance. Past work has shown the mobility of electrons in 6H-SiC to be a maximum of approximately 380 cm2/(V·sec) at room tempeerature [21]. The Version 1
SiC JFET model, using the Caughey-Thomas equation gives mobility levels significantly below what might be expected from the accepted measured data: 348 cm2/(V·sec) at room temperature.
Figure 2-2: Calculated electron mobility as a function of temperature (Version 1 model).
Mnatsakanov, et al propose a semi-empirical model ffor low-field mobility in SiC that is potentially better suited for simulation over a large temperature range [33]. The
Mnatsakanov equation is derived from the Caughey-Thomas equation and accounts for both the dominance of ionized impurity scattering at low temperatures and the dominance of lattice scattering at higher temperatures. At low temperatures, ionized impurity scattering is the primary effect and causes mobility to increase with temperature. At 24 high-temperatures, lattice (phonon) scattering is dominant, and causes mobility to decrease with temperature. Whereas the Caughey-Thomas equation only describes carrier mobility in the temperature regime where it decreases with temperature, the
Mnatsakanov equation can adequately describe carrier mobility for a wider range of temperature, where different scattering mechanisms are dominant [26].
Matthiessen’s rule state that in metals, the total resistivity is the sum of the resistivity due to thermal agitations in the lattice and imperfections in the crystal. For semiconductors, this is adapted to give
11 1 . Eq. 2-13 lattice lattice impurities
At low doping concentrations and room temperature, lattice scattering is dominant such that
Eq. 2-14 max lattice.
Thus, using the temperature dependence of mobility established in Eq. 2-7,
T Eq. 2-15 max ()TT lattice (0 ) . T0
After applying Matthissen’s rule, one can arrive at
N 1 Ng max Eq. 2-16 ionized max 1. max min N N g
Rearranging and applying Eq. 2-10,
25
N max min lattice . Eq. 2-17 N 1 / 1 N / N g g ionized lattice
A complete expression for mobility can be derived by applying the temperature dependence formula of Eq. 2-11 to µlattice and µionized:
BT()(TT/) i 0 Eq. 2-18 (N,)T max (T0 ) 1( BN)(/TT0 )
(N /)N BN() minmaxg . Eq. 2-19 max min
When implemented in Verilog-A as parrt of the Version 2SiC JJFET model, the
Mnatsakanov equation gives values for carrier mmobility that are closer to experimental data: 375 cm2/(V·sec) at room temperature and 319 cm2/(V·sec) at 50°C.
Figure 2-3: Electron mobility as a function of temperature (Version 2 model).
26
2.3 Fermi Level and Ionized Carrier Concentration
Like mobility, carrier concentration is highly susceptible to changes in temperature. While it is straightforward to model the variation in intrinsic carrier concentration with temperature (Eq. 1-1 and Figure 1-2), modeling the total ionized impurity concentration is considerably more difficult. Many key DC performance parameters, including the pinch-off current (IPP) and saturation current (IDSAT), ultimately depend on the number of ionized carriers
Eq. 2-20 nionN D,
where ion is the ionization rate and ND is the activated doping concentration in the channel. The percentage of impurities introduced into a semiconductor crystal that are ionized (the ionization rate) is strongly dependent on the temperature. As temperature increases, so will the donor ionization rate, as confirmed by the following expression:
ND 1 ionization rate , Eq. 2-21 ND EEFD 1exp gd kT
where gD is the ground-state degeneracy of the donor impurity level, EF is the Fermi energy level, ED is the donor energy level, k is the Boltzmann constant, and T is the temperature. The ground-state degeneracy gD is equal to 2 for electron donors because
1 1 each donor level can accept one electron with spin or . 2 2
27
In silicon, the narrow bandgap assures that a high ionization rate will occur even at low and medium temperatures, consistent with Eq. 2-21. With the assumption then that the ionization rate is 1 (i.e., 100% donor ionization), the charge neutrality law becomes
Eq. 2-22 nN A pND.
By combining this with the mass-action law
2 Eq. 2-23 np ni ,
and assuming NNDA , a simplified expression for the number of carriers (electrons) in an n-type semiconductor can be obtained:
1/2 2 NNDA NN DA 2 Eq. 2-24 nn i , 22
where ND is the donor concentration, NA is the acceptor concentration, and ni is the intrinsic carrier concentration. With the further assumption that the donor concentration far exceeds the intrinsic carrier concentration (i.e., NNDAi n), Eq. 2-24 reduces to
n 2 n i , Eq. 2-25 NNDA
thereby yielding a simplified expression for the carrier concentration. This expression accurately describes the carrier concentration in the “saturation region” shown in Figure
28
1-2, which holds valid over a wide temperature range when ionization rate is high because of its narrow bandgap, the saturation region in silicon extends from approximately 10K to 1000K [10].
In wide bandgap materials such as SiC, the larger bandgap means that donor ionization cannot be assumed to be 100% throughout the intended operation temperature range. At room temperature for instance, donor ionization in SiC is expected to be less than 40% [21]. Carrier concentration must be directly calculated as a function of temperature to enable accurate circuit and device simulation over a wide temperature range. Unlike silicon, simple approximations for carrier concentrations in SiC are not possible due to the large variation in donor ionization with temperature.
Hall Effect and infrared absorption measurements performed by Suttrop, et al in
1992 suggested that two donor ionization levels are active in 6H-SiC [34]. Further studies by McLean, et al in 1995 verified that Suttrop’s two-donor ionization level model enables accurate simulation of 6H-SiC buried-gate, n-channel, depletion-mode JFETs
[20]. Since these JFETs are functionally similar to those used at CWRU, McLean’s work has provided a foundation for subsequent modeling work. The two-donor ionization level model, shown in Figure 2-4, has a shallow donor level of 85 meV associated with hexagonal sites and a deeper donor level of 125 meV associated with cubic sites.
29
Figure 2-4: Energy band diagram for SiC showing multipple donor levels (from [7]).
Both the lower and higher levels are necessary to accurately describe carrier ionization over a broad temperature range; the shallow donor level (85 meV) describes carrier activation for temperatures below room temperature, while the deeper donor level
(125 meV) describes carrier activation for temperatures greater than room temperature
[20].
Taking these multiple donor levels into account, the charge neutrality law (Eq.
2-22) becomes
nN D1 NpD2 , Eq. 2-26
ା where n is the total number of carriers, ܰଵ is the number of ionized carriers associated
ା with the lower donor level, ܰଶis the number of ionized carriers associated with the high donor level, and p is the number of holes. The electron, hole, and ionized carrier densities are described by
30
EE Fi Eq. 2-27 nn i exp , kT
EE iF Eq. 2-28 pn i exp , kT
1 Eq. 2-29 NNDD111,and 1 EEDF1 1exp gkT
1 Eq. 2-30 NNDD221, 1 EEDF2 1exp gkT where n is the concentration of electrons, p is the concentration of holes, ni is the concentration of intrinsic carriers, Ei is the intrinsic energy level, EF is the Fermi energy
ା level, ܰଵis the number of ionized carriers associated with the lower donor level, ND1 is
ା the number of donors in the lower donor level, ܰଶ is the number of ionized carriers associated with the high donor level, ND2 is the number of donors in the high donor level,
ED1 is the lower energy donor level, ED2 is the high energy donor level, g=2 is the ground-state degeneracy constant, k is the Boltzman constant, and T is the temperature.
Thus, the charge neutrality equation (Eq. 2-26) can be rewritten as
EE 1 Fi nNiDexp1 1 kT 1 EEDF1 1exp gkT Eq. 2-31 1 EE iF NnDi2 1exp. 1 EEDF2 kT 1exp gkT
31
Earlier work has shown that the concentration of donors in two levels to be at a 1:2 ratio
1 2 [20], i.e, NN and NN , where NNN . D1 3 D D2 3 D DD12 D
To determine the ionized carrier concentration as a function of temperature, Eq.
2-31 must be solved for EF - Ei. In version 1 of the SiC JFET model, Matlab was used to find EF - Ei. The resulting Fermi level is substituted back into the expression for electron density (Eq. 2-27) to find the ionized carrier concentration, n, and the ionization rate is
n ionization rate ion . Eq. 2-32 ND
In circuit simulations using Version 1, the user would manually input this Matlab calculated ionization rate into the model. Therefore, the Version 1 SiC JFET model is not capable of dynamic temperature simulation such as a temperature sweep. Instead, the user must stop the simulation, run Matlab to compute a new ionization rate, and manually enter the new rate into the model for every different temperature.
A drain current (IDS) vs. temperature (T) sweep from 0°C to 600°C for a 100-µm by 100-µm SiC JFET from wafer CR0975-10, die R6C5, is shown in Figure 2-5.
Because the Version 1 SiC JFET model is not able to dynamically calculate ionized carrier concentration and ionization rate, the room temperature ionization rate is used through the entire temperature simulation range. As can be seen, the Version 1 model is able to closely approximate the drain saturation current at room temperature. As temperature increases, however, the model fails: the rise in ionized carrier concentration and ionization rate is unaccounted, thereby leading to unrealistically low drain saturation current.
32
Figure 2-5: Temperature sweep of drain saturation current showing effects of incorrect ionization rate (measured results vs. Veersion 1 simulation).
As shown in Figure 2-6, the ionization rate of carriers in SiC undergoes a large variation, particularly between room temperature and 200°C, when ionization rate increases from 39% to 90%.
Figure 2-6: Calculated ionization rate vs. temperature.
33
The calculation of carrier concentration ultimately comes down to calculating the
Fermi level of SiC for the doping concentrations given. Several methods exist for how this can be accomplished. The first method, as used in the Version 1 model, involves using an outside program such as Matlab or Mathematica, to calculate the Fermi level from Eq. 2-31. This method is not ideal because it involves a great deal of effort on the part of the user and makes temperature sweep simulations difficult and time consuming to perform.
A second graphical method, outlined in Figure 2-7, involves pllotting the donor concentration ND and the carrier density n, and determining where they intersect to find
Fermi level (EF). Like the first method, this method cannot be implemented in Verilog-
A, and is thus impractical for this work.
Figure 2-7: Graphical method for determining Fermi level (from [10]). A third method would involve implementing equation solving algorithms directly in Verilog-A. Theoretically, the Newton-Raphson methood and Gaussian elimination
34 could be implemented to find the zeros of the charge neutrality expression, from which the Fermi level could be extracted and carrier concentration and ionization rate calculated. Verilog-A has robust programming flexibility, and this method wouuld be possible. The trade-offs however, would be enormously decreased simulation speed, increased model complexity, and potential convergence issues.
A fourth method for calculating carrier concentration entails performing a polynomial curve fit to the ionization rate resultts from Matlab calculation, as shown in
Figure 2-8. The resulting polynomial could be implemented as an equation in Verilog-A to calculate the carrier concentration and ionization rate as a function of temperature.
This method is applicable to any SiC device and all dopoing levels providing that donor levels are unchanged.
Figure 2-8: Donor ionization rate vs. temperature.
The fourth-order polynomial obtained from the curve fit was implemented in the
Version 2 SiC JFET model. As shown in Figure 2-9, the Version 2 SiC JFET model with
35 dynamic ionized donor concentration and ionization rate calculations approximates actual measured data much more closely than the Version 1 model.
Figure 2-9: Drain saturation current temperature sweep.
2.4 Optimized Parameter Set for 6H-SiC n-JFETs
The original Verilog-A SiC JFET model (“Version 1”) provides a framework for accurate SiC IC simulation, but required extennsive modification of model parameters.
The default parameters in the model do not accurately reppresent the latest SiC JJFET technology at CWRU. Version 2 of the Verilogg-A SiC JFET model, proposed here, is based on the device parameters extracted from a “typical device” from Phase III of the
DARPA SiC TAPS program to provide accurate modeling of 6H-SiC JFET IC’s.
A default parameter set has now been extracted from a typical JFET (100µm x
100µm, row 5 column 4) fabricated as part off the DARPA TAPS Phase III program.
36
This parameter set has been implemented in Version 2 of the SiC JFET model to enable accurate simulations of current technology. The results of an IDS vs. VDS sweep are shown in Figure 2-10.
Figure 2-10: IDS vs. VDS sweep using Version 2 SiC JFEET model default parameter set, and comparison to measured data.
37
Chapter 3. SPICE and Convergence
3.1 Introduction
A key step in circuit simulation is convergence on the DC operating point, which is the set of node voltages and branch currents for which a circuit satisfies Kirchoff’s voltage law (KVL), Kirchoff’s current law (KCL), and relevant branch constitutive equations (BCE’s). In SPICE, convergence is typically achieved through an iterative process known as the Newton-Raphson method. Failure to converge on an operating point, known as nonconvergence, has been a challenge in circuit simulation since its earliest days, and remains so with SiC JFET integrated circuit simulation.
This chapter covers the processes and algorithms through which convergence can be achieved in SPICE, and then applies this knowledge to develop an updated model for the
SiC JFET that does not suffer from the convergence issues that have affected previous models. First, a general overview of the SPICE simulation and Verilog-A compact modeling process is given. Next, the “stamping” method by which SPICE generates a system of equations from a circuit netlist or schematic is presented. The algorithms used to determine the DC operating point are then summarized. Finally, an updated SiC JFET
Verilog-A model (Version 3, Table 4) that overcomes the convergence issues of past models is described.
38
Version 2 Version 3
3/2-power law Square law IDS vs. VGS
equation
Verilog-A Verilog-A Implementation
Yes No Convergence
Issues
Four (drain, Four (drain, gate, source, Number of gate, source, bulk) terminals bulk)
Semi-empirical Semi-empirical Mobility model (Mnatsakanov (Mnatsakanov [26])
[26])
Empirical - Empirical - based on Carrier based on polynomial fit to concentration polynomial fit measured data calculation to measured
data
Optimized for Optimized for fit to Default fit to typical typical JFET from TAPS parameter set JFET from
TAPS
Table 4: Comparison of Version 2 and Version 3 SiC JFET models.
39
3.2 SPICE and Verilog-A
SPICE (Simulation Program with Integrated Circuit Emphasis) has been the standard circuit simulation tool since the 1970’s, when it was developed in the
Electronics Research Laboratory at the University of California, Berkeley. Since then, the tool has undergone many changes, eventually evolving to SPICE2, SPICE3, and numerous commercial versions, including Cadence Spectre, PSPICE, and LTSpice. All of the aforementioned commercial versions of SPICE are used in this work.
Each revision of SPICE has brought about improvements in speed, accuracy, stability, and usability. SPICE2, introduced in 1975 and the basis of most modern circuit simulators, introduced modified nodal analysis (MNA), memory management, and significant improvements to device modeling [35]. SPICE2 better accounted for device geometries in FETs and allowed for the choice of three levels of modeling: a Level 1 square law model, a Level 2 model that included second order effects, and a Level 3 semi-empirical model [36]. SPICE3, introduced in the 90s, was the first version of
SPICE written in C and had a new architecture, making it easier to add new components and models [35].
Most commercial implementations of SPICE are based on SPICE2, and often feature a combination of revised algorithms and integration with a graphical user interface, schematic capture, models and libraries. Spectre is a commercial version of
SPICE from Cadence Design Systems, and part of the Cadence Design Suite that is widely used in the IC design industry. Spectre represents a substantial improvement over the original SPICE, in that it features enhanced algorithms and improved reliability. Due
40 to these modifications, Spectre is not only considered more accurate and reliable than
SPICE, but is also 3-5 times faster [37].
In addition to Cadence Spectre, this work also uses Cadence Orcad PSPICE and
Linear Technology LTSpice IV. Both PSPICE and LTSpice are implementations of
SPICE commonly used in universities and industry.
Verilog-A is a programming language based on Verilog-HDL that enables modeling and simulation of analog components for simulation in SPICE. The five primary uses of Verilog-A are [38]:
1. To model components that are not typically not available in SPICE
2. To create test benches that more accurately simulate the circuit under
testing conditions
3. To accelerate simulation by replacing complex transistor level blocks with
behavioral models
4. To verify mixed signal systems (when combined with Verilog-HDL)
5. To enable top-down design
Verilog-A will be used exclusively for device modeling in this work. SPICE device models are written in either FORTRAN or C code and are difficult to modify and recompile. By using Verilog-A, new devices such as the CWRU depletion mode SiC n-
JFET can be easily implemented and simulated in SPICE.
Fundamentally, a circuit simulation program such as SPICE must contain five key components: 1) a parser to interpret a given netlist or schematic, 2) an engine that builds
41 the system of equations describing the circuit, 3) algorithms to solve for unknowns in the matrix, and 4) ways to display the output.
SPICE is capable of the following forms of analysis [39]:
DC analysis – to determine the operating point of a circuit and/or generate DC
transfer curves
AC small-signal analysis – to determine circuit behavior as a function of
frequency
transient analysis – to determine circuit behavior as a function of time
pole-zero analysis – to determine the poles and/or zeros of a small-signal AC
transfer function
small-signal distortion analysis – to determine the steady-state harmonic and
intermodulation products for small signal inputs
sensitivity analysis – to determine the DC operating point sensitivity or AC
small signal sensitivity of output variables with respect to circuit variables;
note that these circuit variables can include model parameters
noise analysis – to determine the contributions of device noise to the output
voltage of the circuit
For this work, DC analysis and AC analysis are emphasized. Whichever form of analysis is chosen, the DC operating point must be determined first to allow for linearization of nonlinear circuit elements (such as transistors). In the AC small signal simulation (Figure
3-1), for instance, the DC operating point (Figure 3-2) must be established before any further analysis can proceed.
42
Figure 3-1: SPICE small signal AC analysis flow.
43
Figure 3-2: SPICE DC analysis flow.
44
3.3 Formation of the SPICE Matrix
SPICE interprets a circuit as a network of nodes, elements, and branches. A DC solution consists of currents through the branches and voltages at the nodes. Before any analysis can be performed, however, SPICE must translate a circuit given by a schematic or netlist to a mathematical form that can be solved. A parser is first used to extract the components in the circuit and their placement. Kirchoff’s voltage law (KVL), Kirchoff’s current law (KCL), and branch constitutive equations (BCE’s) are then used to define the current vs. voltage relationships that form the system of equations describing the circuit.
A circuit simulation program can use one of two methods to translate circuit data from the parser to a matrix of equations: sparse tableau analysis (STA) [40] or nodal analysis [41].
Sparse tablaeau analysis consists of three steps [42]:
1) Writing KCL as Ai 0 , where A is the reduced incident matrix and i is a
vector of all branch currents.
2) Writing KVL as uAv T , where u is the vector of all branch voltages and v is
a vector of all nodal voltages with respect to ground.
3) Writing the element equations as ZiYus , where Z and Y are matrices and
s is a vector.
Carrying out steps 1-3 for a circuit put through a parser will result in a matrix equation of the form
Ai00 0 T 00IAu. Eq. 3-1 Z Yvs0
45
Sparse tableau analysis has the advantage greater generality and higher sparsity, but also requires more sophisticated programming techniques to implement [42]. For these reasons, nodal analysis was selected for implementation in SPICE1, and has remained in use in all subsequent versions. Newer simulators such as the Analog Insydes toolbox for
Wolfram Mathematica allow the user to select either STA or nodal analysis.
Nodal analysis can be carried out by [41]:
1) Writing KCL as Ai 0 , where A is the reduced incident matrix and i is a
vector of all branch currents.
2) Using element equations to eliminate as many current variables as possible
from KCL, and forming equations in terms of branch voltages.
3) Using KVL to replace all branch voltages by nodal voltages to ground.
Nodal analysis results in a matrix equation of the form
YBv sv . Eq. 3-2 CZ i si
46
SPICE nodal analysis can be illustrated through a simple example:
Figure 3-3: Linear resistive circuit. Writing KVL equations and using the branch constitutive equation for a resistor leads to
Vv 2 vv23 11 1 V vv23 Eq. 3-3 RR12 RRRR 1221 for node 2 and
vv v 111 23 3 Eq. 3-4 vv23 0 RR23 R 2 RR 23 for node 3. These nodal equations can be translated to matrix form as:
11 1 V RR12 R 2 v2 R . 1 Eq. 3-5 111v3 0 RRR223
SPICE nodal analysis encounters problems when a voltage source or an inductor is present in the circuit. For a voltage source, the conductance is infinite or undefined and the current through it is unknown. Likewise, an inductor becomes a short at DC and therefore also has infinite or undefined conductance.
47
Modified nodal analysis (MNA) extends nodal analysis by representing voltage defined elements as currents in the unknown vector and voltages in the right hand side solution vector [35]. Thus, modified nodal analysis adds an additional step to the nodal analysis procedure [42]:
1) Write KCL as Ai 0 , where A is the reduced incident matrix and i is a vector
of all branch currents.
2) Use element equations to eliminate as many current variables as possible from
KCL, and forming equations in terms of branch voltages.
3) Use KVL to replace all branch voltages by nodal voltages to ground.
4) Append element equations of those elements whose current variables could
not be eliminated as additional equations of the system.
In MNA, the total number of equations needed to analyze a circuit is based on the effective number of nodes
Nnn vl n, Eq. 3-6
where n is the number of circuit nodes, nv is the number of independent voltage sources, and nl is the number of inductors. For a circuit with N effective nodes and E elements, N-
1 independent KCL equations and E-N+1 KVL equations are needed.
The SPICE solution matrix is ultimately composed of a voltage array specifying voltages at the nodes, a current array describing currents through the branches, and a conductance array specifying the current voltage relationships between nodes:
48
Node 1 GGG11 12 13 V1 I 1 Node 2 GGG V I 21 22 23 2 2 . Node 3 GGG31 32 33 V3 I 3 Eq. 3-7
Node123 Node Node
The values of elements in the conductance array are determined from the branch constitutive equations of various elements in the circuit.
One notable feature of SPICE is that matrix formation occurs in a highly organized fashion. After modified nodal analysis is applied, each element in the circuit occupies a regular and predictable place in the matrix. This systematic process of forming the SPICE solution matrix based on familiar elements and their node connections is known as “stamping” [43].
For a resistor placed between node i and node j, shown in Figure 3-4, positive conductance values of 1/R will be added to matrix locations (i, i) and (j, j), while negative conductance values will be added to matrix locations (i, j) and (j, i).
Figure 3-4: Resistor to be stamped In a system with five nodes and a resistor placed between nodes 0 and 1, the following will be stamped:
49
11 000 Node 1 RR22 VI11 Node 2 11 VI 22 000 Node 3 RR22 VI33 . Eq. 3-8 Node 4 0 0 000 VI44 Node 5 0 0 000 VI55 0 0 000
Node12345 Node Node Node Node
If another resistor R3 is added between nodes 1 and 2, the stamping of the two resistors will occur as follows:
11 000 RR 22 Node 1 VI11 1111 Node 2 00 VI 22 RRRR2233 Node 3 VI33 . 11 Eq. 3-9 Node 4 000 VI RR 44 33 Node 5 VI55 00000 00000
Node12 Node Node 345 Node Node
Note that at matrix location (2, 2), the conductance is the sum of the conductances of two resistors that have been stamped there. Stamping for other components occurs in a similar way. For a complete set of stamps, the reader should consult [42].
3.4 SPICE Solution Algorithms
Once the system of equations describing the circuit has been formed through stamping, SPICE implements algorithms to solve the system for values corresponding to node voltages and branch currents. For circuits that can be described by a linear system
50 of equations, such as those composed of sources and resistors only, a form of Gaussian elimination known as LU decomposition can be used. If nonlinear elements such as transistors are present in the circuit, the resulting system of equations will be integro- differential, and Newton-Raphson iteration must be used.
Through modified nodal analysis, SPICE generates a system of equations of the form
Ax = b. Eq. 3-10
In the linear case, Eq. 3-10 can be solved for the solution vector x in several ways. The first is to invert A and use matrix cofactors. One major drawback of this method is that it is inefficient for large matrices. The second is to use Cramer’s rule. This method is better, but still inefficient. For a circuit containing n nodes for example, Cramer’s rule would require 2(n+1)! multiplications to find x; for a circuit with ten nodes, this would evaluate to 79,833,600 calculations.
Instead of matrix inversion or Cramer’s rule, a more efficient method of solving linear systems of equations known as LU decomposition is implemented in SPICE [35].
In LU decomposition, the matrix A is transformed into two triangular matrices: a lower L and an upper U. For a matrix A given by
aaa11 12 13 Aa a a, 21 22 23 Eq. 3-11 aaa31 32 33
LU decomposition forms
51
aaa11 12 13 Uaa 0 22 23 Eq. 3-12 00a33 and
100 a L 21 10. Eq. 3-13 a11 aa 31 32 1 aa11 22
After these matrices are formed, a forward substitution step is performed to give
Ux L1'. b b Eq. 3-14
Back substitution is then performed to produce the solution:
x UbULb1' 1 1. Eq. 3-15
Several LU decomposition algorithms exist, but Gauss’s algorithm is used in SPICE, as shown in Figure 3-5.
Input: A, a nonsingular matrix for (k=1,…,n) do for (j=k,…,n) do ukj = akj for (i=k+1,…,n) do lik = aik/ukk for (i=k+1,…,n) do for (j=k+1,…,n) do aij=aij-likukj
Figure 3-5: Gauss’ algorithm for LU decomposition. Because this algorithm is so similar to the Gaussian elimination method, it is often colloquially said that “Gaussian elimination” is used to find solutions to matrices in
52
SPICE. The prevalence of ULSI circuits with millions of components has spurred the development of algorithms that are much more efficient than LU factorization. For example, one proposed but unimplemented method claims a 1000x speed improvement
[44].
In the case where the circuit is nonlinear, such as when it contains diodes or transistors, the system of equations will consist of differential equations that can no longer be solved through LU decomposition. Instead, SPICE uses the Newton-Raphson algorithm (Eq. 3-16) to iterate to an operating point and linearize the circuit, before using
LU decomposition to solve the system of equations [45].
FX n XXnn1 . Eq. 3-16 FX'n
The Newton-Raphson algorithm is used in SPICE to determine the node voltages that will satisfy the matrix describing a circuit. Newton-Raphson starts with an initial guess and then iterates to a solution. With each iteration, a new set of node voltages is guessed, linearization is performed, and LU decomposition is used to solve the resulting linearized system of equations. The algorithm ends when the difference between successive approximates approaches zero. One important characteristic of the Newton-
Raphson algorithm is that the number of iterations needed to arrive at a solution depends upon how close the initial guess is to the solution.
At each iteration, linearization must be performed on nonlinear devices to arrive at a conductance array that is a linearized approximation of the original BCE’s about a
DC operating point. This foregoes the need for complex algorithms that would be required to solve integro-differential equations. Linearization in SPICE involves using a
53 series of linear, piecewise approximations for eaach device. In the simplest example with a diode, the BCE is given by
qV d Eq. 3-17 Ids I exp 1. NKT
When linearized about a voltage operating point, as shown in Figure 3-6, the linearized BCE can be written as
IGdd VIdeq , Eq. 3-18
where Gd is defined as the dynamic conductance and Ieq is defined as the equivalent current.
Figi ure 3-6: Linearization of a diode (from [45]).
54
The linearized BCE, given in Eq. 3-17, forms the basis for the linear equivalent circuit, shown in Figure 3-7.
Figure 3-7: Linear equivalent model for a diode. Based on this linearized model, SPICe would stamp a diode into the matrix as follows:
GG V I dd1 eq . Eq. 3-19 I GGdd V2 eq
3.5 Convergence and an Updated SiC JFET Model
Nonconvergence in SPICE occurs when the program is unable to find a set of node voltages and branch currents that satisfy KVL, KCL, and BCE’s for a given circuit.
Convergence issues can typically be traced to issues with the Newton-Raphson algorithm, the device models, or interactions between the two.
With regard to simulation of SiC integrated circuits developed at CWRU, techniques to aid convergence can be grouped into three general categories:
1. Adjusting convergence conditions.
2. Setting initial conditions.
55
3. Creating simplified models that are more conducive to convergence.
Techniques (1) and (2) have been used with only mixed results in the past [24]; therefore,
(3), developing new device models, will be the emphasis of this work.
Convergence is achieved when the difference between two consecutive iterations of the Newton-Raphson algorithm is sufficiently small to meet predefined convergence criteria. In SPICE, this means that
1. All voltages and currents in the circuit are within a defined tolerance for two
consecutive iterations.
2. The linear approximations of nonlinear functions are within a set tolerance.
For condition 1, the voltage tolerance for convergence is given by
RELTOLmax Vii1 , V VNTOL, nn Eq. 3-20 where RELTOL is the relative voltage tolerance and VNTOL is the absolute voltage tolerance. In SPICE2, the default values for RELTOL and VNTOL are 10-3 and 1-µV, respectively. For condition 1 to be satisfied,
i1 i VVnn Eq. 3-21 must hold true.
For condition 2, the current tolerance for convergence is given by
I RELTOLmax Inonlinear , I linearized ABSTOL, Eq. 3-22 where RELTOL is the relative voltage tolerance and ABSTOL is the absolute voltage tolerance. Their values are 10-3 and 1-pA, respectively. The convergence condition is met when
56
IInonlinear linearized I . Eq. 3-23
SPICE based simulators use the conditions described above to determine if convergence is reached. The problem with this is that a condition known as false convergence can arise in circuits that have nodes with very highh impedancess. To address this, Cadence adds an additional convergence criterion,, known as the residue criterion [37]:
(k ) Eq. 3-24 f n v f
When using default SPICE models, 75-90 percent of convergence problems can be solved by adjusting three parameters: RELTOL, VNTOL, and ABSTOL. For linear circuits, three additional parameters can be adjusted: GMIN, PIVTOL, PIVREL. For circuits with nonlinear components, adjusting the number of iterations, ITL, can be effective [45].
57
Figure 3-8: Screenshot showing adjustment of convergence parameters in PSPICE. Another popular approach to helping achieve convergence is to use nodesets or node forces. Nodesets, also known as initial conditions, can greatly aid convergence by providing a starting point close to the solution for Newton-Raphson iteration. Also, in cases where multiple solutions exist, nodesets can encourage convergence to a particular solution. For extreme cases where nodesets are not sufficient, node foces can be used to fix a node to a voltage. However, solutions obtained this way do not guarantee the circuit to be in equilibrium, and true convergence is not achieved, even though the simulation might run.
Device models can also play an important role in whether or not a given circuit converges. Improper parameter specifications can cause convergence problems, as can inconsistencies or discontinuities in the model. These issues become even more critical when the model is written in Verlog-A, due to the fine control of all mathematical operations that it enables and the associated risk for incorrect or incomplete calculations.
Both Version 1 and Version 2 of the SiC JFET Verilog-A model suffer from persistent convergence problems, becoming more severe with more complex circuits.
These problems can be traced to the complexity of the mathematical operations used in calculating the drain current, ID. Version 3 of the SiC JFET model resolves convergence issues in circuit simulation by implementing the square law model for Ids vs. Vds.
58
Figuure 3-9: Screenshot showing nonconvergence in the Version 3 Veriloog-A SiC JFET model. A review of literature and discussion on Verilog-A device modeling reveals that convergence issues can be solved by reducing and simplifying mathematical operations as much as possible. This approach was taken in developing Version 3 of the SiC JJFET model (given in the Appendix), where 3/2-power law equations for drain current are replaced by simpler square law equations. In the Version 3 model, a number of Verilog-
A code “best practices” are implemented:
1. Avoiding the exp function when possible.
2. Avoiding feedback loops that require matrix convergence.
3. Using the “cross” function instead of “if”.
4. Using the $strobe function to regularly display values of key parameters as
a simulation is running.
59
5. Using a carefully developed set of initial parameter values.
The Version 3 Verilog-A SiC JFET model enables successful DC convergence in simulation of the single-stage, single-ended transimpedance amplifier (Figure 3-10), something that could not be achieved with earlier models. Thhe Ids vs. Vds characteristics of the model are shown in Figure 3-11. Finally, Figure 3-12 shows an AC sweep of the transimpedance amplifier from 10-Hz to 1-MHz using the Veersion 3 model.
Figure 3-10: Screenshot showing convergence in the Version 3 Verilog-A SiC JFET model.
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Figuure 3-11: Screenshot showing DC sweep of a SiC JFET in the Version 3 model.
Figi ure 3-12: Simulation of the transimpedance amplifier using the Version 3 SiC JFET Verilog-A model.
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Chapter 4. Capacitance Modeling in the Transimpedance Amplifier
4.1 Introduction
Accurate capacitance models are necessary to predict the AC small-signal response of a circuit. In this section, capacitance models for the SiC JFET are analyzed and then verified through SPICE simulation of a SiC JFET transimpedance amplifier.
4.2 SiC JFET Small Signal Model
The current voltage relationships described by the square-law and 3/2-power laws can be used as the basis of the large-signal SiC JFET model. Additional parameters can be added to account for second-order effects, such as the body effect and channel-length modulation.
Figure 4-1: SiC JFET low-frequency small-signal model.
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In the SiC low-frequency small-signal model shown above, gmVgs accounts for the current vs. voltage characteristic, ro accounts for channel length modulation, and gmbVbs accounts for the body effect.
To accurately model the small-signal AC response of a system, a small-signal representation of the transistor that approximates behavior near an operating point is required. The movement and storage of charge within the device are modeled through the use of capacitance models. This necessitates the addition of capacitors to the small- signal model, as follows:
Figure 4-2: SiC JFET high-frequency small-signal model with capacitors. Internal capacitances in the SiC vertical JFET arise from PN junction depletion region capacitance. This is in contrast to the MOSFET, where capacitances may arise from the gate structure or channel charge in addition to junction capacitances. The capacitance in a junction is formed by the separation of charge in the depletion region of a pn junction (Figure 4-3). In this analysis, the depletion is assumed to be abrupt.
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Figure 4-3: Separation of charge in a pn junction depletion region (from [46]). In a pn junction, charge neutrality dictates that the charges on both sides of the junction are equal:
q xANp A qxn AN D Eq. 4-1
Hence,
xn N A Eq. 4-2 xp ND
An expression for the charge stored on one side of the pn junction can be deriveed by combining Eq. 4-2 with
qqj NDnxA Eq. 4-3
NAND qqj AWdep Eq. 4-4 NA ND where
2 s 1 1 Wdep V0 VR Eq. 4-5 q N A ND
is the total width of the junction, i.e. Wn+Wp. A plot of qj versus applied reverse bias VR is shown in Figure 4-4.
64
Figure 4-4: Plot of qj iin a pn junction [46].
Using a small signal approximation, the junction capacitance Cj is defined by
dqJ s A C j Eq. 4-6 dVR Wdep VR VQ
After plugging in Eq. 4-5 for Wdep, a final expression for junction expression can be deduced:
C j0 C j V Eq. 4-7 1 R V0 where
sq NNAD 1 C j0 A Eq. 4-8 2 NNAD V0
is the junction capacitance for zero reverse bias and V0 is the built-in voltage of the pn junction.
65
Using the approach described above, the internal capacitances in the SiC JFET are summarized, as illustrated in Figure 4-5.
Figure 4-5: SiC JFET cross secttion and internal capacitances. By using Eq. 4-7, the capacitances in the SiC JFET, arranged in order of size, are:
Cgs0 Cgs Vgs Eq. 4-9 1 V biG ,
C C bs0 bs V Eq. 4-10 1 bs V biB ,
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C C bd 0 bd V Eq. 4-11 1 bd V biB ,
C C gd 0 gd V Eq. 4-12 1 gd V biG ,
Eq. 4-13 Cgb 0, where
WL qN s d CCgs00 gd Eq. 4-14 22V biG , and
qN s d CCWLbs00 bd diff Eq. 4-15 2V biB .
Two simplifying assumptions are of note here. First, the gate to bulk capacitance, Cgb, is approximately zero for an on-transistor since the gate is shielded from the bulk by the channel. Second, capacitance between gate and channel are assumed to be split equally between gate-source and gate-drain. The gate-source capacitance Cgs and the gate-drain capacitance Cgd are modeled as two separate Schottky barrier diodes. Each diode is assumed to occupy half of the gate carrier, and a constant channel is assumed [47].
Hence, there is an equal split in gate-channel capacitance, as given in Eq. 4-14.
67
Gate
Cgs Cgd
Id
Source Drain
Figure 4-6: Circuit model showinng equal spllitting of gate-channel capaciitance. 4.3 Transimpedance Amplifier Small Signal Model
The SiC JFET transimpedance amplifieer shown Figure 4-8 was designed for applications in sensor interfacing with capacitive and resonant type sensors [7]. It provides a gain of over 200 kΩ with a bandwidth of greater than 200 kHz. In the amplifier, J1 forms the core of the amplifier; J2 acts as a cascode device to increase its output resistance and increase gain; and J4 acts as a common source tto provide a low output impedance of 1/gm to improve bandwidth. J1 and J, together with RCS1 and
RCS2, act as current sources; Rf provides transresistance and a level-shifting voltage drop. Transistors J1, J2, J3, and J5 are sized for (VGS-VT))=2 V, while J4 is sized for
(VGS-VT)=1 V.
Figuure 4-7: Transimpedance amplifier – block view.
68
Figure 4-8: Transimpedance amplifier schematic. The transimpedance gain of the amplifier can be derived as follows:
The small-signal output of the amplifier is given by
AVV vx out, Eq. 4-16
where Av is the small signal open loop gain. The small-signal input current is given by
1 Av Vout VV Av Eq. 4-17 I x out in RR ff.
Therefore, the transimpedance gain is given by
69
Vout RAfv Rm Eq. 4-18 I 1 A in v ,
where Av is large and negative.
4.4 Small Signal Open Loop Gain
The small signal open loop gain, Av, can be analyzed by opening capacitors and reducing the transimpedance as follows:
Figure 4-9: Open-loop transimpedance amplifier – block level view.
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Figure 4-10: Open-loop transimpedaance amplifiier – transistor level view.
The small-signal open-loop gain can be approximated as [7]
Agvm 1 grorm21o23 grm o31Rcs . Eq. 4-19
Upon plugging in parameter values, the exact expression (740) and approximated expression (880) for small signal open loop gain agree to witthhin 16%.
71
Figure 4-11: Small sigi nal open loop gain simulation schematic.
4.5 Closed Loop Transfer Function
By closing the feedback loop with resistor Rf, the open-loop voltage amplifier becomes a closed-loop transimpedance amplifier. To derive the transfer function of the closed-loop transimpedance amplifier, the circuit of Figure 4-12 is used.
Figi ure 4-12: Closed-loop transimpedance ampplifier – block level view. The transfer function of an amplifier can be written in the general form
72
ss 1 1 ... zz12 Hss A0 Eq. 4-20 ss 1 1 ... pp1 2
where A0 is the low frequency gain and ωp and ωz are the poles and zeros of the sys stem, respectively. For a transfer function of the form of Eq. 4-20, the poles and zeros can be easily identified, and the transfer function can be plotted according to Bode’s rules. In Figure 4-14 and Figure 4-15, the model for the transfer function of the closed-loop SiC
JFET transimpedance amplifier is provided. Note that in Figure 4-15, resistor and capacitors have been combined into complex impedances to simplify analysis.
Figuure 4-13: Closed-loop transimpedance amplifier – transistor level view.
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Figure 4-14: Simplified closed-loop small-signal model of the transimpedance ampliifier.
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The small signal capacitances and resistances are lumped together and defined as:
Z15 ro Eq. 4-21
RCS 2 ZZ2 RCS2|| Cbs 5 Cgs 5 Eq. 4-22 1sC C R bs55 gs CS 2
1 ZZ3 Eq. 4-23 CCCdb551 gd gs sC db551 C gd C gs
1 ZZ Eq. 4-24 41Cgd sC gd1
ro1 ZZ5 Eq. 4-25 ro1122|| Cdb C gs C bs 1sC C C ro db1221 gs bs
Eq. 4-26 Z62 ro
1 ZZ7 Eq. 4-27 CCCCgd4322 gd db gd sC gd4322 C gd C db C gd
R ZZCS1 Eq. 4-28 8||RCCS13 gs 1sR CS13 C gs
ro ZZ3 Eq. 4-29 9 ro33|| Cbs 1sroC33 bs
1 ZZ Eq. 4-30 10 Cgs 4 sC gs4
ro ZZ4 Eq. 4-31 11 ro44|| Cbs 1sroC44 bs
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The KVL equations at the critical nodes are:
VVin x V x VVx y gm12 Vin gm V x Eq. 4-32 ZZZ456
VV V VV VV x yyyzyo Eq. 4-33 gm2 Vx ZZZ678 Z 10
VV V yz z Eq. 4-34 gm3 Vyz V Z89Z
VV VV V in oyo o Eq. 4-35 gm4 Vyo V Z f ZZ10 11
Matlab was used to solve the system of equations for Vout/Iin. Based on the transfer
function and its poles and zeros, the dominant capacitors can be found and their values
can be fitted to measured data. The resulting transfer function is too complex to
extrapolate dominant poles and is:
V Rs()out () s cl I Eq. in 36 30 38 113 3 121 2 130 138 1310 (1510 ssss 4910)( 1210 3210 2410 6710 ) 4-36 (1110161ss 6 1110170 5 3910178 s 4 4510186 ss 3 5610193 2 2910200 s 1910208 )
A Bode plot of this expression in Matlab shows that the low frequency gain closely
approximates what is found by hand calculation (Figure 4-15). The 3-dB cutoff
frequency is ~9 MHz and some peaking is observed.
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Figure 4-15: Bode plot of closed-loop transfer function.
4.6 Capacitance Modeling and Extraction of Fit Parameters
The primary internal sources of capacitance in the SiC JFET and their expressions
(Cgs, Cbs, Cbdd, Cgd, and Cgb) were given in section 4.2. The capacitance equation of the form Eq. 4-7 includes only the bottom-well capacitance associated with a pn junction.
This expression does not account for sidewall capacitances illustrated in Figure 4-16, which can be described in a separate term as
C C jsw0 jsw V Eq. 4-37 1 R V0
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Figure 4-16: Illustration showing bottoom-plate and sidewall capacitances in a
FET [48]. thus making the complete capacitance equation
C jsw0 CCj j0 V Eq. 4-38 1 R V0
In most first order junction capacitance models, it is assumed that the doping of the source and drain regions are abrupt. A more general expression for junction capacitance is
C C C j0 jsw0 j m j m jsw VR VR Eq. 4-39 1 1 V0 V0 where m is the grading coefficient, and varies according to the doping profile of the source/drain regions. In the case where the doping profile is assumed to be abrupt, m is
78
1/2. An alternate junction capacitance model, then, assumees a linear-doping profile and uses a grading coefficient of 1/3 in Eq. 4-39.
The accuracy of the above mentioned capacitance models can be verified through
SPICE simulation. Three models were useed: 1) a basic abrupt-doping junction capacitance model, 2) a linear-doping junction capacitance model, and 3) a linear-doping junction capacitance model with sidewall capacitance.
The simulated data using the aforementiooned model is compared to measured data from SiC JFET transimpedance amplifiers fabricated and tested at Case Wesstern.
Previously, these amplifiers have been tested by Amita Patil [7]; they have also been re- tested with near identical results as part of this project.
Figure 4-17: Transimpedance amplifier test setup.
Using the abrupt doping model, the poless of the transimpedance amplifier transfer function roll off at much high frequency than in the measured data, as shown in Figure
4-18. The measured data shows a 3-dB cutoff at approximately 1.7 MHz, while the simulated data has a 3-dB cutoff at approximately 5.9 MHz.
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Figure 4-18: Measured and simulated (SPICE) transimpedance gain using abrupt-
junction model.
A junction capacitance model based on linear doping provides a slightly better match, as seen in Figure 4-19. This model has a 3-dB cutoff at 4.9 MHz, compared to 1.7 MHz in the measured data.
Figuure 4-19: Measured and simulated (SPICE) transimpedance gain using
linear-junction model.
80
Simulation accuracy can be further improved by adding terms for additional capacitances not accounted for in the previously plotted models, including sidewall capacitance and gate overlap capacitance. By adding these terms, a better match can be obtained, as shown in Figure 4-20. This model has a 3-dB cuttoff at 3.6 MHz, compared to 1.7 MHz in the measured data.
Figuure 4-20: Measured and simulated (SPICE) transimpedance gain using
linear-juunction model and including sidewall and gate overlap capacitance.
In addition to the intrinsic device capacitances, the input node also has a capacitance from the two pads needed to connect the external feedback resistor between the input and output. These poles provide a large shunt capacitance that robs Rm current at high frequency. Therefore, a more accurate estimation of the capacitance at the node should account for the capacitance contributed by both the input pad and feedback pad.
By including these parasitics, the simulated frequency response of the transimpedance amplifier can nearly approximate the measured data, as shown in Figure 4-21. This model has a 3-dB cutoff at 2.33 MHz, compared to 1.7 MHz in the measured data.
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Figuure 4-21: Measured and simulated (SPICE) transimpedance gain using
linear-junction model and including parasitics.
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Chapter 5. Conclusion
This work involved modeling the SiC JFET developed at Case Western Reserve
University. In chapter 1, a primer and background to the topic was given. An overview of high-temperature electronics is presented, and the advantages of SiC were outlined.
The SiC JFET and its modeling were also introduced.
In chapter 2, enhancements to DC modeling were presented. A semi-empirical carrier mobility model for SiC was described and implemented, and simulation results were shown. Next, a method for calculating Fermi level and ionized carrier concentration was presented. Finally, a parameter set optimized for the Case Western
SiC JFETs was shown, with simulations showing improved DC simulation matching to measured data.
In chapter 3, the issue of convergence in SPICE simulation was addressed. An introduction to SPICE simulation and solution/convergence algorithms is given. A new square-law Verilog-A model is described and simulation results were shown.
Finally in chapter 4, capacitance models for the SiC JFET were verified in SPICE.
The original models based on abrupt doping were found to be inaccurate, and new models based on a linear profile and accounting for parasitics were proposed that show better correlation with measured data.
Given the wide breadth and scope of the SiC electronics work at Case Western, there is much additional work that can be done. In particular, a major challenge in SiC electronics work is to deal with large and so far, unpredictable process variations that
83 arise from both the material itself as well as the relatively unrefined fabrication steps. It would be helpful to measure variations across fabricated wafers to better characterize them and eventually, incorporate them into a circuit simulator. In the Si CMOS industry, for example, Monte Carlo simulation is routinely carried out to measure the impact of process and temperature variations on circuit performance, robustness, and yield. A similar package could be developed for SiC ICs, and would greatly benefit the SiC IC circuit designer.
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Appendix A: Summary of Model Parameters
85
86
87
Appendix B: MATLAB Code for Deriving
Transimpedance Amplifier Transfer Function clear; clc; %s=tf('s'); syms s; syms vin vx vy vz vo g1 g2 g3 g4 g5 z1 z2 z3 z4 z5 z6 z7 z8 z9 z10 z11 zf zl g1=1.23e-04; g2=1.23e-04; g3=1.23e-04; g4=2.47e-04; g5=6.17e-05; ro1=1.25e+06; ro2=1.25e+06; ro3=1.25e+06; ro4=6.23e+05; ro5=2.49e+06;
Cgd1=1.85615e-12; Cgd2=2.04844e-12; Cgd3=1.60676e-12; Cgd4=1.60676e-12; Cgd5=3.93911e-12;
Cdb1=1.61716e-12; Cdb2=1.54495e-12; Cdb5=1.85615e-12;
Cbs2=1.61716e-12; Cbs3=1.34081e-12; Cbs4=1.31439e-12; Cbs5=2.22394e-12;
Cgs1=3.93911e-12; Cgs2=2.22643e-12; Cgs3=2.22643e-12; Cgs4=2.1114e-12; Cgs5=2.22394e-12;
Cl=10e-12; RCS1=33.12e3; RCS2=66.24e3; Rf=207e3; z1 = ro5; z2= RCS2/(1+((Cbs5+Cgs5)*RCS2*s)); z3=1/(s*(Cdb5+Cgd5+Cgs1)); z4=1/(s*Cgd1); z5=ro1/(1+((Cdb1+Cgs2+Cbs2)*ro1*s)); z6=ro2; %z7=1/(s*(Cgd4+Cgd3+Cdb2+Cgd2)); z7=1/(s*(9e-012)); z8= RCS1/(1+((Cgs3)*RCS1*s)); z9=ro3/(1+((Cbs3)*ro3*s)); z10=1/(s*Cgs4); zl=ro4/(1+((Cbs4+Cl)*ro4*s)); zf=Rf;
P=[0 0 ((1/z8)+g3) -(g3+(1/z8)+(1/z9)); (1/zf) 0 ((1/z10)+g4) 0;0 (g2+(1/z6)) -((1/z6)+(1/z7)+(1/z8)+(1/z10)) (1/z10); ((1/z4)-g1) -((1/z4)+(1/z5)+(1/z6)+g2) (1/z6) 0]; U=[vin; vx; vy;vz]; Q=[0*vo; vo*((1/zl)+(1/zf)+(1/z10)+g4); -vo*(1/z10); 0*vo]; U=inv(P)*Q; vin=U(1); vx=U(2); vy=U(3); vz=U(4); vw=vin*(z2/(z1+z2+(g5*z1*z2))); vinred=simplify(vin); vxred=simplify(vx); vyred=simplify(vy); vzred=simplify(vz); vwred=vinred*(z2/(z1+z2+(g5*z1*z2))); I3=(vin/z3)+((vin-vx)/z4); I3red=(vinred/z3)+((vinred-vxred)/z4); %Iin=(vinred*((1/(z1+z2+g5*z1*z2))+(1/z3)+(1/zf)+g1))-(vo/zf)-(vyred/z6)+(vxred*((1/z5)+g2+(1/z6))); %Iin=vin*((1/z3)+(1/zf)+(g1)+(1/(z1+z2+(z1*z2*g5)))) - (vy/z6) - (vo/zf) + vx*(g2+(1/z5)+(1/z6)); %Iin=I3 - (g5*vw) + ((vin-vo)/zf) + ((vin-vw)/z1) Iin=I3red - (g5*vwred) + ((vinred-vo)/zf) + ((vin-vwred)/z1) Avcl1=vo/Iin;
Avcl=simplify(Avcl1) s=tf('s'); %h=bodeplot(Avcl)
%a=getoptions(h); a.MagUnits='abs'; %setoptions(h,a);
88
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