EXPERIMENT 11

CHARACTERISTICS OF THE JUNCTION FIELD EFFECT TRANSISTOR

1.0 OBJECTIVES: To become familiar with the theory of operation of Junction Field Effect Transistors (JFET) and to examine the V-I characteristics of the JFET.

2. INTRODUCTION: Figure 1 shows a structural comparison between an n-channel JFET and an NPN BJT transistor. As this figure depicts, the n-channel JFET is made of n-type semiconductor material with two islands of p-type materials embedded in the middle sides of this material. One end of the n-type channel is called "Source" while the opposite end is called "Drain". The two p-type materials in the middle are internally connected and are referred to as the "Gate". Notice the narrow channel between the two p-regions of the JFET in Figure 1. It is through this narrow channel that the free electrons in the N- type material must pass as they move from the source to the drain. Thus, when a negative voltage is applied on the gate, the induced electric field in this p-material (gate) will control the flow of electrons between the source and the drain. Therefore, unlike the BJT, the JFET is a voltage-controlled device.

Figure 1 - Structural comparison between the BJT and the JFET.

In biasing the n-channel JFET, a positive voltage VDD is connected between the drain and the source thus allowing for the free electrons to flow from the source to the drain. Since these electrons must pass through the gate region (channel), this would provide a means for controlling the current flow from the drain to the source. This is done by applying negative voltage across the gate region to impede the movement of the electrons passing through this region. Figure 2 (a) illustrates the bias of an n- channel JFET.

Figure 2 - Biasing an n-channel JFET.

Notice that the negative gate supply V GG is connected between the gate and the source. This is standard for all JFET applications. The gate of the JFET must always be reverse biased to prevent electric current from flowing into the gate. However, the reverse bias introduces depletion layers around the gate region (p-region) as shown in Figure 2 (b). Thus, increasing the negative voltage on the gate will make the conduction channel across the gate narrower. The more negative the gate voltage the narrower the channel becomes because the depletion layers get closer together. When the gate voltage is made negative enough, the depletion layers across the gate region touch and the conducting channel disappears (PINCH OFF). In this case the drain- source current is cut-off. The gate voltage in this case is called the "Pinch-off" voltage

(V p-off ). Typical value for such a voltage in small signal JFET's is about -3 to -4V DC.

On the other hand, when VGG is set to zero, the pinch-off region will disappear, and the current from the drain to the source will be free to flow, only controlled by the resistance of the n-type materials forming the n-type channel, see Figure 1. Thus this current is the maximum drain current a JFET can produce for a given drain-to-source voltage before the transistor does into breakdown. This current is typically referred to as I DSS .

The trans-conductance characteristic of the JFET is a set of graphs relating the drain current to the gate voltage, i.e. I D versus V GS . In analytical form, this relationship is universally given as, 2 VGS ID = I DSS 1 − eq. 1 Vp-off

This equation applies to any JFET regardless of the channel polarity.

3. LAB WORK In this experiment, a 2N5457, N-type JFET will be used in the measurement. The pin connection diagram for the 2N5457 transistor is as shown in Figure 3.

Figure 3 - Pin connection diagram of the 2N5457 JFET. JFET. 3.1 Measurement of the DC resistance of the Drain-Source channel of the JFET: For the given transistor, measure the DC resistance between the drain and source terminals with the gate terminal left open. Reverse the polarity of the DMM probe and measure the channel resistance of the drain-source again. Compare the two measured values.

3.2 Measurement of the trans-conductance characteristic of the JFET transistor

ID versus V GS :

Connect the transistor circuit as shown in Figure 4. Adjust V GG voltage and measure the following:

a- The current through the drain in the output circuit (I D) as a function of V GS .

Make sure that V GG is always negative with respect to the Source.

b- Measure the input resistance (R GS ) of the JFET transistor as a function of V GS .

c- Plot I D versus V GS . From this plot determine the value of the pinch-off voltage

(V p-off ) and I DSS . If the measured data does not cover these two data points, make sure that enough readings are taken to extend the graph to these two critical points.

d- Plot the input gate resistance of the JFET (R GS ) versus V GS .

e- Having determined V p-off and I DSS , use equation 1 to plot a theoretical graph of

ID versus V GS . Plot the measured and calculated graphs on the same axis and compare the theoretical results with the measured graph.

Figure 4 - Connection diagram for the measurement of the trans-conductance of the JFET transistor.

3.3 Measurement of the drain curves of the JFET:

Using the test circuit of Figure 4, Measure I D versus V DS for constant V GS . Extend

VDD voltage to about 30V to measure the breakdown voltage of the transistor. Get a

set of curves for V GS = 0, -1, -2, -3 and -4 V. Plot all these graphs as one set of curves to compare them against each other.

4. REPORT:

4.1 Report all the measured and calculated data. Compare measured results against calculated and comment on any possible reasons for differences between the two sets of data.

4.2 How do you compare the JFET against the BJT?

4.3 When do you prefer to use a JFET in your applications rather than a BJT?