Unit Ii Jfet, Mosfet, Scr & Ujt Field Effect Transistor

21-Aug-15

UNIT II JFET, MOSFET, SCR & UJT

• JFET – JFET as an Amplifier and its Output Characteristics – JFET Applications– • MOSFET Working Principles, SCR – Equivalent Circuit and V-I Characteristics. • SCR as a Half wave and full wave rectifier– Application of SCR, UJT– Equivalent • Circuit of a UJT and its Characteristics.

FIELD EFFECT TRANSISTOR

• The acronym ‘FET’ stands for field effect transistor. It is a three-terminal unipolar solid-state device in which current is controlled by an electric field as is done in vacuum tubes.

• Broadly speaking, there are two types of FETs : • (a) junction field effect transistor (JFET) • (b) metal-oxide semiconductor FET (MOSFET)

1 21-Aug-15

CONSTRUCTION OF JFET

• It can be fabricated with either between these gates is called an N-channel or P-channel channel. though N channel is generally preferred. • For fabricating an N-channel JFET, first a narrow bar of N- type semiconductor material is taken and then two P-type junctions are diffused on opposite sides of its middle • These junctions form two P-N diodes or gates and the area

2 21-Aug-15

CONTD..,

• The two P-regions are internally connected and a single lead is brought out which is called gate terminal. • Ohmic contacts (direct electrical connections) are made at the two ends of the bar-one lead is called source terminal S and the other drain terminal D. • When potential difference is established between drain and source, current flows along the length of the ‘bar’ through the channel located between the two P-regions. • The current consists of only majority carriers which, in the present case, are electrons

PARTS OF JFET

• Source. It is the terminal through which majority carriers enter the bar. Since carriers come from it, it is called the source • Drain. It is the terminal through which majority carriers leave the bar i.e. they are drained out from this terminal. The drain-to source voltage V DS drives the drain current ID. • Gate. These are two internally-connected heavily-doped impurity regions which form two P-N junctions. The gate-source voltage VGS reverse biases the gates • Channel. It is the space between two gates through which majority carriers pass from source-to-drain when VDS is applied.

3 21-Aug-15

THEORY OF OPERATION

• While discussing the theory of operation of a JFET, it should be kept in mind that • 1. Gates are always reversed-biased. Hence, gate current IG is practically zero. • 2. The source terminal is always connected to that end of the drain supply which provides the necessary charge carriers. • In an N-channel JFET, source terminal S is connected to the negative end of the drain voltage supply (for obtaining electrons). In a P channel JFET, S is connected to the positive end of the drain voltage supply for getting holes which flow through the channel. • Let us now consider an N-channel JFET and discuss its working when either VGS or VDS or both are changed.

1. When VGS = 0 and VDS = 0 • In this case, drain current ID = 0, because VDS = 0. • The depletion regions around the P-N junctions are of equal thickness and symmetrical as shown in Fig

4 21-Aug-15

2.When VGS = 0 and VDS is increased from zero • For this purpose, the JFET is connected to the VDD supply as shown in Fig. • The electrons (which are the majority carriers) flow from S to D whereas conventional drain current ID flows through the channel from D to S. • Now, the gate-to-channel bias at any point along the channel is . = |VDS | + | VGS | Ie the numerical sum of the two voltages. In the present case, external bias VGS = 0

• Hence gate-channel reverse • Hence, depletion regions bias is provided by VDS penetrate more deeply into alone. Since the value of VDS the channel in the drain-gate keeps decreasing as we go region than in the source-gate from D to S, the gate-channel region. bias also decreases accordingly. • It has maximum value in the drain-gate region and minimum in the source-gate region.

5 21-Aug-15

• As VDS is gradually increased from as VDS is increased from zero zero, ID increases proportionally as onwards per Ohm's law. • It is found that for small initial values of VDS, the N-type channel material acts like a resistor of constant value. • It is so because VDS being small, the depletion regions are not large enough to have any significant effect on channel cross-section and, hence, its resistance. • Consequently, ID increases linearly

• The ohmic relationship between VDS and ID continues till VDS reaches a

certain critical value called pinch-off voltage VPO when drain current

becomes constant at its maximum value called IDSS.

• The SS in IDSS indicates that the gate is shorted to source to make sure that VGS = 0. This current is also known as zero-gate-voltage drain current

• It is seen from Fig. that under pinch-off conditions, separation between the depletion regions near the drain end reaches a minimum value W. It should, however, be carefully noted that pinch-off does not mean ‘current-off ’. In fact, ID is maximum at pinch-off.

6 21-Aug-15

• When VDS is increased beyond VPO, ID remains constant at its

maximum value IDSS upto a certain point. It is due to the fact that further increase in VDS (beyond VPO) causes more of the channel on the source end to reach the minimum width as shown in Fig. 63.2 (d). • It means that the channel width does not increase, instead its length L increases.

• As more of the channel reaches when JFET breaks down and ID the minimum width, the increases to an excessive value resistance of the channel as seen from drain characteristic increases at the same rate at of Fig which VDS increases. • In other words, increase in VDS is neutralized by increases in RDS. Consequently, ID = (VDS / RDS) remains unchanged even though VDS is increased. • Ultimately, a certain value of VDS (called VDSO) is reached

7 21-Aug-15

STATIC CHARACTERISTICS OF A JFET

(i) Drain characteristic: It gives relation between ID and VDS for different values of VGS (which is called running variable).

(ii) Transfer characteristic It gives relation between ID and VGS for different values of VDS.

DRAIN CHARACTERISTIC

1.Ohmic Region OA: • This part of the characteristic is linear indicating that for low values of VDS, current varies directly with voltage following Ohm's Law. • It means that JFET behaves like an ordinary resistor till point A (called knee) is reached.

8 21-Aug-15

DRAIN CHARACTERISTIC

2. Curve AB • The drain-to-source voltage • In this region, ID increases at VDS corresponding to point B is reverse square-law rate upto called pinch-off voltage Vp*. point B which is called pinch- off point. • This progressive decrease in the rate of increase of ID is caused by the square law increase in the depletion region at each gate upto point B where the two regions are closest without touching each other.

DRAIN CHARACTERISTIC

3.Pinch-off Region BC: • It should also be noted that the • It is also known as saturation reverse bias required by the region or ‘amplified’ region. gate-channel junction is supplied entirely by the voltage • Here, JFET operates as a drop across the channel constant-current device resistance due to flow of IDSS because ID is relatively and none by external bias independent of VDS. because VGS = 0. • It is due to the fact that as VDS • Drain current in this region is increases, channel resistance given by Shockley's equation also increases proportionally thereby keeping ID practically constant at IDSS.

9 21-Aug-15

DRAIN CHARACTERISTIC

4. Breakdown Region in VDS produce very large • If VDS is increased beyond its changes in ID. value corresponding to point C (called avalanche breakdown voltage), • JFET enters the breakdown region where ID increases to an excessive value. • This happens because the reverse-biased gate-channel P-N junction undergoes avalanche breakdown when small changes

DRAIN CHARACTERISTIC

• It is interesting to note that increasing values of VDS make a JFET behave • first as a resistor(ohmic region), • then as a constant-current source (pinch-off region) • and finally, as a constant-voltage source (breakdown region).

10 21-Aug-15

JFET CHARACTERISTICS WITH EXTERNAL BIAS

• It is seen that with VGS = 0, ID achieved with a lower value of saturates at IDSS and the ID. characteristic shows VP = 4V. • Similarly, when VGS is –2V and • When an external bias of –1 V is –3V, pinch-off is achieved with applied, gate-channel junctions 2 V and 1 V respectively along still require –4 V to achieve the channel pinch-off (remember, VGS = – VP). • It means that a 3V drop is now required along the channel instead of the previous 4V. • Obviously, this 3V drop can be

TRANSFER CHARACTERISTIC

• It is a plot of ID versus VGS for a constant value of VDS and is shown in Fig • It is similar to the transconductance characteristics of a vacuum tube or a transistor. • It is seen that when VGS = 0, ID =IDSS and when ID = 0, VGS = VP. • The transfer characteristic approximately follows the equation.

11 21-Aug-15

JFET PARAMETERS

• The various parameters of a JFET can be obtained from its two characteristics..,

1.AC Drain Resistance, rd • It is the ac resistance between drain and source terminals when JFET is operating in the pinch-off region. It is given by

2.Transconductance, gm • It is simply the slope of transfer characteristic.

JFET PARAMETERS

3.Amplification Factor, μ

4.DC Drain Resistance, RDS • It is also called the static or ohmic resistance of the channel. It is given by

12 21-Aug-15

DC BIASING OF A JFET

A JFET may be biased by using either 1. a separate power source VGG.

DC BIASING OF A JFET

2.Self-bias. of the ac input voltage, νin. • The circuit of Fig.(b) is called self-bias • Moreover, in case leakage current is not circuit because the VGS bias is obtained totally negligible, RG would provide it from the flow of JFET's own drawn an escape route. Otherwise, the leakage current ID through RS. current would build up static charge (voltage) at the gate which could ∴ VS = ID RS and VGS = – ID RS change the bias or even destroy the • The addition of RG in Fig.(b), does not JFET. upset this dc bias for the simple reason

that no gate current flows through it. • Without RG, gate would be kept ‘floating’ which could collect charge and ultimately cutoff the JFET. • The resistance RG additionally serves the purpose of avoiding short-circuiting

13 21-Aug-15

DC BIASING OF A JFET

3. Source bias. • Fig. (c) shows the source bias circuit which employs a self- bias resistor RS to obtain VGS.

• Here, VSS = ID RS+ VGS or • VGS = VSS – ID RS. 4. Voltage divider bias. • Fig.(d) shows the familiar voltage divider bias. In this case, • V2= VGS + ID RS or VGS = V2 – ID RS

JFET AMPLIFIER

• A simple circuit for such an amplifier is shown in Fig.. Here, RG serves the purpose of providing leakage path to the gate current, RS develops gate bias, C3 provides ac ground to the input signal and RL acts as drain load. WORKING: When negative-going signal is applied to the input 1. gate bias is increased, 2. depletion regions are widened, 3. channel resistance is increased, 4. ID is decreased, 5. drop across RL is decreased, 6. Consequently, a positive-going signal becomes available at the output through C2 in When positive-going signal is applied at the input, then a negative-going signal becomes available at the output.

14 21-Aug-15

COMMON SOURCE JFET AMPLIFIER

• Input Resistance r´i = RG || RGS • In an ideal JFET, RGS is infinite because IG = 0. In an actual device, however, RGS is not actually infinite but extremely high as compared to RG. • Output Resistance ro´ = rd || RL ≅ RL — if rd » RL • (iii) Voltage Gain • Vo = id ×rd || RL Now, id = –gm × vi • ∴ Vo = –gm Vi × (rd || RL)

ADVANTAGES & DISADVANTAGES OF FETS

• Advantages of FETs • The only disadvantages are : 1. high input impedance, 1. small gain-bandwidth product, 2. small size, 2. greater susceptibility to damage in 3. ruggedness, handling them. 4. long life, 5. high frequency response, 6. low noise, 7. negative temperature coefficient, hence better thermal stability, 8. high power gain, 9. a high immunity to radiations, 10. no offset voltage when used as a switch (or chopper), 11. square law characteristics.

15 21-Aug-15

MOSFET

• Like JFET, it has source, gate and drain. the gate because it is insulated from However,its gate is insulated from its the channel. conducting channel by an ultra-thin• Unlike JFET, a DE MOSFET has only metal-oxide insulating film (usually of one P-region or N-region called silicon dioxideSiO2). substrate. Normally, it is shorted the • Because of this insulating property. source internally. MOSFET is alternatively known as insulated-gate field-effect transistor (IGFET or IGT). Here also, gate voltage controls drain current but main difference between JFET and MOSFET is that, in the latter case, we can apply both positive and negative voltages to

MOSFET

• Depletion-enhancement MOSFET or DE MOSFET • This MOSFET is so called because it can be operated in both depletion mode and enhancement mode by changing the polarity of VGS. • When negative gate-to-source voltage is applied, the N-channel DE MOSFET operates in the depletion mode. • However, with positive gate voltage, it operates in the enhancement mode. • Since a channel exists between drain and source, ID flows even when VGS = 0. That is why DE MOSFET is known as normally- ON MOSFET.

16 21-Aug-15

MOSFET

• Enhancement-only MOSFET • As its name indicates, this MOSFET operates only in the enhancement mode and has no depletion mode. • It works with large positive gate voltages only. • It differs in construction from the DE MOSFET in that structurally there exists no channel between the drain and source. • Hence, it does not conduct when VGS = 0. That is why it is called normally-OFF MOSFET.

WORKING

• (i) Depletion Mode of N-channel DE called VGS(off) can cut-off the channel. MOSFET • For obvious reasons, negative-gate • When VGS = 0, electrons can flow operation of a DE MOSFET is called its freely from source to drain through the depletion mode operation. conducting channel which exists between them. • When gate is given negative voltage, it depletes the N-channel of its electrons by including positive charge in it as shown in Fig. • Greater the negative voltage on the gate, greater is the reduction in the number of electrons in the channel and, consequently, lesser its conductivity. • In fact, too much negative gate voltage

17 21-Aug-15

WORKING

(ii) Enhancement Mode of N-channel DE current flows between the terminals. MOSFET • That is why, positive gate operation of a • Again, drain current flows from source DE MOSFET is known as its to drain even with zero gate bias. When enhancement mode operation. positive voltage is applied to the gate, the input gate capacitor is able to create free electrons in the channel which increases ID. Free electrons are induced in the channel by capacitor action. • These electrons are added to those already existing there. This increased number of electrons increases or enhances the conductivity of the channel. • consequently, increasing amount of

SILICON CONTROLLED RECTIFIER

• It is one of the prominent members • It can switch ON for variable of the thyristors family. lengths of time, thereby delivering • It is a four layer or PNPN device. selected amount of power to the Basically, it is a rectifier with a load. control element. • Hence, it possesses the advantages • In fact, it consists of three diodes of a rheostat and a switch connected back-to-back with a gate connection. • It is widely used as a switching device in power control applications. It can control loads by switching current OFF and ON up to many thousand times a second.

18 21-Aug-15

CONSTRUCTION

• it is a three terminal four-layer transistor, the layers being alternately of P-type and N-type silicon. • The three junctions are marked J1, J2 and J3 whereas the three terminals are : anode (A), cathode (C) and gate (G) which is connected to the inner P-type layer. • The function of the gate is to control the firing of SCR.

BIASING

• With the polarity of V as shown there is no flow of current in Fig.(a), the junctions J1 and through the SCR. J3 become forward-biased whereas J2 is reverse- biased. • Hence, no current (except leakage current) can flow through the SCR. • In Fig. (b), polarity of V has been reversed. It is seen that, now, junctions J1 and J3 become reverse-biased and only J2 is forward-biased. Again,

19 21-Aug-15

OPERATION

• In Fig. (a), current flow is blocked due to reverse-biased junction J2. However, when anode voltage is increased, a certain critical value called forward break over voltage VBO is reached, when J2 breaks down and SCR switches suddenly to a highly conducting state. • Under this condition, SCR offers very little forward resistance (0.01 Ω – 1.0 Ω) so that voltage across it drops to a low value (about 1 V) as shown in Fig. and current is limited only by the power supply and the load resistance. Current keeps flowing indefinitely until the circuit is opened briefly. • With supply connection as in Fig.(b), the current through the SCR is blocked by the two reverse biased junctions J1 and J3. When V is increased, a stage comes when Zener breakdown occurs which may destroy the SCR . Hence, it is seen that SCR is a unidirectional device.

APPLICATIONS

• Main application of an SCR is as a power control device. • Consequently, it never dissipates any appreciable amount of power even when controlling substantial amounts of load power. For example, one SCR requires only 150 mA to control a load current of 2500 A.

• Other common areas of its application include. 1. relay controls, 2. regulated power supplies, 3. static switches, 4. motor controls, 5. inverters, 6. battery chargers, 7. heater controls, 8. phase control.

20 21-Aug-15

UNIJUNCTION TRANSISTOR

• It is a three-terminal silicon diode. As its name indicates, it has only one P-N junction. • It differs from an ordinary diode in that it has three leads and it differs from a FET in that it has no ability to amplify. • However, it has the ability to control a large ac power with a small signal.

CONSTRUCTION

• It consists of a lightly-doped conventional current when UJT silicon bar with a heavily-doped is in the conducting state. P-type material alloyed to its one side (closer to B2) for producing single P-N junction. • As shown in Fig. there are three terminals : one emitter, E and two bases B2 and B1 at the top and bottom of the silicon bar. • The emitter leg is drawn at an angle to the vertical and arrow points in the direction of

21 21-Aug-15

INTER-BASE RESISTANCE (RBB)

• It is the resistance between B2 shown as a variable resistor and B1 i.e. it is the total because its value varies resistance of the silicon bar from inversely as IE. one end to the other with emitter terminal open. • From the equivalent circuit of Fig. 64.2 (b), it is seen that

RBB = RB2 + RB1 • It should also be noted that point A is such that RB1 > RB2. Usually, RB1 = 60% of RB1. • The resistance RB1 has been

INTRINSIC STAND-OFF RATIO

• As seen from Fig, when a battery of 30 V • The voltage division factor is given a is applied across B2 B1, there is a special symbol (η) and the name of progressive fall of voltage over RBB ‘intrinsic standoff ratio’ provided E is open. • It is obvious from Fig. that emitter acts as a voltage-divider tap on fixed resistance RBB.

• With emitter open, I1 = I2, the interbase current is given by Ohm’s Law.

• I1= I2=V BB /R BB • It may be noted that part of VBB is dropped over RB2 and part on RB1. Let us call the voltage drop across RB1 as VA. Using simple voltage divider relationship,

22 21-Aug-15

OPERATION

• When VBB is switched on, VA is IP starts to flow through RB1 to ground developed and reverse-biases the (i.e. B1). The UJT is then said to have junction. If VB is the barrier voltage of been fired or turned ON. the P-N junction, then total reverse bias voltage is = VA + VB = ηVBB + VB • Value of VB for Si is 0.7 V. • It is obvious that emitter junction will not become forward-biased unless its applied voltage VE exceeds (ηVBB+ VB). This value of VE is called peak- point voltage VP . • When VE = VP, emitter (peak current),

Contd..,

• Due to the flow of IE (= IP) through increases, the UJT possesses negative RB1, number of charge carriers in RB1 resistance. is increased which reduces its • Beyond the valley point, UJT is in saturation and VE increases very little resistance. As η depends on RB1, its with an increasing IE. value is also decreased. • It is seen that only terminals E and B1 • Hence, we find that as VE and hence IE are the active terminals whereas B2 is increases (beyond IP), RB1 decreases, η the bias terminal i.e. it is meant only for decreases and VA decreases. This applying external voltage across the decrease in VA causes more emitter UJT. current to flow which causes a further • Generally, UJT is triggered into reduction in RB1, η and VA conduction by applying a suitable • Obviously, the process is regenerative. positive pulse at its emitter. VA as well as VE quickly drop as IE • It can be brought back to OFF state by increases. Since, VE decreases when IE applying a negative trigger pulse.

23 21-Aug-15

CONDITION FOR TURN-ON AND TURN- OFF • To ensure turn-on, R must not limit IE at peak point to a value less than IP. It means that

• To ensure turn-off of the UJT at valley point, R must be large enough to permit IE to decrease below the specified value of IV. Hence, condition for turn-off is

APPLICATIONS

• One unique property of UJT is that it can be triggered by (or an output can be taken from) any one of its three terminals. • Once triggered, the emitter current IE of the UJT increases regeneratively till it reaches a limiting value determined by the external power supply. Because of this particular behaviour, UJT is used in a variety of circuit applications. • Some of which are : • 1. phase control 2. switching 3. pulse generation, • 4. sine wave generator 5. sawtooth generator 6. timing and trigger circuits, • 7. voltage or current regulated supplies