ELECTRONIC DEVICES & CIRCUITS

For ELECTRONICS & COMMUNICATION ENGINEERING

ELECTRONIC DEVICES & CIRCUITS SYLLABUS Energy bands in silicon, intrinsic and extrinsic silicon. Carrier transport in silicon: diffusion current, drift current, mobility, and resistivity. Generation and recombination of carriers.p-n junction diode, Zener diode, tunnel diode, BJT, JFET, MOS capacitor, MOSFET, LED, P-I-N and avalanche photo diode, Basics of LASERs. Device technology: integrated circuits fabrication process, oxidation, diffusion, ion implantation, photolithography, n-tub, p-tub and twin-tub CMOS process. ANALYSIS OF GATE PAPERS Exam Year 1 Mark Ques. 2 Mark Ques. Total 2003 5 5 15 2004 3 7 17 2005 3 3 9 2006 4 4 12 2007 2 6 14 2008 4 4 12 2009 2 3 8 2010 2 4 10 2011 3 3 9 2012 1 3 7 2013 3 - 3 2014 Set-1 2 5 12 2014 Set-2 3 3 9 2014 Set-3 3 4 11 2014 Set-4 3 4 11 2015 Set-1 2 2 6 2015 Set-2 2 3 8 2015 Set-3 2 2 6 2016 Set-1 3 4 11 2016 Set-2 3 4 11 2016 Set-3 3 3 9 2017 Set-1 3 4 11 2017 Set-2 3 4 11 2018 4 4 12

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission CONTENTS Topics Page No

1. SEMICONDUCTORS

1.1 Structure of Atom 1.2 Energy Band Theory 1.3 Classification of Materials 01 1.4 Fermi Dirac Function 01 1.5 Classification of Semiconductors 02 1.6 Mobility of Charge Carriers 03 1.7 Law of Electrical Neutrality 03 1.8 Mass Action Law 07 1.9 Conductivity 08 1.10 Resistivity 108 1.11 Resistance 109 1.12 Conductance 10 1.13 Current Density 10 1.14 Einstein’s Equation 11 1.15 Electric Field 11 1.16 Hall Effect 12 1.17 Properties of Germanium & Silicon 12 Gate Questions 13 4 2. P-N JUNCTION DIODES 5

2.1 Junction Theory 2.2 PN junction in Forward Bias 2.3 PN junction in Reverse Bias 26 2.4 I-V Characteristics 227 2.5 Effect of Temperature 228 2.6 Diode Capacitances 8 2.7 Diode switching 9 2.8 Varactor Diode 30 2.9 Light Emitting Diode 31 2.10 Zener Diode 32 2.11 Tunnel Diode 32 2.12 Types of PN junctions 32 Gate Questions 34 34 36

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 3. TRANSISTORS

3.1 Introduction 7 3.2 Bipolar Junction Transistor 7 3.3 Transistor Action 48 3.4 BJT Current Components 48 3.5 Early Effect 4 3.6 Operating Regions of BJT 40 3.7 Operating Modes of BJT 501 3.8 Application of BJT 52 3.9 Field Effect Transistors 52 3.10 Junction Field Effect Transistor 53 3.11 MOS Capacitor 5 3.12 MOSFET 5 3.13 Depletion MOSFET 57 3.14 Enhancement MOSFET 59 3.15 Comparison between MOSFET & JFET 59 Gate Questions 61 64 4. IC FABRICATION 65

4.1 Classification 4.2 Monolithic Technology 4.3 Basic Planer Process 79 4.4 Fabrication of Typical Circuit 79 80 5. ASSIGNMENT QUESTIONS 85

88

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 1 SEMICONDUCTORS

1.1 STRUCTURE OF AN ATOM 1, 2 or 3 electrons in their outer levels will tend to lose them in interactions with Matter has mass and takes up space. Atoms atoms that have 5, 6 or 7 electrons in their are basic building blocks of matter, and outer levels. Atoms that have 5, 6 or 7 cannot be chemically subdivided by electrons in their outer levels will tend to ordinary means. Atoms are composed of gain electrons from atoms with 1, 2 or 3 three types of particles: proton, neutron, electrons in their outer levels. Atoms that and electron. Proton and neutron are have 4 electrons in the outer most energy responsible for most of the atomic mass. level will tend to neither totally lose nor The mass of an electron is very small totally gain electrons during interactions. 31 mn  9.108X10 kg Both the protons and neutrons reside in the 1.2 ENERGY BAND THEORY nucleus. Protons have a positive (+) charge, neutrons have no charge i.e. they are In solid-state physics, the electronic band neutral. Electrons reside in orbitals around structure (or simply band structure) of a the nucleus. They have a negative charge (- solid describes those ranges of energy that ). The electrons of an atom are bound to the an electron within the solid may have nucleus by the electromagnetic force. (called allowed or permitted bands), and Likewise, a group of atoms can remain ranges of energy that it may not have bound to each other by chemical (called forbidden bands). bonds based on the same force, forming a molecule. Out of all the energy bands, three bands are An atom containing an equal number of most important to understand the behavior protons and electrons is electrically of solids. These bands are, neutral; otherwise it is positively or 1) Valence band negatively charged and is known as an ion. 2) Conduction band It is the number of protons that determines 3) Forbidden band or gap the atomic number. e.g. no. of protons in the nucleus of silicon is 14 hence atomic no. of Si=14. All atoms would like to attain electron configurations like noble gases. That is, have completely filled outer shells. Atoms can form stable electron configurations like noble gases by: 1. Losing electrons 2. Sharing electrons 3. Gaining electrons. Fig. Energy Band Diagram For a stable configuration each atom must fill its outer energy level. In the case of The energy band formed due to merging noble gases that means eight electrons in energy levels associated with the valence the last shell (with the exception of He electrons i.e. electrons in the last shell is which has two electrons). Atoms that have called valence band. In normal condition,

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission valence electrons form the covalent bands valence band are overlapped in conductors. and are not free. But when certain energy is Hence even at room temperature, a large imparted to them, they become free. number of electrons are available for The energy band formed due to merging of conduction. So without any additional energy levels associated with the free energy, such metals contain a large number electrons is called conduction band. of free electrons and hence called good Under normal condition, the conduction conductors. band is empty and once energy is imparted, the valence electrons jump from valence band to conduction band and become free. While jumping from valence band to conduction band, the electrons have to cross an energy gap. This energy gap which is present separating the conduction band and the valence band is called forbidden band or forbidden gap. The energy imparted to the electrons must be greater than the energy associated with the 1.3.2 SEMICONDUCTORS forbidden gap, to extract the electrons from valence band and transfer them to Semiconductors are those materials whose conduction band. The energy associated to electrical conductivity is between forbidden band is denoted asEG. conductors and insulators. The forbidden The graphical representation of the energy gap in semiconductors is about 1 eV. In bands in a solid is called energy band semiconductors the energy provided by diagram heat at room temperature is sufficient to Note:-The electrons cannot exist in the lift electrons from valence band to forbidden gap. conduction band. But at T=0 o.k. (absolute zero or −273oC), all the electrons find 1.2.1 UNIT OF ENERGY eV themselves in valence band hence S.C. behaves as perfect insulators at T = 0oK. The unit joule is very large for the energies The forbidden energy band gap in associated with electrons. Hence such semiconductors depends on temperature & energies are measured in electron volts it is given by EEβ T eV denoted as eV. 1 eV is defined as the G at TK0oo K o kinetic energy gained by an electron when where, it falls through a potential of one volt. 4o 19 βo  3.6 10 eV/ K for silicon 1eV1.610J 4o β2.210eV/Ko  for germanium E 1.21eV for silicon 1.3 CLASSIFICATION OF MATERIALS 0Ko

E0.785eVo  for germanium Based on the properties shown at different 0K surrounding conditions, materials are classified as Using above equations the forbidden band gap for silicon and germanium at T = o 1.3.1 CONDUCTORS 300 K i.e. at room temperature are 1.1 eV&0.72 eV respectively. In the metals there is no forbidden gap between valence band and conduction band i.e.EG = 0 eV. The conduction band &

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Example: Case-2:- EG for Ge at 0°K = 0.785eV. Calculate EG When T = 0°K& if E > EF, the exponential at T = 350°K. term becomes infinite andf(E) = 0. Solution: It means at all energy levels above EF the Given, EGO = 0.785eV probability of finding an electron is 0 atT = 4 EGat T 350°K  EGO  2.2  10 350 0°K . Case-3 0.785  2.2  104  350  0.708eV When T = 0°K& if E > EF, the exponential term becomes zero andf(E) = 1. 1.3.3 INSULATORS It means at all energy levels below EF the probability of finding an electron is 1 at T = An insulator has an energy band diagram 0°K as shown in the Fig. In case of such A plot of f(E) versus E − E is shown in fig insulating material; there exists a large F forbidden gap in between the conduction band and the valence band. Practically it is impossible for an electron to jump from the valence band to the conduction band. Hence such materials cannot conduct and called insulators. The forbidden gap is very wide, approximately of about 5 eV.

1.4 FERMI DIRAC FUNCTION

The equations for f(E) is called the Fermi– 1.5 CLASSIFICATION OF SEMICONDUCTORS Dirac probability function, and specifies the fraction of all states at energy E (electron Based on the composition, semiconductors volts ) occupied under conditions of are classified into two types thermal equilibrium 1 1.5.1 INTRINSIC SEMICONDUCTOR fE  1exp[ EE/ kT]F In silicon each atom contains 4 valency Where, electrons hence stability is aquired by each k = Boltzmann constant, eV/°K atom in the material through sharing of T = Temperature in °K valency electrons. The bonds formed through sharing of electrons in EF =Fermi level or characteristic energy in eV semiconductor are called covalent bonds. An intrinsic semiconductor also called Def: The Fermi level represents the energy an undoped semiconductor or I–type state with 50 percent probability of being semiconductor is a pure semiconductor filled (i.e. 50% probability of finding an without any significant dopant species electron at this energy level) if no present. The bond structure of silicon is forbidden band exists. shown in the fig. Case-1 1 If E = EF then fE   for any value of 2 temperature

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 3 2 2πmkTn N2C  2 which is called the h effective density of states function in the conduction band. mnis called effective mass of electron. k is called Boltzmann's constant k 1.3oul/K8110 23 j es o The concentration of hole in valence band can be expressed as o At a very low temperature 0 K no free pNexpEE/  kT electrons are available for conduction V FV hence intrinsic semiconductor behaves as 3 2πmkT 2 perfect insulator. With the increase in Where, N2 p which is called V 2 temperature, the covalent bonds are h broken and electron hole pairs are the effective density of states function in generated. Such a generation of electron the valence band.mpis called effective mass hole pairs due to thermal energy is called of hole. thermal generation. With the generation electron hole pairs an intrinsic 1.5.12 FERMI LEVEL semiconductor starts conducting. Note:-In intrinsic semiconductor electron The Fermi level for an intrinsic concentration is equal to hole semiconductor is given by concentration i.e. EENCV kT C EF ln …(1) npni 22N V niis called intrinsic carrier concentration & If the effective masses of a hole and a free it is given by electron are the same i.e. mp=mn then NC = n23 A T eEG0/kT i0 NV, At room temperature, EECV 13 EF  ni = 2.5 × 10 Atoms/cm3 for Germanium 2 10 ni = 1.5 × 10 Atoms/cm3 for Silicon Putting T = 0°K in above equation we may observe that equation (1) is also valid even Where, for NC ≠ NV . Hence the Fermi level lies in

A0 is material constant the center of the forbidden energy band. o EG0isEG at T = 0 K k is Boltzmann’s constant k = 8.6 × 10−5eV/oK

1.5.11 ELECTRON & HOLE CONCENTRATION

The concentration of electrons in the conduction band can be expressed as

nN expEE/C  kT CF Where, Example For a particular semiconductor material, 18 −3 NC = 1.5 × 10 cm , NV = 1.3 × 19 −3 10 cm andEG = 1.43 eV at T = 300°K

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Determine the position of the intrinsic Fermi level with respect to the center of the band gap. Solution

EENCV kT C EF ln 22N V EE E  CV midgap 2

kT NC EF E midgap ln When donor impurities are added to a 2NV 18 semiconductor, allowable energy levels are 0.0259 1.5 10 introduced just below the conduction band, EEF midgap   In19 2 1.3 10 as shown in fig. These new allowable levels  0.028eV are essentially a discrete level because the Thus the Fermi level is located at 0.028 eV added impurity atoms are far apart in the above the center of the band gap. crystal structure, and hence their interaction is small. In germanium, the 1.5.2 EXTRINSIC SEMICONDUCTOR distance of the new discrete allowable energy level is only 0.01 eV (0.05 eV in silicon) below the conduction band, and therefore at room temperature almost all of the “fifth” electrons of the donor material are raised into the conduction band. If intrinsic semiconductor material is “doped” with n-type impurities, not only does the number of electrons increase, but the number of holes decrease below that 1.5.2.1 N-TYPE SEMICONDUCTOR which would be available in the intrinsic semiconductor. The reason for the decrease When a small amount of penta-valent in the number of holes is that the larger impurity is added to a pure semiconductor, number of electrons present increases the it is called N-type semiconductor. The rate of recombination of electrons with impurity atoms will displace some of the holes. silicon atoms in the crystal lattice. Four of the five valence electrons will occupy Note: covalent bonds, and the fifth will be 1) Donor impurity concentration in an N- nominally unbound and will be available as type semiconductor is given by a carrier of current. The energy required to N = Atomic density in semiconductor detach this fifth electron from the atom is D of the order of only 0.01 eV for Ge or 0.05 × Impurity ratio eV for Si. Where, Atomic density = 4.422 X 1022 atmos/ Suitable penta-valent impurities are cm3 antimony, phosphorous, and arsenic. Such For Germanium 22 impurities donate excess (negative) Atomic density = 5 X 10 atmos/ cm3 electron carriers, and are therefore For Silicon referred to as donor or n-type impurities. 2) The electrons in N-type SC are called majority charge carriers & holes are called as minority charge carriers.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Consider the formation of p-type material 1.5.2.11 FERMI LEVEL by adding boron into silicon (Si). The Boron atom has three valence electrons. So Boron atom fits in the silicon crystal in such a way that it’s three valence electros from covalent bonds with the three adjacent silicon atoms. Being short of one electron, the fourth covalent bond in the valence shell is incomplete. The resulting vacancy is called a hole. Such p-type material formation is represented in the Fig .This means that each gallium atom added into The Fermi level for N-type semiconductor silicon atom gives one hole. The number of lies near the conduction band. The position such holes can be controlled by the amount of Fermi level is given by the equation of impurity added to the silicon. As the NC EEkTFC lneV holes are treated as positively charged, the ND material is known as p-type material. With increase in doping the Fermi level At room temperature, the thermal energy is shifts towards conduction band i.e. shift sufficient to extract an electron from the upward with respect to the Fermi level of neighboring atom which fills the vacancy in intrinsic semiconductor. This upward shift the incomplete bond around impurity is given by atom. But this creates a vacancy in the

ND adjacent bond from where the electron had EEkTFFi lneV ni jumped, which is nothing but a hole. This With increase in temperature the Fermi indicates that a hole created due to added level of N-type semiconductor shifts impurity is ready to accept an electron and towards Fermi level of intrinsic hence is called acceptor impurity. semiconductor & at a very high Note: temperature it coincides with EFi i.e. at this temperature N-type semiconductor 1) Acceptor impurity concentration in an behaves as an intrinsic semiconductor. P-type semiconductor is given by NA =Atomic density in semiconductor × 1.5.2.2 P-TYPE SEMICONDUCTOR Impurity ratio Where, When a small amount of trivalent impurity Atomic density = 4.422×1022atmos/cm3 is added to a pure semiconductor, it is for Germanium called P-type semiconductor. The Atomic density = 5 X 1022atmos/cm3 for trivalent impurity has three valence Silicon electrons. The examples of such elements 2) The holes in P-type SC are called are gallium, boron or indium, such an majority charge carriers & electrons are impurity is called acceptor impurity. called as minority charge carriers.

1.5.2.21 FERMI LEVEL

The Fermi level for P-type semiconductor lies near the valence band. The position of

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Fermi level is given by the equation

NV EEkTFV lneV NA

1.6.1 EFFECT OF TEMPERATURE

At any temperature above absolute zero, the vibrating atoms create pressure (acoustic) waves in the crystal, which are termed phonons. Like electrons, phonons can be considered to be particles. A phonon With increase in doping the Fermi level can interact (collide) with an electron (or shifts towards valence band i.e. shift hole) and scatter it. At higher temperature, downward with respect to the Fermi level there are more phonons, therefore of intrinsic semiconductor. This downward increased phonon scattering which tends to shift is given by reduce mobility i.e. with increase in NA temperature mobility of charge carriers EEkTFiF lneV ni decreases. With increase in temperature the Fermi level of P-type semiconductor shifts 1.6.2 EFFECT OF DOPING towards Fermi level of intrinsic semiconductor & at a very high Semiconductors are doped with donors temperature it coincides with EFi i.e. at this and/or acceptors, which are typically temperature p-type semiconductor ionized, and are thus charged. The behaves as an intrinsic semiconductor. Columbic forces will deflect an electron or hole approaching the ionized impurity. This 1.6 MOBILITY OF CHARGE CARRIERS is known as ionized impurity scattering. The amount of deflection depends on the Consider a material is subjected to an speed of the carrier and its proximity to the external electric field E Volts/m. As a result ion. The more heavily a material is doped, of electrostatic force, the charge carriers the higher the probability that a carrier will start moving in a definite direction. The collide with an ion in a given time, and the velocity of these charge carriers is called smaller the mean free time between drift velocity. This velocity of charge collisions, and the smaller the mobility i.e. carriers is directly proportional to the with increase in doping the mobility of applied electric field charge carries decreases.

vEvdd μE Where μ is constant of proportionality and Example is called mobility of the electrons. This is A bar of silicon 1 cm long is subjected to a applicable to the free electrons as well as potential difference of 20 v. If the velocity the holes. of electrons in bar is 250m/s. Determine So in general, the mobility of electrons. Mobility of a charged particle Solution v m2 μ  d Given, E V sec 1cm  1  102 m At room temperature the mobility of V 20volts electrons and holes are

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission V 2 5 0 m/s e c NnD  We know, ν Mobility μ  Case-2 E In p-type material, ND = 0 and the number V20 of electrons is much less than number of electric fieldE  110 2 holes i.e. n<

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 1.9 CONDUCTIVITY P = Concentration of holes in n-type material. Conductivity of a material is defined as the We know, product of carrier concentration, charge of But the concentration of holes in a n-type carriers & their motilities. semiconductor is very less as compared to conductivity(σ) = charge carrier the concentration of free electrons i.e. concentration × charge of carriers × Pn. Hence neglecting P we can write mobilty nn n σ n μ q σ nqμnp pqμ siemens / m nn Now practically all the donor atoms added 1.9.1 CONDUCTIVITY OF INTRINSIC release their fifth electron as a free electron SEMICONDUCTOR at room temperature. Hence concentration of donor atoms (푁퐷) added is We know that, approximately equal to the concentration σ n μ p μ q of free electrons in n-type material (푛푛) i.e.   np nN But in intrinsic semiconductor, the electron nD Hence conductivity of n-type material is, hole pairs are generated and at any instant σ N μ q number of free electrons is same as nDn number of holes. Note: With increase in temperature the mobility of charge carriers decreases by i.e. n p n i large value in a doped semiconductor, Substituting in above equation, hence conductivity of N-type semiconductor σniinp qμμ  …… (1.17) decrease with temperature i.e. conductivity Where σi is conductivity of intrinsic in N-type semiconductor has negative semiconductor. coefficient of temperature. Note: With increase in temperature, mobility of electrons & holes decreases but 1.9.3 CONDUCTIVITY OF P-TYPE at the same time there is large increase in SEMICONDUCTOR electron &hole concentration hence the conductivity of intrinsic semiconductor In p-type of material, the holes are majority increases with temperature i.e. carriers and the free electrons are minority conductivity of intrinsic semiconductor has carriers. When acceptor impurity is added positive coefficient of temperature. to the intrinsic semiconductor, acceptor atom accepts an electron to become 1.9.2 CONDUCTIVITY OF N-TYPE negatively charged ion. SEMICONDUCTOR Let NA = Concentration of acceptor atoms In n-type of material, the free electrons are np = Concentration of free electrons in p- majority carriers and the holes are type material minority carriers. When donor impurity is PP = Concentration of holes in p- type added to the intrinsic semiconductor, material donor atom donates electron to the We know, conduction band and becomes positively charged ion. But the concentration of electrons in p-type Let materials is very much less as compared to the concentration of holes i.e. nP. ND = Concentration of donor atoms pP n = Concentration of free electrons in n- Hence neglecting np we can write, type material σp P P μ p q

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Now practically all the acceptor atoms added accept the electron and produce 1.10.2 RESISTIVITY OF N-TYPE hole. Hence concentration of acceptor SEMICONDUCTOR atoms (NA) is approximately equal to the concentration of holes in P-type material For N-type semiconductor conductivity is

(PP) i.e. PNPA given by Hence conductivity of p-type material is, σ NnDn μ q σ N μ q 1 pAp ρ Note: With increase in temperature the NqDnμ mobility of charge carriers decreases by Note: Resistivity of N-type semiconductor large value in a doped semiconductor, has positive coefficient of temperature. hence conductivity of P-type semiconductor decrease with temperature i.e. conductivity 1.10.3 RESISTIVITY OF P-TYPE in P-type semiconductor has negative SEMICONDUCTOR coefficient of temperature. For N-type semiconductor conductivity is Example given by Find conductivity of N-type Semiconductor 18 with Donor impurity concentration 10 1 atoms/ cm3 & mobility of electrons ρ N μq 3 8 0 0 c m2 / v s e c Ap Solution: Note: Resistivity of P-type semiconductor Given, has positive coefficient of temperature. N10atoms/ 18 cm 3 D 1.11 RESISTANCE 2 μ3800cm/n  vsec

σNqμ Dn Resistance of a material is defined as 101.610380018 19 R ρl /AΩ  608s/m Where, ρ is the resistivity of material l is the length of material 1.10 RESISTIVITY A is cross-sectional area of the material Resistivity is the reciprocal of conductivity Example i.e. A bar of intrinsic silicon has a cross 1 ρΩm sectional area of2.5 × 10−4m2. The electron σ density is 1.4 × 1016/m3. How long the bar be if I=1.2mA when 9 volts is applied 1.10.1 RESISTIVITY OF INTRINSIC across it. The mobility of electros & holes SEMICONDUCTOR are 0.14m2 / vsec &0.05m2 / vsecresp. For intrinsic semiconductor conductivity is Solution: given by We know that, V9 R  3 7.5kΩ σi n i q μ n μ p 3 I 1.2 10 1 Now, ρ R  ρ nqiμμ n p  A Note: Resistivity of intrinsic semiconductor has negative coefficient of temperature.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 1 in electron concentration i.e. there exist a ρ  푑푛 concentration gradient . Due to such nqinp μμ 푑푥 1 concentration gradient, electrons move  1.4101.6100.140.0516 19  from the higher concentration area to the lower concentration area to adjust the 2 3 4 9 . 6 2Ωm concentration. Such a movement of RA75002.510 4  electrons, due to the concentration ρ2349.62 gradient in a semiconductor is called  0 . 7 9 mm diffusion. Due to the movement of electrons, current is constituted in a bar 1.12 CONDUCTANCE which is called diffusion current. This is the characteristic of semiconductors and Conductance of the material is the cannot be observed in conductors. reciprocal of its resistance i.e. G 1/ R 1.13.21 DIFFUSION LENGTH ⟹ G A/ ρl ⟹ G  σ A/ l Diffusion length is the average length a Where, carrier moves between generation and 𝜎 is the conductivity of material recombination. Mathematically it is given 푙 is the length of material by LD τ A is cross sectional area of the material Where, D is diffusion constant 1.13 CURRENT DENSITY 휏is minority carrier lifetime Note: The current density J is defined as the 1) Minority carrier lifetime is the average current per unit area of the conducting time between generation & medium. recombination of minority charge I carriers JAmp / m 2 A 2) Semiconductor materials that are heavily doped have greater 1.13.1 DRIFT CURRENT recombination rates and consequently, have shorter diffusion lengths. When conductor is subjected to an external 3) Higher diffusion lengths are indicative voltage, free electrons move from negative of materials with longer lifetimes, and to positive terminal & holes moved from are therefore an important quality to positive to negative terminal with a steady consider with semiconductor materials. velocity constituting a current. Such a current is called drift current which is due 1.13.3 DRIFT CURRENT DENSITY to drifting under the effect of external voltage. The drift current density is expressed as, J  σE Where, 1.13.2 DIFFUSION CURRENT 𝜎is conductivity and is measured in Ωm 1 Consider a semiconductor, along its length, in the direction of x as shown in fig; there E is applied electric field expressed in V/m decrease in the concentration of electrons. 1) Electron drift current density is given As we move from x1 to x2 there is decrease by Jnn nqμE

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 2) Hole drift current density is given by Calculate the diffusion current in a piece of

J ppp q μE germanium having concentration gradient 22 4 2 of 1 . 5 1 0 electrons/ m & Dn 0 . 0 0 1 2 m / s 1.13.4 DIFFUSION CURRENT DENSITY Solution

dn 2 The diffusion current density is JqDamp/m n  d proportional to the concentration gradient x dp dn 1.6100.00121.51019 22 i.e. J  & J  p dx n dx  2 . 8 8 A/ m 2 Where, Jp is diffusion current density due to 1.14 EINSTEIN’S RELATION holes It states that, at thermal equilibrium, the Jn is diffusion current density due to electrons ratio of diffusion constant to the mobility is constant. This is Einstein’s relation. 1) The hole diffusion current density is Mathematically it is expressed as, DpDn given by,  kTV dp μμ T J q D pn ppdx where, T is the temperature in °퐾 where, Dp is diffusion constant for holes k is Boltzmann’s constant expressed in m2/sec 8 . 6 2 1 0 e V/°5 K

2) The electron diffusion current density is VT is called thermal voltage given by, T dn VT  JqDnn 11600 dx At T=300oK, where, Dn is diffusion constant for 300 electrons expressed in m2/sec V0.0256V26mV T 11600 1.13.5 TOTAL CURRENT DENSITY 1.15 ELECTRIC FIELD The drift current is due to the applied When a potential difference is applied voltage while the diffusion current is due across a material, a force acts on the charge to the concentration gradient & in carriers due to which electrons & holes semiconductor it is very much possible that move in the material i.e. a current flows both the types of currents may exist through the material, this force on charge simultaneously. carriers is called electric field intensity. Total current density due to the electrons is dn Mathematically it is given by J nqμ E qDn dV nn dx E  V/ m And total current density due to the hoes is, dx dp J pqμ E qDp pp dx

Example Note: In a material with uniform doping & uniform cross-sectional area the electric field is same at any point on the material

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission and the magnitude this electric field can be bottom surfaces of the material called Hall calculated using equation voltage & mathematically its is given by voltageapplied BI E  V  lengthofmaterial H ρw Where, ρ is called charge density 1.16 HALL EFFECT 1 ρ  chargeqcarrierconcentration(norp)  If specimen (metal or semiconductor ) The reciprocal of charge density is called carrying a current I is placed in a hall coefficient. transverse magnetic field B, an electric I field 퐸 is induced in the direction R H  perpendicular to both I and B. This ρ phenomenon is known as the Hall Effect. Applications: 1) It is used to determine whether a semiconductor is n-or p–type. (Type of material is determine by observing the polarity of hall voltage) 2) It is used to find the carrier When a current carrying material is placed concentration. in transverse magnetic field, a force acts on (Carrier concentration (n or p) the charge carriers called Lorentz’s force 1/ (R q)H ) given by 3) It is used to determine the mobility of Fq(vB) charge carriers using equation μ = σ × −19 where, q is charge of carriers(1.6 × 10 C) RH. v is velocity of charge carriers(m/s) 4) It is used to calculate magnetic flux B is magnetic flux density (Tesla or density. weber/m2)

The force acting on holes is Fq(vB)pp  Example For the given direction of current and Consider a rectangular cross –sectional magnetic field the direction of (v × B) is semiconductor bar with lengthl = 12mm, p width w = 5mm and thickness d = 4mm downward (direction of v is same as the p which is placed in the coordinate system as direction of current) using right hand rule. shown in fig. The positive and negative Hence the direction of force on hole is also terminals of a battery of voltage Vd = 5V downward. are connected between the two cross– The force acting on electrons is sectional surface of the bar at x = 0 and x = 3 Fq(vB)nn  l respectively. A magnetic field B = 6 × 10 For the given direction of current and Gauss is applied perpendicular to the bar magnetic field the direction of (vn × B) is along the +z-direction. If the bar is of n- upward (direction of vn is opposite to that type semiconductor with electron 15 −3 of current) using right hand rule. But as concentration nn = 2.5 × 10 cm and the electrons are negatively charged carriers, current flowing through the bar is I = the direction of force on electrons is also 10mA , determine the magnitude and downward. polarity of the Hall voltage between the Due to displacement of charge carriers in terminal 1 and 2. Also find the value of the the downward direction, a potential Hall coefficient. difference is developed across the top &

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission The negative sign in the value of Hall coefficient indicates that the sample used for Hall measurement is an n-type semiconductor.

Solution 1.17 PROPERTIES OF GERMANIUM & Since the semiconductor is of n-type with SILICON 153  n 2n . 5 1 0 c m , the charge density 𝜌is Property Ge Si given by Atomic number 32 14 19 153 3 22 22 ρqn1.6010C2.510cm  n  Atoms percm 4.42 × 10 5 × 10 43 EGOat 0°K 0.785eV 1.21 eV   4 . 0 1 0 / C c m 3 13 10 niat 300°Kpercm 2.5 × 10 1.5 × 10 The negative sign is used to denote that the Intrinsic resistivity 45 2.3 × 105 type of majority carrier involved in the at 300°KinΩ − cm 2 conduction of current in the semiconductor μncm /V − sec 3800 1300 2 is electron. μpcm /V − sec 1800 500 2 Substituting the values of Dncm /sec 99 34 D cm2/sec 47 13 I 1 0 1 0 A , 3 p 8 3510Wbwb  B610Gauss 22610 cm cm

ρ4.010C / cm42 andw510cm 1 in Eq; the magnitude of the Hall voltage is given BI by V3.010V3.0mV 3 H ρw Since the direction of applied electric field is in the +X direction, the velocity of the electron v must be in the – X direction. Thus, the direction of deflection of the electrons can be determined as follows. Let the magnetic field and velocity of electrons in the bar be expressed as

B Bzandve   vx Where x̂ and ẑ are the unit vectors along the +X and+Z directions. Thus the force acting on an electron is given by

Fee e B  v   eBv  z  x   eBv   y  Where ŷ is the unit vector in the +Ydirection. Since the force is acting on the electron in the – y direction, the polarity of the Hall voltage at terminal 1 is negative with respective to the terminal 2. Using Eq. the Hall coefficient can be obtained as 11 R    2.5  1033 cm / C H ρ 4.0 1043 C / cm

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission GATE QUESTIONS

Q.1 n-type silicon is obtained by doping a) Diffusion current silicon with b) Drift current a) Germanium b)Aluminum c) Recombination current c)Boron d)Phosphorous d) Induced current [GATE-2003] [GATE-2006]

Q.2 The band gap of silicon at 300K is Q.7 The majority carriers in an n-type a)1.36eV b)1.10 eV semiconductor have an average drift c)0.80 eV d)0.67 eV velocity V in a direction perpendicular [GATE-2003] to a uniform magnetic field B .The electric field E induced due to Hall Q.3 The intrinsic carrier concentration effect acts in the direction of silicon sample of 300K is 1.5 x a) VB× b) BV× 1016/m3. If after doping, the number c) along V d)opposite to V of majority carriers is 5x1020/m3, [GATE-2006] the minority carrier density is a) 4.50× 1011 / m 3 b) 3.33× 1043 / m Q.8 A heavily doped n-type 10−5 semiconductor has the following c) 5.00× 1020 / m 3 d) 3.00× data Hole-electron mobility ratio: m3 0.4 Doping concentration: 4.2× 8 [GATE-2003] 10 atoms/m 4 Q.4 The impurity commonly used for Intrinsic concentration:3 1.5 ×10 realizing the base region of a silicon atoms/m n-p-n transistor is The ratio3 of conductance of the n- a)Gallium b)Indium type semiconductor to that of the c)Boron d)Phosphorus intrinsic semiconductor of same [GATE-2004] material and at the same temperature is given by Q.5 The concentration of minority a) 0.00005 b) 2,000 carriers in an extrinsic semiconductor c) 10,000 d) 20,000 under equilibrium is [GATE-2006] a) Directly proportional to the doping concentration Q.9 The electron and hole concentration b) Inversely proportional to the in an intrinsic semiconductor are ni doping concentration per cm3 at 300 K. Now, if acceptor c) Directly proportional to the impurities are introduced with a intrinsic concentration concentration of N per cm3 (where d) Inversely proportional to the ? ,the electron concentration NAi )n A intrinsic concentration per cm at 300 K will be [GATE-2006] 3 a) ni b) nNiA+ Under low level injection n2 Q.6 c) Nn− d) i assumption, the injected minority Ai Na carrier current for an extrinsic [GATE-2007] semiconductor is essentially the

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.10 Which of the following is true? c) Epitaxial deposition a) A silicon wafer heavily doped d) ion implantation with boron is a p+ substrate [GATE-2010] b) A silicon wafer lightly doped + Statement for Linked Answer with boron is a p substrate Questions 15 & 16 c) A silicon wafer heavily doped The silicon sample with unit cross- + with arsenic is a p substrate sectional area shown below is in d) A silicon wafer lightly doped thermal equilibrium. The following with arsenic is a p+ substrate information is given : T=300K, −19 [GATE-2008] electronic charge =1.6 × 10 C , thermal voltage =26 mV and Q.11 Silicon is doped with boron to a electron mobility=1350 cm2 / V− s concentration of 4× 1017 atoms / cm 3 . Assume the intrinsic carrier concentration of silicon to be kT 1.5× 1010 / cm 3 and the value of q to be 25 mV at 300 K. Compared to un doped silicon, the Fermi level of Q.15 The magnitude of the electric field at doped silicon. x= 0.5μm is a) goes down by 0.13 eV b) goes up by 0.13 eV a)1 kV/cm b) 5 kV/cm c) goes down by 0.427 eV c) 10kV/cm d) 26kV/cm d)goes up by 0.427 eV [GATE-2010] [GATE-2008] Q.16 The magnitude of the electron drift current density at = is Q.12 In an n-type silicon crystal at room x 0.5μm temperature, which of the following a) 2.16× 1042 A / cm can have a concentration of b) 1.08× 1042 A / cm 4× 1019 cm− 3 ? 103 A c) 4.32× a)Silicon atoms cm2 b)Holes 102 A c)Dopant atoms × d) 6.48 2 d)Valence electrons cm [GATE-2009] [GATE-2010]

Q.13 The ratio mobility to the diffusion Q.17 Drift current in semiconductors coefficient in a semiconductor has depends upon the units a) Only the electric field − b) Only the carrier concentration a) V-1 b) cm.V 1 gradient c) −1 d) V.cm V.s c) Both the electric field and the [GATE-2009] carrier concentration d) Both the electric field and the Thin gate oxide in a CMOS process is Q.14 carrier concentration gradient preferably grown using [GATE-2011] a) Wet oxidation b) dry oxidation

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.18 In IC technology, dry oxidation electrons injected into a P-type (using dry oxygen) as compared to silicon sample is 1x1021/cm4, the wet oxidation (using steam or water magnitude of electron diffusion vapor) produces current density (in A/cm2) is______. a) Superior quality oxide with a [GATE-2014] higher growth rate b) Inferior quality oxide with a Q22 When a silicon diode having a higher growth rate doping concentration of NA= 9 x c) Inferior quality oxide with a 1016 cm-3 on p-side and = 1 x 1016 lower growth rate cm-3 on n-side is reverse biased, the d) Superior quality oxide with a total depletion width is𝑁𝑁 found𝐷𝐷 to be lower growth rate 3 m Given that the permittivity of [GATE-2013] silicon is 1.04 x 10 F/cm, the depletion𝜇𝜇 width on the−12 p-side and Q.19 The doping concentrations on the p- the maximum electric field in the side and n-side of a silicon diode are depletion region, respectively, are 1× 1016cm-3 and 1 × 1017cm-, a) 2.7 m and 2.3 x 105 V/cm respectively. A forward bias of 0.3 V b) 0.3µm and 4.15 x 105 V/cm is applied to the diode. At T = 300K, c) 0.3µm𝜇𝜇 and 0.42 x 105 V/cm the intrinsic carrier concentration of d) 2.1 µm and 0.42 x 105 V/cm silicon =1.5×1010 cm-3 and = [GATE-2014] kT 26mV. The electron Concentration 𝑛𝑛𝑖𝑖 q Q.23 A thin P-type silicon sample is at the edge of the depletion region uniformly illuminated with light on the p-side is which generates excess carriers. The 9 -3 16 -3 a) 2.3 x 10 cm b) 1 ×10 cm recombination rate is directly 17 -3 6 -3 c) 1 ×10 cm d) 2.25 × 10 cm proportional to [GATE-2014] a) The minority carrier mobility b) The minority carrier Q.20 A silicon bar is doped with donor recombination lifetime 15 impurities ND =2.25x10 atoms/ c) The majority carrier concentration 3. cm Given the intrinsic carrier d) The excess minority carrier concentration of silicon at T = 300 K concentration is ni = 1.5 x 1010 cm-3. Assuming [GATE-2014] complete impurity ionization, the equilibrium electron and hole Q.24 At T = 300 K, the band gap and the concentrations are intrinsic carrier concentration of 16 -3 5 - a) n0=1.5x10 cm , po=1.5x10 cm GaAs are 1.42 eV and 106 cm-3, 3 respectively. In order to generate 10 -3, 15 - b) n0=1.5x10 cm po=1.5x10 cm electron hole pairs in GaAs, which 3

one of the wavelength ( Rc) ranges of 15 - 10 -3 c)n0=2.25x10 cm 3,po=1.5x10 cm incident radiation, is most suitable? 15 -3 5 -3 d) n0=2.25x10 cm , po=1x10 cm (Given that: Plank's constant𝜆𝜆 is 6.62 [GATE-2014] x 10-34 J-s, velocity of light is 3 × 1010 cm/s and charge of electron is Q.21 Assume electronic charge q = 1.6 x 10-19C) 1.6x10-19C, kT/q = 25 mV and a) 0.42 μm< λ c < 0.87 µm electron mobility . = 1000 cm2/V-

b) 0.87 µm < Rc < 1.42 µm s. If the concentration gradient of 𝜇𝜇𝑛𝑛 λ

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission c) 1.42 µm < Rc < 1.62 µm

d)1.62 µm < Rc < 6.62 µm λ [GATE-2014] Q.25 In the figureλ ln( ) is plotted as a function of 1/T, where the If Ec is the lowest energy level of the 𝑖𝑖 intrinsic resistivity𝜌𝜌 of silicon, T conduction band, Ev is the highest is the temperature, and the 𝜌𝜌plot𝑖𝑖 is energy level of the valance band almost linear. and E is the Fermi level, which one of the following represents the energyF band diagram for the biased N-type semiconductor? a) b)

The slope of the line can be used to estimate a) Band gap energy of silicon (Eg) c) d) b) Sum of electron and hole mobility in silicon ( + ) c) Reciprocal of the sum of electron n p and hole μmobilityμ in silicon ( -1 [GATE-2014-4] μμnp+ ) d) Intrinsic carrier concentration of Q.29 A silicon sample is uniformly doped silicon (ni) with donor type impurities with a [GATE-2014] concentration of 1016 / cm 3 . The electron and hole mobilities in the The cut-off wavelength (in m) of Q.26 sample are 1200 cm / V– s and light that can be used for intrinsic 400cm2/V–s respectively.2 Assume excitation of a semiconductorμ complete ionization of impurities. material of bandgap Eg= 1.1 eV The charge of an electron is 1.6 is______. ×10−19 C. The resistivity of the [GATE-2014-4] – cm) is ______. Q.27 Consider a silicon sample doped [GATE-2015-1] with ND = 1x1015/cm3 donor atoms. sample (in Ω A piece of silicon is doped uniformly Assume that the intrinsic carrier Q.30 with phosphorous with a doping concentration ni=1.5x1010/cm3. If concentration of 10 /cm . The the sample is additionally doped expected value of mobility16 3 versus with NA = 1x1018/cm3 acceptor atoms, the approximate number of doping concentration for silicon assuming full dopant ionization is electrons/cm3 in the sample, at shown below. The charge of an T=300 K, will be ______. electron is 1.6 × 10 C. The [GATE-14-4] conductivity (in S cm−19) of the silicon sample at 300 K is−1 ______. Q.28 An N-type semiconductor having uniform doping is biased as shown in the figure.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 10 cm & 1000 cm V s , respectively16 −3 . The average2 time−1 −1(in s) taken by the electrons to move from one end of the bar to other end isμ ______.

[GATE-2015-2] [GATE-2015-2] Q.31 An n+type silicon sample is Q.34 A small percentage of impurity is uniformly illuminated with light added to an intrinsic semiconductor which generates 1020 electron hole at 300 K. Which one of the following pairs per cm3 per second. The statements is true for the energy minority carrier lifetime in the band diagram shown in the sample is 111,s . Int eh steady state, following figure? the hole concentration in the sample is approximately 10' , where x is an integer. The value of x is [GATE-2015-2] Q.32 The energy band diagram and electron density profile n(x) in a semiconductor are shown in the

qax −3 a) Intrinsic semiconductor doped cm figure. Assume that n(x)= 1015 ekT with pentavalent atoms to form , with = 0.1V / cm and x expressed n-type semiconductor kT b) Intrinsic semiconductor doped in cm. Given = 0.026V, D =36 α q with trivalent atoms to form n- type semiconductor D kT n cm s ,& = . The electron c) Intrinsic semiconductor doped 2 −1 μ q with pentavalent atoms to form current density (in A / cm ) at x = 0 is p-type semiconductor 2 d) Intrinsic semiconductor doped with trivalent atoms to form p- type semiconductor [GATE-16-1]

Q.35 The figure below shows the doping a) -4.4× 10 b) -2.2 × 10 distribution in a p-type c) 0 −2 d) 2.2 × 10 −2 semiconductor in log scale. [GATE-2015−2-2] Q.33 A dc voltage of 10V is applied across an n-type silicon bar having a rectangular cross-section & a length of l cm as shown in figure. The donor doping concentration N and the mobility of electrons are D μn

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission The magnitude of the electric field d) Silicon atoms act as n-type (in kV/cm) in the semiconductor dopants in Arsenic as well as due to non uniform doping is Gallium sites ______. [GATE-16-1] [GATE-2017-1]

Q.36 Consider a silicon sample at Q.38 As shown a uniformly doped Silicon T=300K, with a uniform donor (Si) bar of length L = 0.1 with a 16− 3 16 -3 density Nd ×= 10 m5c illuminated donor concentration ND = 10 cm uniformly such that the optical is illuminated at x = 0 such that generation rate is electron and hole pairs are = × 20 −− 31 throughout Gopt 1.5 10 cm s generated at the rate of the sample. The incident radiation is x turned off at t=0. Assume low-level GL= G L0  1 − ,0 ≤≤ x L where L injection to be valid and ignore surface effects. The carrier lifetimes GL0 = 1017cm-3s-1. Hole lifetime is are = 0.1 s and = 0.5 s 10-4s, electronic charge q = 1.6 x τp0 μ τn0 μ 10-19C , hole diffusion coefficient DP = 100cm2/s and low level injection condition prevails. Assuming a linearly decaying steady The hole concentration at t = 0 and state excess hole concentration the hole concentration at t =0.3 s, respectively, are that goes to 0 at x = L, the a) 1.5 ××1013 cm−− 3& 7.47 10 11 cm 3 μ magnitude of the diffusion current density at x = L/2, in A/cm2 is b) 1.5 ××1013 cm−− 3& 8.23 10 11 cm 3 ______. m c) 7.5 ××1013 cm−− 3& 3.73 10 11 cm 3 d) 7.5 ××1013 cm−− 3& 4.12 10 11 cm 3 [GATE-2016-1]

Q.37 A bar of Gallium Arsenide (GaAs) is doped with Silicon such that the [GATE-2017-1] Silicon atoms occupy Gallium and Arsenic sites in the GaAs Q.39 The dependence of drift velocity of crystal. Which one of the electrons on electric field in a following statement is true? semiconductor is shown below. The semiconductor has a uniform a) Silicon atoms act as p-type dopants in Arsenic sites and n- electron concentration of n = 1 x type dopants in Gallium sites 1016cm-3 and electronic charge q = b) Silicon atoms act as n-type 1.6 x 10-19C. If a bias of 5V is applied dopants in Arsenic sites and p- across a 1 region of this type dopants in Gallium sites semiconductor, the resulting c) Silicon atoms act as p-type current density in this region, in dopants in Arsenic as well as kA/cm2, is ______. Gallium sites

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission [GATE-2017-1]

Q.40 A junction is made between p- Si with doping density NA1 = 1015 cm-3 and p Si with doping density NA2 = 1017cm-3

Given: Boltzmann constant k = 1.38 × 10-23 J.K-1, electronic charge

q = 1.6 × 10-19 C. Assign 100% acceptor ionization. At room temperature (T = 300 K), the magnitude of the built-in potential (in volts, correct to two decimal places) across this junction will be_____.

[GATE-2018]

ANSWE R KEY: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (d) (b) (a) (c) (b) (a) (b) (d) (d) (a) (c) (c) (a) (b) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (c) (a) (c) (d) (a) (d) 4000 (b) (d) (a) (a) 225.2 (d) 0.52 29 30 31 32 33 34 35 36 37 38 39 40 1.92 14 (c) 100 (a) (a) (a) (a) (a) 16 1.6 0.1192

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission EXPLANATIONS

Q.1 (d) 4.2× 108 = = N-type silicon is obtained by doping 4[] 1+ 0.4 20,000 1.5× 10 silicon with a pentavalent impurity i.e. phosphorus. Q.9 (d) By the law of electrical neutrality Q.2 (b) pN+=+DA nN Q.3 (a) As N = 0 2 NAi? n≅= 0p N A ni = np D Using mass action law np= n ni = intrinsic concentration nn22 2 n2 1.5× 1016 ×× 1..5 10 16 So, n =ii = i p =i = pN n 5× 1020 A =×=×45 1010 4.5 10 11 Q.10 (a) Boron is acceptor impurity, so high Q.4 (c) concentration makes p substrate. For an n-p-n transistor, the base + region is a p type semiconductor. In Q.11 (c) the options there are 3 trivalent For p-type material , impurities but for silicon boron is +−()EE = Fi F preferred. NAi n e / KT ()EE− ⇒×4 1017 = 1.5 × 10 10 eFi F / KT Q.5 (b) EE− ⇒=Fi F 17.1 Minority concentration KT n2 ⇒ −= × = i EFi E F 17.1 25mv majority carrier concentration = 0.427eV 1 It is p-type so Fermi level goes down I,e, p ∝ h by 0.427eV

Q.6 (a) Q.12 (c) The injected minority carrier current is diffusion current and it is Q.13 (a) because of concentration gradient. D = V μ T

Q.7 (b) μ1 −1 The electric field will be ⇒= ⇒units : V DV perpendicular to both V and B, and T inB × V direction. Q.14 (b) Dry oxidation is preferred because Q.8 (d) of less contamination. σ nqμn n n = = + μ σi nqinp()μμ p Q.15 (c) n1i + μn Electric field will be constant inside sample.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission V1 Q.21 (4000) E= = = 10kV / cm d 10−6 Given q =1.6x10-19; - = 2.5 mV, . KJ 2 =1000 cm / v – s n Q.16 (a) q µ From Einstein relation, = — = Jnμn qε Dn KJ 2 16− 19 3 Dn = 25mVx1000cm / v –S = × × × ×× μn q 10 1350 1.6 10 10 10 2 42 25 cm / s =2.16 × 10A / cm ⇒ Diffuion current Density J =qDn ⇒ dn Q.17 (c) =1.6x10-19x25x1x1021 = 4000A / cm2 dx J= n eVd Put, V = μE d Q.22 (b) J = n e E Given N = 9 x1016 / cm3; N =1 x Hence, I = n e EA 1016 / cm3 So,∴ it dependsµ upon carrier Total depletionA width x=x +x D=3µm concentration andµ electric field =1.04 x 10-12F/ cm n p

= = Q.18 (d) 16 ϵxn NA 9 x10 The designed characteristics and 16 xxp= 9N xD …….(1)1 x 10 requirements of the fabricated oxide Total Depletion width, x + x = 3 µm can be mainly influenced by the n p 9 x + x = 3 µm used oxidant species. With dry n p x = 0.3µm oxidation, normally high –quality p p Max. Electric field, E = thin oxide films are produced. p qN X 1.6× 10−19 ×× 9 10 16 × 0.3μm During wet oxidation, the silicon AP= water is settled to a water vapor  1.04× 10−12 temperature .Wet oxide grow really =4.15×105V/cm fast compared to any oxidation, which is the biggest advantage. Q.23 (d) Recombination rate, Q.19 (a) '' R=++ B(nn n nn )() P P n Electron concentration, oo n & P = Electron and hole n2 ne= i Vbi /V T concentrations respectively under N no no A thermal equilibrium (1.5× 1010 ) 2 = 0.3/26mV n & P = Excess elements and hole 16 e 1× 10 concentrations′ ′ respectively = 2.3 x 109 / cm3 n n Q.24 (a) Q.20 (d) hc 6.62× 10−34 ×× 3 10 8 15 3 = ⇒= = µ ND = 2.25 x 10 Atom / cm E λ−19 0.87 m λ 1.42×× 1.6 10 h =1.5x1010 / cm3 Since complete ionization taken i Q.25 (a) place, 3 2 −Eg/kT 1 h = ND = 2.25 x1015 / cm3 n αT e and ρα i i η 10 2 i 0 n2 ()1.5× 10 =i = = × 53 From the graph, Energy graph of P0 15 1 10 / cm n0 2.25× 10 Si can be estimated ∴

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.26 (225.2) J ( )= -2.2× 10 A/cm P=NA-ND=1x1018–1x1015=9.99 −12 22 J=+= Jn()() drift J n drift 0A / cm x1017 n drift 10 2 η 2 ()1.5× 10 Q.32 (100) η=i = = 225.2 / cm3 × 17 V 10 P 9.99 10 ε= = = 10V / m d1 Q.27 (d) 4 Vd =με = 1000 ×= 10 10 cm/s L L 1× 100 Q.28 (0.52) V=⇒== T =µ 100 s d T V 1042× 10 1 1 d P = = σ Nqμ N Dn Q.33 (a) 1 New energy level is near to = − 1016×× 1.6 10 19 × 1200 conduction band, so it is pentavalent = -cm atoms to form n-type semiconductor. Q.29 (1.920.52Ω) As per the graph mobility of Q.34 (1.10 to 1.25) electrons at the concentration cm2 Q.35 (a) 10 /cm is 1200 Vs− n 2 2.25× 1020 16 3 P =i = = 0.5× 10 /cc cm2 n0 N 5× 1016 So, =1200 D 4 20− 6 3 Vs− →∆PG =τp0 =1.5 × 10 × 10 × 0. 1 = 1.5 × 10 / cc n µ= N q −t = 10 ×1.6 × 10 × 1200 ∆=∆P() t pe τp n D n =σ 1.9216 S cmµ −19 PP()()()=∆+PtPt n0 ≈∆ t −1 13 Q.30 (14) ∆P() 0 =∆= P 1.5 × 10 / cc The concentration of hole-electron ∆==×P() t 3 7.47 1011 / cc pair in lvt sec =1020 x 10-6 = 1014/cm3 So, the power of 10 is 14. Q.36 (a) x =14 Given = 20 3 Q.31 (c) Gopt 1.5x10 / cm / sec dn(x) N J (diff) = qD A GRopt = = dx τp n n qax 15 kT Given n(x) = 10 e 2 NA 1.5x10 = − d (x) 0.1x10 6 n 3.846×= 1015 cm 4 = 13 3 dx x0= NA 1.5x10 / cm

−22 −τt/ P Jn () diff= 2.2 × 10 A / cm Pt() = Pen0 −0.3 Jn() drift = n() 0 .qμEnx 13 0.1 x0= =1.5x10 e 15− 19 11 3 10×× 1.6 10×= 1384.5 × Ex = 7.46x10 / cm −kT 1 d (x) E= ..n x q n(x) dx Q.37 (a) = - = 0.1 V/cm

α −

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Silicon atoms act as P- type dopants V dP E = T in Arsenic sites and n- type dopants P dx in Gallium sites. dP dV dV=−=− V E T dx dx P V=−= V V V ln 1 Q.38 15.9-16.1 21 2 1 T  P2 L Built in potential   ∆=∆= −2 τ kT NA2 P nGL0 1 p Vbi = ln  L qNA1  1.38x3 1 = ln() 100 V =GxL0 τ p 1.6x100 2 = 0.1192V 1 =1017 x x10− 4 2 1 = x1013 / cm 3 2 dp J diff= qD PP1 dx 1 x1013 =1.6x10−19 x100 2 0.1x10−4 2 =16A / cm2

Q.39 1.5-1.7

vdn=µε v 1072 cm µ=d = 20 n ε−5x105 v sec V5 EV= = / cm d 1x10−4

Jdrift= nqv d = nq µε n

Jdrif t= nqv a = nq µεn =1016 x1.6x10− 19 x20x5x10 4 = 1.6kA / cm 2

Q.40 0.1192

Setting Jp = 0

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 2 P-N JUNCTION DIODES

2.1 JUNCTION THEORY the junction. The depletion region is also termed as space charge region. PN junction is formed in a single crystal of Figure 1: shows majority carrier diffusion semiconductor by making one end of the in pn junction crystal p-type by doping it with acceptor Figure 2: A pn junction showing depletion atom and making the other end n-type by region doping with donor atoms. The region Figure 3: Charge density on either sides of where p-type and n-type meet is the the junction junction. Figure 4: Electric field across the depletion layer Figure 5: Potential barriers

When two semiconductor material types, p-type and n-type are brought to contact, majority carrier of each type would diffuse across the junction i.e. the majority carrier hole from p-type diffuses to n-type material and the majority carrier electron from n- type diffuses to p-type material. As the majority carrier such as hole diffuses across the junction, it combines with electron in the n-type side, which creates a net positive charge. Likewise, the majority carrier electron from n-type material diffuses across the junction recombines with hole in p-type side creates net negative charge. The net charge at each side creates an electric field in the direction from N type to P type semiconductor, which would oppose further diffusion of majority charge carriers. The electric field created would drift the minority carrier in the opposite direction across the junction. Thus when equilibrium attained, the drift carriers and diffused carriers should be balanced in terms of magnitude and in opposite direction. Due to positive & negative charges on As the result of this process, a depletion either sides of depletion layer a potential is region i.e. a region of lack of carrier of developed across the depletion layer called certain thickness is created on both sides of as contact potential (Vo) or built-in

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission potential ( Vbi ) or junction potential ( Vj ). Magnitude of this contact potential depends on temperature & doping on P & N sides

NNAD VVln0T lnvolts2 ni Where,

VT is thermalvoltage o VT  26mVatT 300 K

NA isdopingon N side N isdoping on P side D The Fermi level E is closer to the n isintrinsiccarrierconcentration F i conduction band edge E in the N-type n 2.5 1013 atoms/ cm3 Cn i material (like in isolated N-type SC) and for germanium closer to the valence band edge EVp in the p n1.510atoms/10 cm 3 i side (like in isolated P-type SC). Clearly, for silicon then the conduction band edge E in the p The width of depletion layer formed near Cp the junction is of the order of material cannot be at the same level as 6 E, nor can the valence band edge E in 1 0 m 1m i c r o n & is mathematically given Cn Vn by the n side line up with . Hence the 2ε11 energy–band diagram for a p-n junction WVO appears as shown in Fig. where a shift in qNNAD energy level Eo is indicated. Note that Where, ε ε ε or EoCpCnVpVn12 =E-E=E-E=E +E

εo ispermitivityof freespace 12 2.1.2 CIRCUIT SYMBOL ε8.8510F/o  m 14 ε8.8510F/o  cm

εr isrelativepermitivityof thematerial Note: The magnitude of the electric field induced across the junction is maximum at the junction. 2.2 PN JUNCTION IN FORWARD BIAS 2.1.1 BAND STRUCTURE OF OPEN CIRCUITED PN JUNCTION When anode terminal of diode is biased at higher potential with respect to cathode When a PN junction is formed the Fermi terminal (or positive terminal of battery level must be same throughout the diode. If connected to P-side & negative terminal this were not so, electrons on one side of connected to N-side), a PN junction diode is the junction would have an average energy said to be forward biased. higher than those on the other side, and there would be a transfer of electrons and energy until the Fermi levels in the two sides did line up.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission When PN junction is forward biased the effect of electric field across the depletion layer decreases on majority charge i.e. the height of potential barrier decreases & majority charge carriers are injected to the other sides of diode i.e. holes are injected from P to N while electrons are injected When PN junction is reversed biased the from N to P. These carriers move away majority charge carriers cross the junction from the junction due to diffusion and will while majority charge carriers move away eventually recombine with majority from the junction. The reverse current in carriers of other region. Due to the applied the diode flows due to minority charge forward voltage the minority charge carriers & it is called as reverse saturation carriers move away from the junction i.e. current, minority carrier current, leakage they do not take part in conduction. current or thermally generated current. The forward current of diode If is related to IIexpV/r0 rT ηV1 the voltage Vd by the equation Normally, exp V / ηV  1 If I 0  exp Vd / ηV T  1 rT  II  0 thus the reverse current is Where, I0 is reverse saturation current V is forward voltage across diode constant & independent of the applied d reverse bias. η1 for germanium In a reverse biased PN junction, the η2 for silicon depletion layer width is given by V is thermal voltage T 2ε11 T W  (VVOr ) V  26mVatT300°K qNNAD T 11,600 i.e. W(VV ) Or As, expV/ dTηV1 Hence, the width of depletion layer in diode I=IexpV/ ηV f0dT  increases with applied reverse voltage. Note:

1) The direction of If is from P-side to N- Note: side. 1) The direction of reverse current is from 2) The width of depletion layer decreases N-side to P-side. with the increase in applied forward 2) The reverse current is basically drift voltage. current. 3) The forward current is basically diffusion current. 2.4 I-V CHARACTERISTICS

2.3 PN JUNCTION IN REVERSE BIAS

When cathode terminal of diode is biased at higher potential with respect to anode terminal (or positive terminal of battery connected to N-side & negative terminal connected to P-side), a PN junction diode is said to be reverse biase

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 1) In a forward biased PN junction the Note: The dynamic conductance of diode is current through diode increases not constant, it increases exponentially exponentially with applied forward with applied forward voltage. voltage. 2) In a reverse biased PN junction is of the 2.4.4 EQUIVALENT CIRCUITS order of neon amperes for silicon & micro amperes for germanium. 1) Forward Bias: An ideal diode in forward bias can be replaced with short

2.4.1 CUT-IN VOLTAGE ( Vγ ) circuit & a practical diode can be replaced with a battery (cut-in voltage) & a series resistance (if given). It is the minimum value of Vd for which diode enters into conduction when it is forward biased. Below the current through diode is negligibly small. V0.2Vforgermaniumdiode γ 2) Reverse Bias: An ideal diode in reverse V0.7Vforsilicondiodeγ  bias can be replaced by an open circuit & a practical diode can be replaced with a 2.4.2 DIODE RESISTANCE reverse resistance (if given).

For small –signal operation the dynamic, or incremental, resistance r is defined as the reciprocal of the slope of the volt –ampere characteristic. dV 2.5 EFFECT OF TEMPERATURE r  d dIf 1) REVERSE SATURATION CURRENT (I0): ηV r  T It increases approximately 7 percent per ℃ If rise in temperature for both silicon and Note: The dynamic resistance of diode is germanium & it approximately doubles for not constant; it decreases exponentially every 10℃ rise in temperature.

with applied forward voltage. TT21  I I 210 0T21 0T 2.4.3 DYNAMIC CONDUCTANCE where, I is reverse saturation current at 0T2

The dynamic conductance is the slope of temperature T2 volt-ampere characteristics of diode. I is reverse saturation current at 0T1 1 g  temperature T1 r 2) FORWARD VOLTAGE ACROSS DIODE dI g  f (Vd): dVd Forward voltage of diode decreases with temperature Vd Iexp0  2.1mV /℃ forGe ηV dVd  T    dT 2.3mV /℃ forSi ηVT  In general, the temperature coefficient of IIf0 If  is considered as 2.5mV /℃ ηVTT ηV

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission dV i.e. d 2 . 5 m V / ℃ As W (V V ) Or, the transition dT capacitance 1 2.6 DIODE CAPACITANCES CvT  (VV)Or Any variation of the charge within a p-n 1 Note: In general C  diode with an applied voltage variation T m (Vr ) yields a capacitance which must be added 1 to the circuit model of a p-n diode. The Where m  for step graded PN junction capacitance associated with the charge 2 1 variation in the depletion layer is called the m  for linearly graded PN junction junction capacitance or transition 3 1 capacitance or depletion capacitance, m  for diffused PN junction while the capacitance associated with the 2 . 5 excess carriers in the quasi-neutral region When no reverse voltage is applied i.e.

is called the diffusion capacitance. Both Vr 0V then the capacitance is CT0 . types of capacitance are present in the CT0 forward- and reverse-bias regions, but one CT  V dominates the other in each region that we 1 r consider the effect of only one in each Vo region. 2.6.3 DIFFUSION CAPACITANCE 2.6.1 TRANSITION CAPACITANCE If diode is forward biased, the potential A reverse bias causes majority carriers to barrier at the junction is lowered and holes move away from the junction hence the from the p side enter the n side. Similarly, thickness of the space–charge layer at the electrons from the n side move into the p junction increases with reverse voltage, side. This process is called minority- carrier thereby uncovering more immobile injection. After injection the excess electron charges. This increase in uncovered charge & hole density falls off exponentially with with applied voltage may be considered a distance. capacitive effect. We may define an With change in the applied forward voltage, incremental capacitance CT as the concentration of injected charge dQ C  particles changes which is a capacitive T dV effect & the capacitance of this kind is

The quantity CT is referred to as the called diffusion capacitance CD . It is called transition, space–charge, barrier or the diffusion or storage capacitance

depletion region capacitance. CD  τg εA C  where, g is dynamic conductance of diode T W If where, W is depletion region width g  ηVT 2 1 1 τ is minority carrier lifetime W  VVor   e NAD N τIf CD ηVT εεε 0r A is cross sectional area of diode Note: Diffusion capacitance of diode increases exponentially with applied forward voltage.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 2.7 DIODE SWITCHING However for a practical diode, this does not happen because of large number of The transient response of a diode driven minority carriers on each sides of depletion from an ON to an OFF state signifies that an layer in forward bias condition. When interval of time elapses before the diode diode is suddenly reversed biased these reaches its new steady state. Because it injected charge carriers are swept back represents an important practical limitation, across the junction to the side from which the reverse recovery i.e. switching from ON they originated. This charge motion to OFF, is described below produces a current in the reverse direction. The period of time during which these minority carriers are swept back i.e. time

between and tt s , is called the

storage time ts . During this time interval the diode conducts (i.e. offers a very low

In the forward- bias state large number of resistance rr unlike reversed biased diode) electrons from the n side injected into p & a large reverse current I V / R flows side and large number of holes injected RRL through diode i.e diode remains in ON into n side from p side. Due to this diffusion state. process, large number of minority carriers After storage time t = t (once all the will be there on either sides of the s depletion layer. In a forward biased diode injected minority carriers are swept back) the diode begins to reverse biased and the the forward resistance rd is very small as magnitude of the current decreases toward compared to RL hence the forward current I0 (i.e reverse saturation current). This through diode is IV/R .The diode is fFL time during which diode current decreases operated in the same bias for a long time from IR to is called transition interval before t0 . denoted by tr . The sum of storage time and transition interval is known as reverse

recovery time t rr for the diode.

Now, if at the polarity of the applied bias voltage is suddenly reversed to make the diode reverse biased then ideally the diode should change its condition from ON to OFF instantly. The reverse recovery time depends on the RC time constant where C is a transition capacitance of a diode. Thus to have fast switching from ON to OFF of a diode, the transition capacitance should be as small as possible. Thus the transition capacitance plays an important role in the switching circuits using diodes.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 2.8 VARACTOR DIODE A light-emitting diode (LED) is a two- lead semiconductor light source that resembles a basic pn-junction diode, except that an LED also emits light. LED is always A varactor diode is a linearly graded diode fabricated with direct band gap & always operated in a reverse- semiconductor. biased state. No current flows, but since the When an LED is forward biased, the thickness of the depletion zone varies with majority charge carriers cross the junction the applied bias voltage, the capacitance of & large no. of recombinations take place at the diode can be made to vary. the junction. Due to these recombination’s Capacitance is inversely proportional to the energy is released in the form of light. This depletion region thickness. Thus, the effect is called electroluminescence, and capacitance is inversely proportional to the the color of the light (corresponding to the root of applied voltage. energy of the photon) is determined by the 1 energy band gap of the semiconductor. CT  Eh ν 3 R.B.voltage G hc All diodes exhibit this phenomenon to EG  some degree, but varactor diodes are λ hc manufactured specifically to exploit this λ  effect and increase the capacitance (and EG thus the range of variability), whereas most 1.24 λμm ordinary diode fabrication strives to E minimize the capacitance. G where, EG is forbidden band gap of material (eV) 2.8.1 EQUIVALENT CIRCUIT ν is frequency of emitted light h is plank’s constant h6.6210m kg34 / s2 λ is wavelength in μm

2.9.1 APPLICATIONS Where, C is depletion d 1) Visual signals where light goes more or capacitance? less directly from the source to the R r is reverse resistance human eye, to convey a message or

R s is contact resistance meaning. 2) The light from LEDs can be modulated 2.8.2 APPLICATIONS very quickly so they are used extensively in optical fiber and free 1) They are used in Parametric Amplifiers. space optics communications. 2) They are used for tuning receivers. 3) LEDs are also suitable for backlighting 3) They are used as voltage controlled for LCD televisions. oscillators. 2.10 ZENER DIODE 2.9 LIGHT EMITTING DIODE The Zener diode's operation depends on the heavy doping of its p-n junction allowing electrons to tunnel from the valence band of the p-type material to the conduction

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission band of the n-type material. In the atomic conventional device, a reverse-biased scale, this tunneling corresponds to the Zener diode will exhibit a controlled transport of valence band electrons into the breakdown and allow the current to keep empty conduction band states; as a result the voltage across the Zener diode at the of the reduced barrier between these bands Zener voltage. For example, a diode with a and high electric fields that are induced due Zener breakdown voltage of 3.2 V will to the relatively high levels of doping on exhibit a voltage drop of 3.2 V even if both sides. reverse bias voltage applied across it is more than its Zener voltage.

2.10.1 ZENER BREAKDOWN

Zener breakdown occurs in heavily doped pn junctions. The heavy doping makes the depletion layer extremely thin. Due to thin depletion layer the electric field acting on depletion layer is very strong & due to this high electric field, there is direct rupture of covalent bonds & current through diode increases. Zener breakdown voltage is less than 7 volts. The temperature coefficient of the Zener mechanism is negative i.e. the breakdown voltage for a particular diode decreases A Zener diode is a type of diode that with increasing temperature. permits current not only in the forward direction like a normal diode, but also in 2.10.2 AVALANCHE BREAKDOWN the reverse direction if the voltage is larger than the breakdown voltage known as Avalanche breakdown occurs in lightly Zener knee voltage or breakdown voltage. doped diodes. It is caused by impact A Zener diode does not allow significant ionization of electron-hole pairs. In a current if it is reverse-biased below its reverse biased diode, electrons that enter reverse breakdown voltage. When the the depletion region undergo a tremendous reverse bias breakdown voltage is acceleration. As these accelerated carriers exceeded, a Zener diode is subject to high collide with the atoms they can knock current due to breakdown. Unless this electrons from their bonds, creating current is limited by circuitry, the diode additional electron/hole pairs and thus will be permanently damaged. additional current. As these secondary In case of large forward bias (current in the carriers are swept into the depletion direction of the arrow); the diode exhibits a region, they too are accelerated and the voltage drop due to its junction built-in process repeats itself. This is akin to an voltage and internal resistance. The avalanche where a small disturbance amount of the voltage drop depends on the causes a whole mountainside of snow to semiconductor material and the doping come crashing down. Avalanche breakdown concentrations. A Zener diode exhibits voltage is greater than 6 volts. almost the same properties, except the The temperature coefficient of the avalanche device is specially designed so as to have a mechanism is positive i.e. the breakdown greatly reduced breakdown voltage, the so- voltage for a particular diode increases called Zener voltage. By contrast with the with increasing temperature.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 2.10.3 APPLICATIONS is the most important and most widely used characteristic of the tunnel diode. 1) The Zanier diode ideal for applications such as the generation of a reference 2.11.1 EQUIVALENT CIRCUIT voltage (e.g. for an amplifier stage). 2) They are used as a voltage stabilizer for low-current applications.

2.11 TUNNEL DIODE

In the tunnel diode, the semiconductor materials used in forming a junction are 2.11.2 APPLICATIONS doped to the extent of one impurity atom per thousand atoms of semiconductor. 1) A tunnel diode biased to operate in the This heavy doping produces an extremely negative resistance region can be used narrow depletion zone similar to that in as either an oscillator or an amplifier in the Zener diode. Also because of the heavy a wide range of frequencies and doping, a tunnel diode exhibits an unusual applications. current-voltage characteristic curve as 2) Tunnel diodes are also used compared with that of an ordinary extensively in high-speed switching junction diode. The characteristic curve circuits because of the speed of the for a tunnel diode is illustrated in figure tunneling action. below 2.12 TYPES OF PN JUNCTIONS

Based on the fabrication process there are several different types of PN junctions. Some of these are discussed below.

2.12.1 STEP GRADED PN JUNCTION

A step graded junction is also called as abrupt junction. In a step graded PN junction The three most important aspects of this both the layers are uniformly doped but characteristic curve are: there is abrupt change in doping at the 1) When VV , the forward current junction i.e. in a step graded junction P & N dp sides have different doping. A highly doped increases linearly to a peak ( ). Ip region is represented with a ‘+’ superscript

2) When VVVpdv, with increase in i.e. step graded junction is either  forward voltage current decreases PNor PN . The charge density & electric

from Ip to Iv i.e. it exhibits negative fields are shown in the figure below resistance in this region.

3) When VVdv , the normal increasing forward current with further increases in the bias voltage. The portions of characteristics curve between and is the region of negative resistance. The negative resistance region

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission As the depletion layer width is inversely proportional to doping concentration, it penetrates more into lightly doped region as compared to highly doped region. The

depletion region width W,WNP& doping

concentrations N,NDA on P & N sides are related by the charge neutrality equation as W N N  A WNPD

Or WNDPA N W N The electric field across the depletion layer directs from N-side to P-side, it is maximum at the junction & it decreases as we move away from the junction. The magnitude of maximum electric field is given by qNW qNW E DN AP max εε

Where ε ε ε 0r 12 ε8.85410F/m0 

ε r is relative permittivity

2.12.2 LINEARLY GRADED JUNCTION

In a linearly graded PN junction, the doping concentration does not abruptly change but the change is almost linearly across the junction. The width of depletion layer is same on both the sides. The depletion layer 1 1 width varies as V2 instead of V3 as in the case of step graded junction. The charge density variation in linearly graded diode is as shown in figure.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission GATE QUESTIONS

Q.1 In the figure, a silicon diode is time t .For <≤ is given by 0 t tVs' R carrying a constant current of 1 mA. (all in Volts) When the temperature of the diode s is 20oC, VD is found to be 700 mV. If the temperature rises to 40oC, VD becomes approximately equal to

a) V5R = − b) V5R = +

c)0 V < 5 d) −<5VR < 0

R [GATE-2006] a)740 mV b)660 mV ≤ c)680 mV d)700 mV Q.5 Find the correct match between [GATE-2002] Group 1 and Group 2 Group 1 Q.2 Choose proper substitutes for X and E. Varactor diode Y to make the following statement F. PIN diode correct. Tunnel diode and Avalanche G. Zener diode photodiode are operated in X bias H. Scotty diode and Y bias respectively. Group 2 a) X: reverse, Y:reverse 1. Voltage reference b) X:reverse, Y:forward 2. High-frequency c) X: forward , Y : reverse 3. Tuned circuits d) X : forward , Y : forward 4. Current controlled attenuator [GATE-2003] a) E-4, F-2, G-1, H-3 b) E-2, F-4, G-1, H-3 c) E-3, F-4, G-1, H-2 Q.3 The values of voltage ()VD across a d) E-1, F-3, G-2, H-4 tunnel–diode corresponding to peak and valley currents are V and V [GATE-2006] respectively. The range of tunnel- p V Q.6 In a p n junction diode under diode voltage for which the ()VD reverse + bias, the magnitude of

slop of its I- ()VD characteristics is electric field is maximum at negative would be a) the edge of the depletion region on the p-side a) V0< b) 0V≤< V D Dp b) the edge of the depletion region c) VVVpDV≤< d) VVDV≥ on the n-side [GATE-2006] c) the p n junction d) the +centre of the depletion Q.4 In the circuit shown below, the region on the n-side switch was connected to position 1 [GATE-2007] at t<0 and at t=0, it is changed to position 2. Assume that y the diode Q.7 Group I lists four type of p-n has zero voltage drop and a storage junction diodes . Match each device in Group I with one of the Options in

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Group II to indicate the bias S2: For quantum tunneling to occur, condition of that device in its a very narrow energy barrier is normal mode of operation required. Group I Group II Which of the following is correct? P. Zener diode 1)Forward Bias a) Only S2 is true Q. Solar cell 2) Reverse Bias b) S1 and S2 are both true but S2 is R. LASER Diode not a reason for S1 S. Avalanche Photodiode c) S1 and S2 are both true and S2 is a)P-1,Q-2,R-1,S-2 a reason for S1 b) P-2,Q-1,R-1,S-2 d) Both S1 and S2 are false c) P-2,Q-2,R-2,S-1 [GATE-2008] d) P-2,Q-1,R-2,S-2 [GATE-2007] Q.12 Compared to a p-n junction with 14 3 NAD= N = 10 / cm , which one of Q.8 Group I lists four different the following statements is TRUE semiconductor device. Match each for a p-n junction with device in Group I with characteristic N= N = 1020 / cm 3 ? property in Group II AD Group I Group II a) Reverse breakdown voltage is P. BJT 1.Population lower and depletion capacitance inversion is lower Q. MOS Capacitor 2. Pinch off Voltage b) Reverse breakdown voltage is R. Laser Capacitor 3. Early effect higher and depletion capacitance S. JFET 4.Flat –band voltage is lower a)P-3, Q-1, R-4, S-2 c) Reverse breakdown voltage is b) P-1, Q-4, R-3, S-2 lower and depletion capacitance c) P-3, Q-4, R-1, S-2 is higher d) P-3, Q-2, R-1, S-4 d) Reverse breakdown voltage is [GATE-2007] higher and depletion capacitance is higher Q.9 Ap n junction has built–in potential [GATE-2010] of +0.8 V. The depletion layer width at a reverse bias of 1.2V is 2 m. For Q13 A silicon PN junction is forward a reverse bias of 7.2 V, the depletion biased with a constant current at layer width will be µ room temperature. When the a) 4 m b) 4.9 m temperature is increased by , c) 8 m d) 12 m the forward bias voltage across the µ [GATEµ -2007] PN junction 10℃ µ µ a) Increase by 60mV Q.10 Which of the following is Not b) decrease by 60mV associated with a p-n junction? c) Increase by 25mV a) Junction Capacitance d) decrease by 25 mV b)Charge Storage Capacitance [GATE-2011] c) Depletion Capacitance d) Channel Length Modulation Q.14 In a forward biased p-n junction [GATE-2008] diode, the sequence of events that best describes the mechanism of Q.11 Consider the following assertions: current flow is S1: for Zanier effect to occur, a very abrupt junction is required

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission a) Injection, and subsequent a) 0.7 V and 1 x 10-4 cm diffusion and recombination of b) 0.86 V and 1 x 10-4 cm minority carriers c) 0.7 V and 3.3 x 10-5cm b) Injection, and subsequent drift d) 0.86 V and 3.3 x 10-5cm and generation of minority [GATE-2014-3] carriers c) Extraction, and subsequent Q.18 A region of negative differential diffusion and generation of resistance is observed in the current minority carriers voltage characteristics of a silicon d) Extraction, and subsequent drift PN junction if and recombination of minority a) Both the P-region and the N- carriers region are heavily doped [GATE-2013] b) The N-region is heavily doped compared to the P-region Q.15 When the optical power incident on c) The P-region is heavily doped a photodiode is 10 W and the compared to the N-region responsivity is 0.8A / W, the d) An intrinsic silicon region is photocurrent generatedµ (in A) is inserted between the P-region ______. and the N-region [GATE-2014µ -1] [GATE-2015]

Q.16 Consider an abrupt PN junction (at T Q.19 The built-in potential of an abrupt p- = 300 K) shown in the figure. The n junction is 0.75V. If its junction depletion region width Xn. on capacitance (C ) at a reverse bias the N-side of the junction is 0.2 m (V ) of 1.25V is 5pF , the value of C J and the permittivity of silicon ( ) is (in pF) when V = 7.25V is ______. R J 1.044x10-12 F/cm. At the junction,µ [GATE-2015] the approximate value of the εpeaksi R electric field (in kV/cm) is ______. Q.20 For a silicon diode with long P and N regions, the accepter and donor impurity concentrations are 1 × 10 cm and 1 × 10 cm , respectively.17 −3 The lifetimes15 −3of electrons in P region and holes in N [GATE-14-2] region are both 100 s . The electron and hole diffusion coefficients are Q.17 The donor and accepter impurities µ in an abrupt junction silicon diode 49 cm / s and 36 cm / s, are 1 x 1016 cm-3 and 5 x 1018 cm-3, respectively.2 Assume kT / q=2 26 mV respectively. Assume that the , the intrinsic carrier concentration intrinsic carrier concentration in is 1 × 10 cm and q =1.6 × 10 C . When a10 forward−3 voltage of 208 silicon ni = 1.5 x 1010 cm-3 at 300 K, −19 mV is applied across the diode, the kT = 26 mV and the permittivity of hole current density (in nA /cm ) q injected from P region to N regions2 -12 silicon Rsi = 1.04 x10 F/ cm. The is ______. built-in potential and the depletion [GATE-2015-1] width εof the diode under thermal equilibrium conditions, respectively, Q.21 The electric field profile in the are depletion region of a p-n junction in

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission equilibrium is shown in the figure. VBR, the relationship between VBR Which one of the following and ND is given by statements is NOT TRUE? a)VBR × N = constant

b)ND × V = constant � D c)ND × VBR = constant BR d)ND / V�BR = constant [GATE-2016-2]

Q.24 Assume that the diode in the figure has V = 0.7V, but is otherwise ideal. a) The left side of the junction is n- The magnitude of the current i (in on type and the right side is p-type mA) is equal to ______. 2 b) Both the n-type and p-type depletion regions are uniformly doped c) The potential difference across the depletion region is 700 mV d) If the p-type region has a doping concentration of 1015 cm-3 , then [GATE-2016-2] the doping concentration in the n-type region will be 1016 cm-3 Q.25 The I-V characteristics of three [GATE-2015-3] types of diodes at the room temperature, made of Q.22 Consider a silicon p-n junction with semiconductors X, Y and Z, are a uniform acceptor doping shown in the figure. Assume that the concentration of 10 cm on the p- diodes are uniformly doped and side and a uniform17 donor−3 doping identical in all respects except their concentration of 10 cm on the materials. If EgX, EgY and EgZ are n-side. No external16 voltage−3 is the band gaps of X, Y and Z, applied to the diode. Given: kT/q = respectively, then 26 mV, n =1.5× 10 cm , =12 , ε =8.85 × 10 10F/m,−3 and q= 0 i si 0 1.6 × 10 C The− 14charge perε unitε junction− 19area (nC cm ) in the depletion region on the p−2-side is ____. [GATE-2016-1]

Q.23 Consider avalanche breakdown in a a) EgX > EgY > EgZ silicon p+ n junction. The n-region is b) EgX = EgY = EgZ uniformly doped with a donor c) EgX < EgY < EgZ density ND. Assume that breakdown d) no relationship among these occurs when the magnitude of the band gaps exists electric field at any point in the [GATE-2016-3] device becomes equal to the critical field Ecrit . Assume Ecrit to be Q.26 The figure shows the I-V independent of ND. .If the built-in characteristics of a solar cell voltage of the p+ n junction is much illuminated uniformly with solar smaller than the breakdown voltage, light of power 100 mW/cm2. The

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission solar cell has an area of 3 cm2 and a [GATE-2016-3] fill factor of 0.7. The maximum efficiency (in %) of the device is ___. Q.29 An n+ -n Silicon device is fabricated with uniform and non-degenerate donor doping concentrations of ND1 = 1 x 1018cm-3 and ND2 = 1 x 1015 cm-3 corresponding to the and n+ regions respectively. At the operational temperature T, assume complete impurity ionization, kT/q [GATE-2016-3] = 25 mV, and intrinsic carrier concentration to be n1 = 1 x 1010 Consider a region of silicon devoid Q.27 -3 of electrons and holes, with an cm . What is the magnitude of the + 17 built- in potential of this device? ionized donor density of Nd =10 CM-3. The electric field at x = 0 a)0.748V b) 0.460V is 0 V/cm and the electric field at x = L is 50 kV/cm in the positive x c) 0.288V d) 0.173V direction. Assume that the electric field is zero in the y and z directions [GATE-2017-1] at all points. Q.30 As shown, two Silicon (Si) abrupt p- n junction diodes are fabricated with uniform donor doping concentration of ND1 = 1014cm-3 and -19 Given q =1.6 × 10 coulomb, = ND2 = 1016cm-3 in the n-regions of -14 8.85 × 10 F/cm, = 11.7 for the diodes, and uniform acceptor silicon, the value of L in nm is _____.ϵ0 r doping concentration of NA1 = [GATEϵ -2016-2] 1014cm-3 and NA2 = 1016cm-3 in the p-regions of the diodes, respectively. Q.28 The I-V characteristics of the zener Assuming that the reverse bias diodes D1 and D2 are shown in voltage is >> built-in potentials of Figure I. These diodes are used in the diodes, the ratio C2/C1 of their the circuit given in Figure II. If the reverse bias capacitances for the supply voltage is varied from 0 to same applied reverse bias, is 100 V, then breakdown occurs in ______.

[GATE-2017-1] a) D1 only b) D2 only c) both D1and D2 d) none of D1 & D2

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.31 For a particular intensity of incident c) light on a silicon pn junction solar cell, the photocurrent density (JL) is 2.5 mA/cm2 and the open-circuit voltage (Voc) is 0.451 V. consider thermal voltage (VT) to be 25mV. If the intensity of the incident light is increased by 20 times, assuming that the temperature remains unchanged. Voc (in volts) will be ______. d)

[GATE-2017-1]

Q.32 An abrupt pn junction (located at x = 0) is uniformly doped on both p and n sides. The width of the depletion region is W and the electric field variation in the x-direction is E(x). Which of the following figures represents the electric field profile [GATE-2017-2] near the pn junction? Q.33 A p-n step junction diode with a a) contact potential of 0.65 V has a depletion width 1µm of at equilibrium. The forward voltage (in volts, correct to two decimal places) at which this width reduces to 0.6 µm is____.

[GATE-2017-2]

Q.34 In a p-n junction diode at b) equilibrium, which one of the following statements is NOT TRUE?

a) The hole and electron diffusion current components are in the same direction.

b) The hole and electron drift current components are in the same direction.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission c) ON an average, holes and d) ON an average, electrons drift and electrons drift in opposite diffuse in the same direction. direction.

ANSWER KEY:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 (b) (c) (c) (a) (c) (c) (b) (c) (a) (d) (a) (c) (d) (a) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 8 30.6 (d) (a) 2.5 28.6 (c) * (c) 0.25 (c) 21 32.4 (a) 29 30 31 32 33 34 (d) 10 0.5262 (a) 0.416 (d)

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission EXPLANATIONS

Q.1 (b) Q.9 (a) dV Depletion width ∝+ For either Si or Ge ; −2.5mV /℃ wdep() VV o R dT 7.2+ 0.8 In order to maintain a constant of I w2= × μ dep 1.2+ 0.8 T21−= T 40 − 20 =20 -2.5× 20mV=50mV =22 × µ Therefore, ℃ = 4μm

VD = 700 − 5 =650 660mV Q.10 (d) Channel length modulation is Q.2 (c) ≃ phenomena in MOSFET. A tunnel diode is always operated under forward bias in negative Q.11 (a) resistance region & avalanche photo diode is operated in reverse bias. Q.12 (c) Zener breakdown voltage is lower Q.3 (c) for higher doping Depletion Varactor diodes are used in tuned capacitance is inversely proportional circuits and zener diodes is used as to width of depletion and higher the voltage reference when it is in doping lower width. So when doping reverse bias. Scottky diode is used is higher depletion capacitance is as high frequency switch. higher

Q.4 (a) Q.13 (d) During storage time, diode will be For Si forward bias voltage by ON so 2.5mv/ V =-5V during 0 < . 10 increase, change will be R −2.5 × 10℃= 25mV 𝑡𝑡𝑠𝑠 ≤𝑡𝑡 decrease℃ by 25 mV Q.5 (c) − − Between and voltage, tunnel Q.14 (a)∴ diode acts as negative resistance. 𝑉𝑉𝑝𝑝 𝑉𝑉𝑣𝑣 Q.6 (c) Electric field is max at the junction.

Q.7 (b) Zener diode and avalanche photo diode –Reverse bias, Solar cell and laser diode –forward bias. In a forward biased p-n junction diode, the outward voltage force is Q.8 (c) applied , at first the minority By the basic properties of various carriers are injected through the devices. depletion region that diffused

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission through the depletion region. As the Q.20 (28.59) minority carriers diffuse through Hole current density = the depletion region, they will qVa qDpn P  recombine each other 0 e1kT − Lp  n 2 Q.15 (8 ) P = i IP n0 Responsivity (R) = Nd P0 Given 53− I Nd = 1 × 10 cm = P 0.8 −6 10× 10 τpn= τ = 100μ sec ⇒= I88 μA Va= 208mV,D pn = 36,D = 49 2 D qVa qni p kT Q.16 (30.66) J1p =e − N τ Given xn = 0.2 m, Rsi dp -12 −19 20 208 = 1.044×10 F / Rn,  1.6×× 10 10 36 26 ND =1016 /cm3𝜇𝜇 𝜖𝜖 = e −1 × 15 µ 𝜇𝜇 1 10 100  qNDn X Peak Electric field, E = 6× 102 ×× 1.6 10  = ××3 15 2.979 10 1.6x10−19 10 16 ×× 0.00002 10 = = 28.59 nA/ cm 1.044× 10−12 = 30.66KV/cm 2 Q.21 (c) Built in potential Q.17 (d) 1 NN ψ=× 1066V ×× (1.1 10− m) Vbi = VT In AD 0 () 2 2 m n i =0.55 volts  5× 1018 ×× 1 10 16 But in Question (option C) is given = 26 mv In  as 700 mV 10 2 ()1.5× 10 = 0.859V Q.22 (47 to 49) 2εV NN+ W= s bi AD Q.23 (c) q NNAD If the depletion region is not making =3.34 × 10−5 cm any change it means ND × VBR = constant Q.18 (a) Q.24 (0.25) Diode is the OFF state Q.19 (2.5) 2 1 == ∝ I2 0.25mA CJ 8k VVbi+ R C VV+ 2J= bi R1 Q.25 (C) C1j VV bi+ R 2 Q.26 (21) 2 C1j = = FF.V∝ ISC C2J C 1j 2.5pF Efficiency = 82 P So, answer is 2.5 in 0.7×× 0.5 180 = = 21% (100× 3)

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission kT JL Q.27 (32.37) VOC = ln + 1 3 qJS dEqND 50× 10 = ⇒ 20x2.5x10−3 dx ∈ L −3 + 25x10 ln−11 1 1.6×× 10−19 10 17 3.6x10 = 8.854×× 10−14 11.7 = 0.5262Volt 50×× 103 8.854 × 10− 14 × 11.7 L = −2 Q.32 (a) 1.6× 10 If left side is p-region and right side = 32.372× 10 m is n-region then electric field −9 Q.28 (a) triangle will be down warded and if the left side is n-region and right Q.29 (d) side is p-region, then electric field triangle will be upward. N1 Vbi= V T ln  N 2 Q.33 0.416 1018 = = 0.25ln15 0.173V We know that in pn junction 10 W∝− VV Q.30 10 bi f

εA Given, C = W W1f=µ= 1 m,V 0 11 C∝∝ andW W=µ= 0.6 m,V ? W doping 2f W1 5 0.65 C∝ doping = = W2 3 0.65− x C ()doping 1016 21= = = = 25 25 14 100 10 x0.65⇒= x 0.65 C1 () doping2 10 99 x= 0.416 Q.31 0.51-0.54 J = L Js V OC Q.34 (d) e1VT −   Since the concentration of holes on 2.5x10−3 = the p side is much greater than that 0.451  in the n side, a very large hole e10.025 − diffusion current tends to flow  across the junction from the p to the = 3.6x10−11 A / cm 2 n material. Hence an electric field Now if the intensity of the light is must build up across the junction in increased by 20 times it means their such a direction that a hole drift photo current will also increase by current will tend to flow across the 20 times junction from n to p side in order to

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission counterbalance the diffusion current.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 3 TRANSISTORS

3.1 INTRODUCTION The three portions of a transistor are known as emitter, base and collector. The Transistors are active components and are arrow on the emitter lead specifies the found everywhere in electronic circuits. direction of current flow when the emitter They are used as amplifiers and switching –base junction is biased in the forward devices. As amplifiers, they are used in high direction. and low frequency stages, oscillators, modulators, detectors and in any circuit Emitter: Emits minority carriers into the needing to perform a function. In digital base region of a BJT. For example, in an circuits they are used as switches. There NPN BJT the n-type emitter emits electrons are two types of junction transistors into the p-type base (electrons are called as 1) Bipolar junction transistors: Bipolar minority charge carriers in P-type base). transistors are so named because their The emitter usually has the highest doping operation involves both electrons levels of the three regions in order to inject and holes. These two kinds of charge large number of minority charge carriers carriers are characteristic of the two into base. kinds of doped semiconductor material. Base: Thin region which is used to control 2) Unipolar junction transistors: Unipolar the flow of minority carriers from the are called so because transistors such emitter to the collector. Base is lightly as the field-effect transistors have only doped in order to reduce the one kind of charge carrier. recombinations of injected minority carriers with the majority carriers of base 3.2 BIPOLAR JUNCTION TRANSISTOR region. Also base is smallest region in transistor so that a high concentration A bipolar junction transistor consists of a gradient for injected charge carriers can be silicon (or germanium) crystal in which a created between base and collector. layer of n-type silicon is sandwiched between two layers of p-type silicon. Collector: Collects the minority carriers Alternatively a transistor may consist of a that make it through the base from the layer of p-type between two layers of n- emitter. The collector usually has moderate type material. In the former case the doping. It is the largest region of transistor transistor is referred to as a p-n-p in order to dissipate the heat generated at transistor, and in the latter case, as an n-p- the reverse biased collector junction. n transistor.

In BJT there are two junctions 1) JE is called base emitter junction or simply emitter junction.

2) JC is called base collector junction or simply collector junction.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission As base is lightly doped region, the combine with holes in p-region (base). As depletion region penetrates more into base the base is very thin and lightly doped, very region. few of the injected electrons recombine with holes to constitute base current(IB).

The remaining large numbers .of electrons cross the depletion region and move In both cases the emitter, base and through the collector region to the positive collector currents are IE, IB and IC terminal of the external dc source. This respectively. These are assumed positive constitutes collector currentIC. Thus the when the current flows in the given electron flow constitutes the dominant direction. current in an n-p-n transistor. Since the Also, I IE I B C most of the electrons from emitter flow in the collector circuit and very few combine The symbols VBE, VCB and VCE are the emitter–base, collector-base, and collector– with hole in the base, the collector current emitter voltages respectively. (More is larger than the base current. Hence specifically, VBE represents the voltage drop from base to emitter). Also, VCE = VBE + VCB 3.4 TRANSISTOR CURRENT COMPONENTS

3.3 TRANSISTOR ACTION

Let us consider the n-p-n transistor for our discussion. The base to emitter junction is forward biased by the dc sourceVEE. Thus, the depletion region at this junction is reduced. The collector to base junction is reverse biased, increasing depletion region at collector to base junction as shown Fig.

Fig. shows an n-p-n transistor with forward-biased emitter junction and the reverse –biased collector junction. The emitter current IE consists of hole current 1) I : Due to holes crossing junction from The forward biased BE junction cause the pE emitter to base. electrons in the n-type emitter to flow 2) I : Due to electrons crossing junction towards the base. This constitutes the nE from base to the emitter. emitter currentIE. As these electrons flow through the p-type base, they tend to

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission In transistor the doping of the emitter is II γ nEnE made much larger than the doping of the I I IEE E base. This feature ensures (in a p-n-p Pn Where I is the injected hole diffusion transistor) that the emitter current consists pE almost entirely of holes. Such a situation is current at emitter junction and InE is the desired since the current which results injected electron diffusion current at from electrons crossing the emitter emitter junction.

junction from base to emitter does not ∗ contribute which can reach the collector. 3.4.2 TRANSPORTATION FACTOR 훃

Not all the holes crossing the emitter ∗ junction J reach the collector junction J The transport factor β is defined as E C injected carrier current reaching J because some of them combine with β*  C electrons in the n-type base. If IpC is the injected carriercurentat JE hole current at JC there must be a bulk In the case of p-n-p transistor we have recombination current I −I leaving the I pE pC β*  pC base, as indicated in Fig (actually, electrons IpE enter the base region through the base lead In case of n-p-n transistor to supply those charges which have been I lost by recombination with the holes β*  nC I injected into the base acrossJE). nE If the emitter is open–circuited so thatIE = 0 , then IpC is also zero. Under these 3.4.3 LARGE SIGNAL CURRENT GAIN 훂 circumstances, the base and collector would act as a reverse–biased diode, and The ratio of the negative of the collector – current increment to the emitter-current the collector current IC would equal the change from zero (cutoff) to I as the large- reverse saturation currentICO. E signal current gain of a common-base i.e. if IE = 0, then IC = ICO. transistor, or & if IE ≠ 0, then IC = ICO − IPC II For a p-n-p transistor, ICO consists of holes α  C Co moving across JC from left to right (base to IE collector) and electrons crossing JC in the Since IC and IE have opposite signs, then α opposite direction. Since the assumed as defined, is always positive. Typical reference direction for ICo in Fig is from numerical values of α lie in the range of right to left then for a p-n-p transistor ICO is 0.90 to 0.995. negative. For an n-p-n transistor, I is CO IIIpCpCpE positive. α  IIIEpEE 3.4.1 EMITTER EFFICIENCY 후 ∴ αβγ *

The emitter, or injection, efficiency γis The transistor alpha is the product of the defined as transport factor and the emitter efficiency. current of injected carriersat J γ  E It should be pointed out that α is not a total emitter current constant, but varies with emitter current IE In the case of p-n-p transistor we collector voltage VCB and temperature. If the transistor is in active region, the IIPPEE γ  collector current is given by IIIEE Pn E I αI I In case of n-p-n transistor C E Co

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 3.4.4 COLLECTOR REVERSE SATURATION CURRENT 퐈퐂퐁퐎 3.6 OPERATING REGIONS OF BJT

The collector current in a physical 1) FORWARD ACTIVE transistor when the emitter current is zero The base–emitter junction is forward is designated by the symbol ICBO . It biased and the base–collector junction is increases approximately by 7% with one reverse biased. Most bipolar transistors are degree rise in temperature & it doubles for designed to afford the greatest common- o every 10 rise in temperature. emitter current gain, βF, in forward-active mode. If this is the case, the collector– Note: The actual collector current with emitter current is approximately collector junction reverse biased & base proportional to the base current, but many open-circuited is denoted as ICEO. times larger, for small base current Also, I1CEO   βICBO variations. ICBβI  1  β  ICBO

3.5 EARLY EFFECT But, I1CBO ∴ I  βI An increase in magnitude of collector CB Note: voltage increases the depletion width at the For an N-P-N silicon transistor operating in output junction diode & such action causes active region V ≥ 0.7 V (for gemanium the effective base width W to decrease, this BE V ≥ 0.2 V) phenomenon known as the Early effect. BE This decrease in W has two consequences 2) SATURATION With both junctions forward-biased, a BJT 1) There is less chance for recombination is in saturation mode and facilitates high within the base region. Hence the current conduction from the emitter to the transport factor β∗ increases with an collector (or the other direction in the case increase in the magnitude of the of NPN, with negatively charged carriers collector junction voltage. flowing from emitter to collector). This 2) Alsoα increases with an increase in the mode corresponds to a logical "on", or a magnitude of the collector junction closed switch. voltage. Note: 3) The charge gradient is increases within the base, and consequently the current  In saturation region, collector current IC of minority carriers injected across the is not proportional to base current IB. Hence IC = βIB this equation is not valid emitter junction increases i.e. IC increases. in saturation.  For an N-P-N silicon transistor When the base–collector voltage reaches a operating in saturation VBE ≥ certain (device specific) value, the base– 0.7 V & VCE ≤ 0.2 V (for germanium collector depletion region boundary meets VBE ≥ 0.2 V&VCE ≤ 0.1 V). the base–emitter depletion region boundary. When in this state the transistor 3) CUT-OFF effectively has no base. The device thus In cutoff, biasing conditions opposite of loses all gain when in this state &this saturation (both junctions reverse biased) situation is called punch through or are present. There is very little current, reaches through. When this situation which corresponds to a logical "off", or an occurs, a large collector current flows open switch. (breakdown) which may destroy transistor.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Note:  In cut-off region IE = 0& a small reverse current ICBO flows through transistor as shown in figure Here the input signal which is to be amplified is applied between emitter & base while output signal is taken between collector & base. The o/p current in this case is IC& the i/p current is IE. Current gain of common base transistor is I  C  For an N-P-N germanium transistor to IE operate in cutoff ∝ ≈ 1, but it is always less than 1 VBE  V BB  R B I CBO   0.1V  For an N-P-N silicon transistor to operate in cutoff 3.7.2 COMMON EMITTER CONFIGURATION

VBE  V BB  R B I CBO  0.0V

4) REVERSE ACTIVE By reversing the biasing conditions of the forward-active region, a bipolar transistor goes into reverse-active mode. In this mode, the emitter and collector regions switch roles. Because most BJTs are designed to maximize current gain in Here the input signal which is to be forward-active mode, the βF in inverted mode is several times smaller (2–3 times amplified is applied between base & for the ordinary germanium transistor). emitter while output is taken between collector & emitter. The o/p current in this Typical values of junction voltages for N- case is IC& the i/p current is IB. P-N Transistor Current gain of common emitter transistor is V V V V CE,sat BE,sat BE,active BE,cutoff I Si 0.2 0.8 0.7 0.0 β  C Ge 0.1 0.3 0.2 -0.1 IB

3.7 OPERATING MODES OF BJT 3.7.3 COMMON COLLECTOR CONFIGURATION

Depending on which of the three terminals is used as common terminal, there can be three possible configurations for the two- port network formed by a transistor: common emitter (CE), common base (CB), and common collector (CC).

3.7.1 COMMON BASE CONFIGURATION Here the input signal which is to be amplified is applied between base & collector while output signal is taken between emitter & collector. The o/p

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission current in this case is IE& the i/p current is In a grounded-emitter transistor circuit, IB. such as the light-switch circuit shown, as Current gain of common collector the base voltage rises, the emitter and transistor is collector currents rise exponentially. The I collector voltage drops because of reduced γ  E resistance from collector to emitter. If the IB 3.7.4 RELATION BETWEEN ∝, 훃&후 voltage difference between the collector and emitter were zero (or near zero), the β collector current would be limited only by 1)  the load resistance (light bulb) and the 1β supply voltage. This is  2) β  called saturation because current is flowing 1 from collector to emitter freely. When 3) γ 1 β saturated, the switch is said to be ON& 1 when it is in cut-off, the switch is said to be 4) γ  1 OFF.

3.8 APPLICATIONS OF BJT

1) As a diode BJT can be used as a diode by shorting the base & collector terminals. Another way to use BJT as diode is by keeping base & collector terminals at same potential. Due 3) As an amplifier the short circuit across collector junction The common-emitter amplifier is designed there will be only one PN junction (J ). so that a small change in voltage (Vin) E changes the current through the base of the transistor & hence the current through collector. The transistor's current amplification combined with the properties of the circuit mean that small swings in Vin produce large changes in Vout. Various configurations of single transistor amplifier are possible, with some providing current gain, some voltage gain, and some When base & collector terminal are both. shorted, the emitter current through BJT is given by

V/VBET IIeECO Where, ICO is reverse saturation current VBEis base to emitter voltage VTis thermal voltage

2) As a switch Transistors are commonly used as 3.9 FIELD EFFECT TRANSISTOR electronic switches, both for high-power applications such as switched-mode power The field-effect transistors a semiconductor supplies and for low-power applications device which depends for its operation on such as logic gates. the control of current by an electric field.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission There are two types of field-effect transistors, the junction field–effect transistor (abbreviated JFET, or simply FET) and the insulated–gate field–effect transistor (IGFET), more commonly called the metal-oxide-semiconductor (MOS) transistor(MOST or MOSFET). 3.9.1 ADVANTAGES OF FET OVER BJT

1) Its operation depends upon the flow of majority carriers only. It is therefore a unipolar (one type of carrier) device. The vacuum tube is another example of a unipolar device. The conventional transistor is a bipolar device. 2) It is relatively immune to radiation. 3.10 JUNCTION FIELD EFFECT TRANSISTORS 3) It exhibits a high input resistance, The structure is quite simple. In an N- typically many mega-ohms. channel JFET an N-type silicon bar, referred 4) It is less noisy than a tube or a bipolar to as the channel, has two smaller pieces of transistor. P-type silicon material diffused on the 5) It exhibits no offset voltage at zero drain opposite sides of its middle part, forming P- current, and hence makes an excellent N junctions, as illustrated in figure. The two signal chopper P-N junctions forming diodes or gates are 6) It has excellent thermal stability. connected internally and a common terminal, called the gate terminal, is Note: brought out.  BJT is a current controlled device while FET is a voltage controlled device.  Unlike BJT, FET is a symmetrical device hence source & drain terminals can be interchanged.

3.9.2 DISADVANTAGE

The main disadvantage of the FET is its relatively small gain–bandwidth product in comparison with that which can be obtained with a conventional transistor.

3.9.3 CLASSIFICATION OF FET’s

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission The silicon bar behaves like a resistor impurity regions are called the gate G. between its two terminals D and S. The gate Between the gate and source a voltage VGS terminal is analogous to the base of an is applied in the direction to reverse-bias ordinary transistor (BJT). It is used to the p-n junction. Conventional current control the flow of current from source to entering the bar at G is designatedIG. drain. Thus, source and drain terminals are analogous to emitter and collector Note terminals respectively of a BJT. As the junctions between gate-source & In the figure above, the gate is P-region, gate-drain are always kept reverse biased, while the source and the drain are N- the gate current entering the gate terminal regions. Because of this, a JFET is similar to in negligibly small & considered as 0 two diodes. The gate and the source form i.e. IG ≈ 0 A one of the diodes, and the drain form the other diode. These two diodes are usually Channel referred as the gate-source diode and the The region in fig of n-type material gate-drain diode. Since JFET is a silicon between the two gate regions is the device, it takes only 0.7 volts for forward channel through which the majority bias to get significant current in either carriers move from source to drain. diode. P-channel JFET is similar in construction to N-channel JFET except that P-type semiconductor material is sandwiched between two N-type semiconductors. With the gate terminal not connected, and a potential applied (+ ve at the drain and – ve at the source), a current called the drain 3.10.1 OPERATION current, ID flows through the channel located between the two P-regions. This Consider an N-channel JFET shown in current consists of only majority carriers- figure. electrons in this case. When neither any bias is applied to the gate (i.e. when VGS = 0) nor any voltage to the Source drain with respect to source (i.e. when The source S is the terminal through which VDS = 0), the depletion regions around the the majority carriers enter the bar. P-N junctions, are of equal thickness and Conventional current entering the bar at S symmetrical. is designated byIS.

Drain The drain D is terminal through which the majority carriers leave the bar. Conventional current entering the bar at D is designated by ID.

Gate On both sides of the n-type bar of fig. heavily doped (p+) regions of acceptor impurities have been formed by alloying, by diffusion or by any other procedure available for creating p-n junctions. These

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 3.10.2 TRANSFER CHARACTERISTICS: In the equation values of IDSS and Vp are (Varying VGS& keeping VDS constant) constants, value of VGS controls ID I0whenVVD GSGS(cutoff )  1) When 퐕퐆퐒 = ퟎ 퐕 , the application IIwhenV0DDSSGS ofVDS causes a current to flow from source to drain. The drain current in this case is maximum as the channel Note: As the drain current depends on resistance is minimum & it is denoted square of VGS, a jfet can be called as a square law device. as IDSS. 3.10.3 DRAIN CHARACTERISTICS 2) When negative 퐕퐆퐒 is applied, the depletion region of the gate-channel (Varying VDS& keeping 푉퐺푆 constant) junction widens & the channel becomes correspondingly narrower; thus the 1) When 푽푫푺 = ퟎ 푽 the electric field in the channel resistance increases & the channel is zero & the drain current 퐼퐷 is zero. current ID(for a given VDS) decreases. 2) When a positive voltage is applied to 3) If we keep increasing VGS in the negative direction, a value is reached at the drain terminal with respect to the which the depletion region occupies the source terminal i.e. 푽푫푺 > 0 푉 is applied, a field is induced in the channel entire channel. At this value of VGS the channel is completely depleted of & electrons flow from source to drain charge carriers (electrons) & drain results in drain current. current reduces to zero. This value of 3) With increase in 푉퐷푆 the reverse biasing of gate to drain increases and the VGS is called cut-off voltageVGS(cut−off) or pinch-off voltage V . depletion layer widens as shown in P figure. Also the field in channel Note: This variation in width of channel increases with 푉퐷푆 & hence drain current퐼퐷 increases. with applied VGS is called channel width modulation.

4) For a particular value of 푉퐷푆called pinch The relationship between the drain current off voltage, both the depletion layers ID and gate to source voltage VGS is non- come extremely closer to each other but linear. This relationship is defined by due to a very strong electric field the Shockley’s equations flow of charge carriers continue in the 2 channel & drain current saturates.  VGS I I 1 5) For 푉퐷푆 > 푉푃, the drain is almost D DSS  Vp constant

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission The trans conductance, gm, is the change in the drain current with change in gate to source voltage with the drain to source voltage constant.

6) If 푉퐷푆 is increased to a very large value above pinch off, jfet breaks down due to avalanche effect.

3.10.4 DRAIN RESISTANCE From fig .we can say that it is the slope of the transfer characteristic. Since the slope From the drain characteristic, the varies g also varies. g has a greater value important parameter of JFET, drain m m near the top of the curve than it does near resistance 풓 ,can be calculated fig. shows 풅 the bottom. The transconductance g is the drain characteristics of n-channel JFET m defined as I g| D m VDS constant VGS The transconductance gm is also called mutual conductance. The practical unit for gm is mS or mA/V. For given gm we can calculate an approximate value for gm at any point on the transfer characteristic curve using the following equation . The drain resistance 풓 is the ac resistance V 풅 gg1GS between drain and source terminals when mmo VGS off, the JFET is operating in the saturation  region. It is reciprocal of the slope of the Where gmo is the value of gm for VGS = 0 drain characteristic in the saturation and is given by, 2I region. It is given by g  DSS V mo V r| DS P d VconstantGS  ID Since the characteristics in the saturation 3.10.6 AMPLIFICATION FACTOR 훍 region is almost flat, 퐫퐝 is not easily V determined from the characteristics. Value Amplification factor μ| DS ID constant of 퐫퐝 ranges from 50kΩ to several VGS hundredkΩ. Since 퐫퐝is usually the output VDS resistance of the JFET. μ  VGS V I DS D 3.10.5 TRANSCONDUCTANCE IVD GS

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission ∴ μ r g 2 dm V II1GS DDSS V Example GSoff, Data sheet of a JFET indicates that 2 3 4V I10mA and V  4V 20101 DSS GS cutoff, 5V Determine the drain current for  2 0 1 0 0 . 03 4 V0V,1Vand4VGS  .  0 . 8 mA Solution

For V0V,II10mAGSDDSS 3.11 MOS CAPACITOR

For V1GS  , 2 The MOS capacitor structure is shown in  VGS Figure 1. The “metal” plate is a heavily II1 + DDSS V doped p poly-silicon layer which behaves GSoff, as a metal. The insulating layer is silicon 2 1 dioxide and the other plate of the capacitor 10mA 1 4 is the semiconductor layer which in our case is p-type silicon. The 101010.253   2  1 0 1 0 0 . 53 6 2 5 5 . 6 2 5 mA

For V4VGS  2 4V I10mA1D  4V 332 2 10101110100  The capacitance depends on the voltage  0mA that is applied to the gate (with respect to the body). Depending on the gate voltage the operation of MOS capacitor can be Example divided into three modes For JFET, if I20mA,VDSS  GS CUToff , 3.11.1 ACCUMULATION MODE  5V,andg4mAmo / V. Determine the trans conductance for V = GS When the applied gate voltage VG < VFB, (a −4V and find ID at the point. negative voltage at gate) the majority Solution charge carriers (holes) in the P-type we have , substrate accumulates near the oxide V semiconductor interface. g g 1 GS m mo V GS off  , 4V 4101 3 5V 4  103  0.2  0.8mS Also,

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 2) Depletion capacitance εsi 2 Cd  F/ m xd

Where, εsi ε 0 ε r is the permittivity of Silicon substrate xd is width of the depletion layer

The total capacitance ( F/m2 ) in the In accumulation mode, the capacitance in depletion mode will be given by CC C  oxd ε ox 2 CCoxd Cox F/ m tox 11  11tx  oxd where, ε 3 . 9 ε is the permittivity of o x 0 CCoxd εεoxsi oxide layer 12 ε8.8510F/m0  3.11.3 INVERSION MODE

Note: With N-type substrate, there will be When VG ≥ VT, the minority charge carriers accumulation of electrons. in the p-type substrate (electrons) are attracted towards oxide semiconductor 3.11.2 DEPLETION MODE interface i.e. an inversion layer of negatively charged carriers is formed.In When VFB < VG < VT (small positive gate voltage), the positively charged carriers inversion mobile carriers of the opposite will be repelled away from the oxide type to the body aggregate at the surface to semiconductor interface (note that this invert the conductivity type. voltage is not sufficiently strong to attract the minority charge carriers in the substrate) & a depletion region is formed which is devoid of any mobile carriers leaving only ions.

Note: With N-type substrate, inversion layer is formed due to holes. In inversion mode, the capacitance in given by

In depletion mode there will be two The two voltages that separate the three capacitances in series modes are 1) Oxide capacitance

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission a) Flat band VoltageVFB which separates the accumulation mode from the depletion mode b) Threshold Voltage VT which separates the depletion mode from the inversion mode.

3.11.4 CAPACITANCE CURVE

Where, CCm a x o x

CCoxdmin Cmin  CCoxdmin Cdwill be minimum when xdis maximum.

Note: At high frequency (of gate voltage), inversion layer cannot form hence for high MOSFET stands for metal oxide frequency the capacitance remain semiconductor field effect transistor. It has minimum in inversion mode also. four terminals gate, source drain and Example substrate or body. The drain and source The oxide thickness is 100 nm. Assume terminals are connected to the heavily 2 MOS has area of 1 cm . Calculate Cox. doped regions. The gate terminal is Solution connected top on the oxide layer. The oxide we know, layer results in an extremely high input ε resistance 1010to1015Ω for the MOSFET. CF/ m ox 2 ox The metal of the gate terminal and the SC tox εA acts the parallel plates and the oxide layer CF ox acts as insulator of the state MOS capacitor. ox t ox Between the drain and source terminal ε3.9εox0 there is space for flow of carriers & it is 3.9 8.85 10(F/14 cm) 1cm 2 called channel region. The voltage applied ∴ Cox  at the gate terminal is used to control the 105 cm charge carriers in the channel i.e. drain 3.4710F8 current can be controlled using VGShence it is a voltage controlled device. There are 3.12 METAL OXIDE SEMICONDUCTOR two types of MOSFET FET 1) Depletion MOSFET 2) Enhancement MOSFET

3.13 DEPLETION MOSFET

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 2) When –veVGS is applied, the holes from P-type substrate will be attracted in the channel (remember accumulation mode of MOS capacitor). Due to accumulation of holes the majority carriers in the channel (electrons) will recombine with the holes results in decrease in majority carrier concentration in the channel, hence drain current ID decreases. 3) For a particular value of VGS called VGS(cut−off) , due to large no. of recombinations the majority carriers in the will be zero & hence drain current becomes zero.

3.13.2 ENHANCEMENT MODE

In enhancement mode the applied VGS In depletion MOSFET the conduction increase the majority charge carriers channel is physically implanted (rather (electrons in N-MOS) in the channel. than induced). Thus, for a depletion NMOS transistor, the channel conducts even if no gate to source voltage applied. Depending upon the polarity of applied Gate voltage with respect to source (VGS), a depletion MOSFET operates in two modes

3.13.1 DEPLETION MODE

In depletion mode the applied VGS decrease the majority charge carriers (electrons in N-MOS) in the channel. Due to applied VDS an electric field induces in the channel & 1) When V = 0 V , minimum no. of electrons flow from source to drain results GS electrons flow from source to drain, in drain current. hence drain current is minimum IDSS. 2) When positive VGS < VT is applied, the electron concentration in the channel will not be affected i.e no inversion layer will form & same number of electrons will flow through channel & hence drain current remains minimum i.e. IDSS. 3) When VGS ≥ VT is applied, the electrons in the p-type substrate will be attracted in the channel i.e. the majority carriers 1) When V = 0 V , maximum no. of GS increases in the channel & hence drain electrons flow from source to drain, current increases. hence drain current is maximum IDSS. 3.13.3 TRANSFER CHARACTERISTICS

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 3.14.1 TRANSFER CHARACTERISTICS

(Varying VGS& keeping VDSconstant)

3.13.4 DRAIN CHARACTERISTICS

1) When VGS = 0 V, the gate metal will be at zero volts & no channel will be induced & drain current IDis 0. 2) When V < V (where V is called 3.14 ENHANCEMENT MOSFET GS T T threshold voltage) is applied, again no channel will be induced &I = 0. In enhancement MOSFET, also called a E- D 3) When V ≥ V is applied, the electrons MOSFET, channel is absent between source GS T in the P-type substrate will attracted & drain for conduction. When proper gate towards oxide layer & an inversion to source voltage is applied a channel is layer is formed. This inversion layer of induced between source & drain. Also an electrons acts as channel for N-channel Enhancement MOSFET operates only in enhancement MOSFET. With the enhancement mode. creation of channel, MOSFET starts conducting & current IDflows through device. With increase in VGSmore no of electrons are attracted in the channel & drain current increases.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission increases & the drain current increases linearly with applied VDS.

3.14.2 DRAIN CHARACTERISTICS

3) When VDS becomes VDS(sat) = VGS − VT (Varying VDS& keeping VGSconstant) (saturation voltage or overdrive voltage), the channel width reduces to When proper gate to source voltage i.e. zero i.e. channel is pinched off at drain VGS ≥ VT is applied, a channel will induce & end but due to a very strong electric device starts conducting. field the charge carriers (electrons) are able to cross the depletion layer hence drain current continues to flow. 4) VDS(sat) > VGS − VT, the pinch off point shifts towards source. This process where the length of channel can be varied with applied VDSis called channel length modulation.

1) For small values of appliedVDS , the channel between source & drain is almost flat as shown in figure. With the application ofVDS, an electric is induced in the channel which directs from drain to source & this field is responsible for the flow of electrons in N-channel & hence drain currentID. 5) At VDS = VDS(sat) , the velocity of 2) With increase in VDS , the reverse electrons almost saturates & hence for biasing of drain to body junction VDS ≥ VDS(sat) the drain current increases which results in penetration IDremains constant. of depletion layer into channel & channel width gets tapered towards drain end as shown in figure below. With decrease in channel width the resistance of channel increases but at the same time field in the channel

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission  In saturation region, a MOSFET can used as a voltage controlled constant current source (in saturation current ID is almost constant & with change in VGS we get another constant current curve).

3.14.4 BODY EFFECT

In MOSFET the source to body junction & drain to body junction must always be reverse biased in order to avoid conduction between S-B & D-B. In most of the cases source & body are connected together so that VSB = 0 V i.e. no potential difference between source & body. 3.14.3 OPERATING REGIONS If source is biased at higher voltage than body i.e. VSB > 0 V, the reverse biasing of  CUT-OFF source to body increases & the depletion VGS < VT layer width increases. This increase in In cut-off no channel is induced & hence depletion layer will make it difficult for ID = 0 applied VGS to create a channel i.e. the  TRIODE REGION threshold voltage VTof MOSFET increases. VV&VVGSTDSDS(sat)

In triode region ID increases almost linearly with VDS. 2 W VDS IDnoxGSTDS μ C(VV )V  L2  SATURATION REGION VV&VVGSTDSDS(sat)

In saturation region IDis constant i.e. it is independent of VDS. 1W I μC(VV ) 2 DnoxGST2L 3.14.5 THRESHOLD VOLTAGE 1 2 IK(VV)DnGST  It is the minimum value of VGSfor which 2 enhancement MOSFET enters into 2 I(VV)DGST conduction. Therefore it should be as W small as possible. Where, Knnox μC is called L  VTis positive for N-channel MOSFET & it transconductance parameter is negative for P-channel MOSFET.  Magnitude of VTis around 1 V. Note: VVTT0 γ| 2V ||fSB 2| f   In triode or ohmic region, a MOSFET Where, V is V when V = 0 can be used as voltage variable resistor T0 T SB 2qN ε (in linear region it follows Ohm’s law γ  A si is called body effect like resistor & with change in VGS we Cox get another linear curve). parameter.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 2 Coxis oxide capacitance in F/m kT NA f lnlna is called substrate Fermi qni potential. NA is doping concentration in P-type substrate k is boltzmann’s constant k8.6210eV /K5o

εs ε i ε0 r(s i)

niis intrinsic carrier concentration VSBis source to body voltage

Note:VTdecreases approximately by 2mV for 1o rise in temperature.

3.14.6 PROCEDURE TO REDUCE 퐕퐓

1) Choice of Gate Electrode: Threshold voltage can be reduced by using N+ doped poly silicon gate for N-channel MOSFET & P+ doped poly silicon gate for P-channel MOSFET. 2) Ion Implantation: By implanting dopants through the gate conducting layer and gate insulating layer and deposit the dopants into the superficial portion of the substrate below the gate insulating layer.

3.15 COMPARISON BETWEEN MOSFET & JFET

1) Gate leakage current in MOSFET is of the order of 10−12A, hence the input impedance is very high 1010 to 1015 Ω . 2) The drain characteristics of JFET are flatter than that of MOSFET, hence the drain resistance of JFET (0.1 to 1 M Ω) is much higher than that of MOSFET (1 to 50 K Ω). 3) As compared to JFET, MOSFETs are easier to fabricate

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission GATE QUESTIONS

Q.1 MOSFET can be used as a concentration in the base is a) Current controlled capacitor increased. Which one of the b) Voltage controlled capacitor following is correct? c) Current controlled inductor a) S1 is False and S2 is TRUE d) Voltage controlled inductor b) both S1 and S2 are TRUE [GATE-2001] c)both S1 and S2 are FALSE d) S1 is TRUE and S2 is FALSE Q.2 The effective channel length of a [GATE-2004] MOSFET in saturation decreases with increase in Q.6 The phenomenon known as “Early a) Gate voltage Effect” in a bipolar transistor refers b) Drain voltage to a reduction of the effective base- c) Source voltage width caused by d) Body voltage a) electron–hole recombination at [GATE-2001] the base b) the reverse biasing of the base– Q.3 For an n-channel enhancement type collector junction MOSFET, if the source is connected c) the forward biasing of emitter– at a higher potential than that of the bias junction bulk (i.e. VSB> 0 volts), the threshold d) the early removal of stored base voltage VT of the MOSFET will charge during saturation-to- a) Remain unchanged cutoff switching b) Decrease [GATE-2006] c) Change polarity d) Increase Q.7 The drain current of MOSFET in [GATE-2003] saturation is given by 2 ID =K() V GS -V T where K is a Q.4 If for a silicon n-p-n transistor, the constant. The magnitude of the base to emitter voltage (VBE) is 0.7 transconductance is volts and the collector to base gm 2 voltage (VCB) is 0.2 volts, then the K() VGS -V T transistor is operating in the a) b) 2K() VGS -V T V a) Normal active mode DS 2 b) Saturation mode I K() V -V c) d d) GS T c) Inverse active mode VGS -V DS VGS d) Cutoff mode [GATE-2008] [GATE-2004] Q.8 The measured transconductance g Q.5 Consider the following statements m S1 and S2. of an NOMS transistor operating in the linear region is plotted against reduces if the base width is the gate voltage V at a constant increased.S1: The β of a bipolar transistor drain voltage V . Which of the following figures Grepresents the D increases if the doping expected dependence gm on VG ? S2: The β of a bipolar transistor

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Which of the following is correct? a) Only S2 is true b) Both S1 and S2 are false c) Both S1 and S2 are true, but S2 is not a reason for S1 a) b) d) Both S1 and S2 are true, and S2 is a reason for S1 [GATE-2009]

Q.11 At room temperature, a possible value for the mobility of electrons in c) d) the inversion layer of a silicon n- [GATE-2008] channel MOSFET is a) 450cm2 /V-s b)1350cm2 /V-s Q.9 The cross section of a JFET is shown c)1800cm2 /V-s d) 3600cm2 /V-s in the following figure. Let V be - G [GATE-2010] 2V and let Vp be the initial pinch-off voltage. If the width W is doubled Q.12 In a uniformly doped BJT, assume

(with other geometrical parameters that NEB ,N and NC are the emitter, and doping levels remaining the base and collector doping in atoms / same), then the ratio between the 3 cm , respectively. If the emitter mutual trans conductance’s of the injection efficiency of the BJT is initial and the modified JFET is close to unity, which one of the following conditions is TRUE?

a) NEBC =N =N

b) NE> N B and N> BC>N

c) NEB =N and N BC

d) NEBC

Common Data for Q.13 and Q.14 1 1- 2/Vp a) 4 b) The channel resistance of an N- channel 2 1- 1/ 2V ()p JFET shown in the figure below is 600 when the full channel thickness (t ) of 10 1- 2/Vp 1-() 2/ Vp Ω c) d) m is available for conduction. The built-in voltage of the gate P+N junction (chV )is -1 1- 1/() 2Vp 1-() 1/2 Vp .µWhen the gate to source voltage (V ) is 0 [GATE-2008] V , the channel Is depleted by 1 m onbi each side due to the built -in voltage andGS hence Q.10 Consider the following two the thickness available for conditionµ is statements about the internal only 8 m conditions in an n-channel MOSFET operating in the active region µ S1:The inversion charge decrease from source to drain S2:The channel potential increase from source to drain

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.13 The channel resistance when Q.17 The gate source overlap capacitance V = 0Vis is approximately a) 480 b) 600 a)0.7fF b)0.7pF c)GS750 d) 1000 c)0.35fF d)0.24pF Ω [GATEΩ-2011] [GATE-2012] Ω Ω Q.14 The channel resistance when Q.18 If fixed positive charges are present V = 3Vis in the gate oxide of an n-channel a) 360 b) 917 enhancement type MOSFET, it will c)GS1000− d) 3000 lead to Ω [GATEΩ-2011] a) a decrease in the threshold Ω Ω voltage Q.15 The source of a silicon b) channel length modulation 10 3 c) an increase in substrate leakage ()ni =10 percm n-channel MOS current transistor has an area of 1 sq m d) an increase in accumulation and a depth of 1 m . If the dopant capacitance density in the source is 10 /cmµ , [GATE-2014-1] the number of holesµ in the19 source3 region with the above volume is Q.19 A BJT is biased in forward active approximately mode, Assume VBE = 0.7V, kT / q = a)10 b)100 25mV and reverse saturation c)10 7 d)0 current Is=10-13 A. The [GATE-2011] transconductance of the BJT (in mA/V) is ______. Common Data for Question 16 and 17 [GATE-2014-1] In the three dimensional view of a silicon n- channel MOS transistor shown below, =20 Q.20 A depletion type N-channel MOSFET nm.The transistor is of width 1 m . The is biased in its linear region for use depletion width formed at everyδ pn as a voltage controlled resistor. junction, is 10nm. The µ relative Assume threshold voltage VTH = permittivity’s of Si andO , respectively , are W 0.5V, VGs = 2.0V, VDS = 5 V, L = 11.7 and 3.9 and = −12 ε0 8.9x102 F / m. 100, C =10-8F/cm2 and n = 800 cm2 /V — s. The value of �the resistance0x of the voltage µcontrolled

[GATE-2014-1] resistor (in Ω) is______. Q.21 An increase in the base recombination of a BJT will increase a) the common emitter dc current gain Q.16 The source body junction b) the breakdown voltage BVCE0 capacitance is approximately c) the unityβ -gain cut-off frequency a)2 fF b)7fF fT c)2pF d)7 pF d) the transconductance gm [GATE-2012] [GATE-14-2]

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.22 In CMOS technology, shallow P-well identical, kT/q = 26 mV, the intrinsic or N-well regions can be formed carrier concentration is 1 x 1010 cm- using 3, and q = 1.6 × 10-19 C, the a) low pressure chemical vapour difference between the base-emitter deposition voltages (in mV) of the two BJTs b) low energy sputtering (i.e., VBE1 — VBE2 )is ______. c) low temperature dry oxidation [GATE-2014-4] d) low energy ion-implantation [GATE-2014-2] Q.27 A BJT in a common-base configuration is used to amplify a Q.23 In MOSFET fabrication, the channel length is defined during the process Assume kT/q = 25 mV. The value of of thesignal collector received bias by current a 50Ω antenna.(in mA) a) Isolation oxide growth required to match the input b) Channel stop implantation impedance of the amplifier to the c) Poly-silicon gate patterning impedance of the antenna is d) Lithography step leading to the ______. contact pads [GATE-2014-4] [GATE-2014-3] Q.28 For the NMOSFET in the circuit Q.24 The slope of the ID vs VGS curve of an shown, the threshold voltage is V , n-channel MOSFET in linear regime where V > 0 . The source voltage th is 10-3 -1 at VDS = 0.1 V. For the V is varied from 0 to V . same device, neglecting channel Neglectingth the channel length length Ωmodulation, the slope of the modulss ation, the drain current I DD as a I vs VGS curve (in A /V) function V is represented by. D under saturation regime is D ss approximately� ______√ [GATE-2014-3]

Q.25 An ideal MOS capacitor has boron doping-concentration of 1015 cm-3 in the substrate. When a gate voltage is applied, a depletion region of width 0.5 m is formed with a a) b) surface (channel) potential of 0.2 V. Given thatµ |= 8.854 x 10-14 F/cm and the relative permittivities of silicon andεo silicon dioxide are 12 and 4, respectively, the peak electric field (in V/ m) in the oxide region is ______. c) d) µ[GATE-2014-3]

Q.26 Consider two BJTs biased at the same collector current with area A = 0. m × 0. and A2 = 300µm x 300µm . Assuming that all [GATE-2015-1] other1 2µdevice 2µmparameters are

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.29 A MOSFET in saturation has a drain a) Current gain will increase current of lmA for V = 0.5V . If the b) Unity gain frequency will channel length modulation increase coefficient is 0.05 VDS , the output c) Emitter base junction −1 capacitance will increase ______. d) Early voltage will increase resistance (in kΩ) of[GATE the MOSFET-2015- 1]is [GATE-2015-3]

Q.30 In a MOS capacitor with an oxide Q.34 An npn BJT having reverse layer thickness of 10 nm, the saturation current I = 10 A is maximum depletion layer thickness biased in the forward active−15 region is 100 nm. The permittivities of the with V = 700 mV.s The thermal semiconductor and the oxide layer voltage ( V ) is 25 mV and the are and respectively. currentBE gain ( ) may vary from 50 Assuming / = 3, the ratio of the to 150 dueT to manufacturing maximumεs capacitanceεox to the variations. Theβ maximum emitter minimum εcapacitances εox of this MOS current ( in A) is ______. capacitor is ______[GATE-2015-3] [GATE-2015-2] µ Q.35 Consider the following statements Q.31 Which one of the following for a metal oxide semiconductor processes is preferred to from the field effect transistor (MOSFET): gate dielectric (SiO ) of MOSFETs? P: As channel length reduces, OFF- a)Sputtering state current increases. b) Molecular beam 2epitaxy Q: As channel length reduces, c) Wet oxidation output resistance increases. d) Dry oxidation R: As channel length reduces, [GATE-2015-3] threshold voltage remains constant. Q.32 The current in an enhancement S: As channel length reduces, ON mode NMOS transistor biased in current increases. saturation mode was measured to Which of the above statements are be 1 mA at a drain-source voltage of INCORRECT? 5 V. When the drain-source voltage a) P and Q b) P and S was increased to 6 V while keeping c) Q and R d) R and S gate-source voltage same, the drain [GATE-2016-1] current increased to 1.02 mA. Assume that drain to source Q.36 What is the voltage V in the saturation voltages is much smaller following circuit? than the applied drain-source out voltage. The channel length modulation parameter (in V ) is ______. −1 [GATEλ -2015-3]

Q.33 If the base width in a bipolar junction transistor is doubled, which one of the following statements will be TRUE?

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission a) OV b) 6.0× 10 cm c) 7.2 × 1011 cm−2 b) ( VTT of PMOS+ V of NMOS) / 2 c) Switching threshold of inverter d) 8.4 × 10 11 cm −2 11 −2 [GATE-2016-2] d) VDD [GATE-2016-1] Q.40 The Ebers-Moll model of a BJT is valid Q.37 Consider an n-channel metal oxide a) only in active mode semiconductor field effect transistor b) only in active and saturation (MOSFET) with a gate-to source modes voltage of 1.8 V. Assume that =4, c) only in active and cut-off modes C = 70 × 10 AV , W the d) in active, saturation and cut-off L threshold voltage−6 is −20.3V, and the modes channelµN ox length modulation [GATE-2016-2] parameter is 0.09 V . In the saturation region, −1the drain Q.41 Consider a long-channel NMOS conductance (in micro seimens) is transistor with source and body ______. connected together. Assume that the [GATE-2016-1] electron mobility is independent of V and VDs. Given, gm = 0.5 A/V for A long-channel NMOS transistor is VDS = 50 mV and VGS= 2 V, Q.38 GS biased in the linear region with V gd = 8 A/V for VGS = 2 V andµ VDS = 0

= 50mV and is used as a resistance. ∂ID DS V, Whereµ gm = and gd = Which one of the following ∂VGS statements is NOT correct? ∂I a) If the device width W is D . The threshold voltage (in ∂V increased, the resistance DS decreases. volts) of the transistor is ______. b) If the threshold voltage is [GATE-2016-2] reduced, the resistance decreases. Q.42 The figure shows the band diagram c) If the device length L is of a Metal Oxide Semiconductor increased, the resistance (MOS). The surface region of this increases. MOS is in d) If V is increased, the resistance increases. GS [GATE-2016-2]

Q.39 A voltage V is applied across a MOS capacitor with metal gate and p-type silicon substrateG at T = 300K.The inversion carrier density (in number of carriers per unit area) for V = 0.8 V is 2 × 10 cm . For V = 1.3V, G the inversion11 carrier−2 density is 4× a) inversion b) accumulation 10 cm .What is the valueG of the c) depletion d) flat band inversion11 −2 carrier density for V = 1.8 [GATE-2016-2] V? a) 4.5 × 10 cm Q.43 Figures I and II show two MOS 11 −2

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission capacitors of unit area. The for base, ∆nC for collector) capacitor in Figure I has insulator normalized to equilibrium minority materials X (of thickness t1 = 1 nm and dielectric constant = 4) and Y carrier concentration (nE0 for (of thickness t2 = 3 nm and dielectric emitter, pB0 for base, nC0 for constant = 20). The εcapacitor1 in collector) in the quasi-neutral Figure II has only insulator material emitter, base and collector regions 2 X of thicknessε tEq. If the capacitors are shown below. Which one of the are of equal capacitance, then the following biasing modes is the value of tEq (in nm) is ______. transistor operating in?

[GATE-2016-3] a) Forward active b) Saturation

Q.44 The injected excess electron c) Inverse active d) Cutoff concentration profile in the base region of an npn BJT, biased in the [GATE-2017-1] active region, is linear, as shown in the figure. If the area of the emitter- base junction is 0.001 cm2, = Q.46 An npn bipolar junction transistor 800cm /(V-s) in the base region n (BJT) is operating in the active and depletion2 layer widths µare region. If the reverse bias across the negligible, then the collector current base – collector junction is Ic (in mA) at room temperature is increased, then ______. a) the effective base width increases and common – emitter current gain increases b) the effective base width increases and common – emitter current gain decreases c) the effective base width decreases and common – emitter current gain (Given: thermal voltage VT = 26 mV increases at room temperature, electronic d) the effective base width charge q =1.6 × 10-19 C) [GATE-2016-3] decreases and common – emitter current gain decreases Q.45 For a narrow base PNP BJT, the excess minority carrier [GATE-2017-2]

concentration ( ∆nE for emitter, ∆pB

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.47 Two n-channel MOSFETs, T1 and T2, Q.48 Assuming that transistors M1 and are identical in all respects except M2 are identical and have a that the width of T2 is double that of threshold voltage of 1V, the state of T1. Both the transistors are biased transistors M1 and M2 are in the saturation region of operation, but the gate overdrive respectively. voltage (VGS-VTH) of T2 is double that of T1, where VGS and VTH are the gate – to – source voltage and threshold voltage of the transistors, respectively. If the drain current and transconductance of T1 are ID1 and gm1 respectively, the corresponding values of these two parameters for T2 are

a) 8ID1 and 2gm1

b) 8ID1 and 4gm1 a) Saturation, Saturation c) 4ID1 and 4gm1 b) Linear, Linear c) Linear, Saturation d) 4ID1 and 2gm1 d)Saturation,Linear

[GATE-2017-2] [GATE-2017-2]

ANSWER KEY:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 (b) (b) (d) (a) (d) (b) (b) (c) (b) (d) (b) (b) (c) (c) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (d) (a) (a) (a) 5.785 500 (b) (d) (c) 0.07 2.4 381 0.5 (a) 29 30 31 32 33 34 35 36 37 38 39 40 41 42 20 4.33 (d) 0.022 (d) 1475 (c) (c) 28.47 (d) (b) (d) 1.2 (a) 43 44 45 46 47 48 1.6 6.65 (c) (b) (b) (c)

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission EXPLANATIONS

Q.1 (b) Early effect refers to a reduction of Voltage controlled capacitor. effective base width caused by the reverse bias of collector–base Q.2 (b) junction. At the edge of saturation i.e. when drain to source voltage reaches Q.7 (b) the inversion layer charge at ∂I g=D = 2K() V − V the drain end becomes zero m GS T 𝐷𝐷𝑠𝑠𝑠𝑠𝑠𝑠 ∂VGS (ideally).𝑉𝑉 The channel is said to be pinched off at the drain end. If the Q.8 (c) drain to source voltage is In linear region increased even further beyond the W1 𝐷𝐷𝐷𝐷 ='2 −− saturation edge so that 𝑉𝑉 > ID K n() V GS VV T DS V DS , an even larger portion of the L2 𝐷𝐷𝐷𝐷 ∂ channel becomes pinched off𝑉𝑉 and ID ' W 𝐷𝐷𝑠𝑠𝑠𝑠𝑠𝑠 gm= = KV n DS effective𝑉𝑉 channel length is reduced. ∂VLGS So Q.3 (d) g remains constant with V . In saturation region VV= +γ2 − + V −− 2 m GS T To ΦFF SB Φ 1W' 2 =substrate bias coefficient ID= K n() VV GS − Th 2L V =substrate bias voltage W γ gK=' () VV − SB m n GS Th Q.4 (a) L As V = 0.7, i.e. positive, the base emitter junction of n-p-n transistor Q.9 (b) is forwardBE biased& as V = 0.2V i.e. positive, collector base junction is Q.10 (d) reverse biased. ThereforeCB the From source to drain channel transistor is operating in normal potential increases, so inversion active region. charge reduces from source to drain. Q.5 (d) I α Q.11 (b) β =C = The mobility of electrons in Si is I1− α B 1350cm2 / V− sec When base width increases, recombination in base region Q.12 (b) increases and decreases & hence N? N andN> N , for emitter decreases. E B BC If doping in base𝛂𝛂 region increases, injection efficiency of BJT close to thenβ recombination in base unity. increases and decreases thereby decreasing . Q.13 (c) α 1 rdonα Q.6 (b) β tOh

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission At V= 0, t = 10μm;  A  A GS Ch C =11 = 0 r1 1 g dd (Given rd 600Ω ) 11 10 1 = 3.9as between gate and source r=×← 600 at8μm = 750Ω d there is Si 2 8 𝑟𝑟 𝜖𝜖 A11 =μm × δ 𝑂𝑂 Q.14 (c) =×××1 10−−69 20 10 Width of the depletion large W =2 × 10−14 m 2

αVbi+ V GS d = 1 nm = 10 m So −9 W −−13 1 2 = 8.9× 10−−12 × 3.9 ×× 2 10 14 W1− C = 1 g 10−9 ⇒=w21 2w = 2() 1μm = 2μm −17 Cg = 69.42 × 10 F So that channel thickness C= 0.69 × 10−15 =10 −= 4 6µm g = m 750 Cg 0.7fF m ? 8µ 8− Q.18 (a) r=×= 750 1000Ω 6µd 6− Q.19 (5.785) KT Q.15 (d) VBE = 0.7V, = 25 mV, Is =10-13 10 3 19 3 niD= 10 / cm andN = 10 / cm q

2 IC n Transconductance, gm = ∴=Pi = 10as VT ND V /V So holes in volume v is = pV = IC = Is [ e BE T -1] 10 , since holes number cannot =10 13 [ e0.7/25mV -1] = 144.625 mA − be − a11 decimal number so = 0 IC 144.625mA ∴=gm = VT 25mV Q.16 (a) 𝑝𝑝 =5.785 A /V Source body junction capacitor A 0rA Q.20 (500) C j = = dd Given VT = -0.5V; VGS= 2V, Here = 11.7 as there is Si W VDS = 5 V: L =100; capacitor -8 𝑟𝑟 C =10 f / cm 𝜖𝜖 12 2 A1=μm × 0.2μm = 0.2 ×− 10 m =800 cm�2 / v - s θx d =depletion width of p-n junction 1W n 2 d = 10mm = 10 m D0=×μCn2V()GS −− V T DS VIV D S µ2 L  so −8 −1 −−12 12 ∂I 8.9× 10 × 11.7 ×× 0.2 10 D = = rds C j −8 ∂ 10 VDS −15 −1 Cj = 2.082 × 10 F ∂ 1W μC 2V()−− V V V 2 = n 0x GS T DS DS Cj 2fF ∂V2DS  L WW =[μC (V −− V) μC V ]−1 a Q.17 (a) n 0xLL GS T n 0x DS Gate source capacitance is

𝐶𝐶𝑔𝑔

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission I V−= V V ln S2 1 BE1 BE2 T ⇒=r IS1 ds W μ C (V−− V V 3 300× 300 n 0xL GS T DS = 26 ×10 ln  − 0.2× 0.2 1 = = 500Ω IS A(VBE1 VBE2) = 381mV 800× 10−8 × 100(2 +− 0.5 5) Q.27 (∵0.5α) − Q.21 (B) Input impedance of CB amplifier, VΙ z =rei = Q.22 (D) ΙE 25mV Q.23 (C) ⇒=50 ( signal is received ΙE Q.24 (0.07) ∵ T= 25 mV) 25m V In linear region, ⇒= = fromΙE 50Ω antenna 0.5mA and V 2 50Ω VDS ID = k()VGS−− VV T DS 2 Q.28 (a) ∂ID −3 V = V =10 = kVDS ∂VGS Hence MOS Transistor is in saturation.GS DS V 2 ∴V is small.DS neglected In saturation, DS 2 I= k(V − V )22 = k(V −− V V ) 10−3 D GS r DD ss T ⇒=K = 0.01 As V (Not linearly because 0.1 square factor) In Saturation region , Hencess ↑option𝐼𝐼𝐷𝐷 ↓ (a) correct 1 2 IVkV()GD ST−= 2 Q.29 (20) k Under channel length modulation I= (V − V ) D2 GS T I = I (1+ V ) dI 1 ∂ I k 0.01 D D =Dsat = λI DS D = = = 0.07 dV r Dsatλ ∂V22 DS 0 GS 11 r = = 0 λI 0.05× 10−3 Q.25 (2.4) Dsat 2× 0.2 E= = 0.8v / m s 0.5 Q.30 (4=.33 20) kΩ E E=s E = 2.4v /μ m  oxE s ox ox Ct μ max= ox C ox s Q.26 (381) min × tX II= (Given) ox dmax CC12 ox s VBE1 VBE 2 + VV TT tXox dmax IeS1= Ie S2

(VBE1− V BE 2 )  I Xdmax ox e VT = S2 =+×1 t  IS1 ox x

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 100 1 So option (C) is matching =+1 ×= 4.33 10 3 Q.36 (c) The transfer characteristics of the Q.31 (d) CMOS inverter is as follows Q.32 (0.022) NMOS SATURATION

ID= 1mA@V DS = 5V

ID= 1.02mA@V DS = 6V

VVDSat= DS 2 ID=−+ k(V GS V T ) (1 λV DS )

ID= k'(1 + λV DS ) 10−3 = k'(1 + λ5) 1.02×=+ 10−3 k'(1 6λ) Since the inverter is connected in 16+ λ 1.02= ⇒+=+1.02 5.1λ 1 6λ feedback loop formed by connecting 15+ λ 10X resistor between the output 0.02= 0.9λ and input, the output goes and stays λ= 0.022V−1 at theΩ middle of the characteristics VV+ V = IR IH Q.33 (d) a 2 W doubled (increased) early V effect is still present but its effect a B less severe relative to previous→ W . ⇒ Switching threshold of inverter Slope I Vs V decreases Q.37 (28.47) B 1W 2 = −+ c CE IDSμ N C ox()() V GS V T 1 λV DS Q.34 (1475) 2L VBE dI 1W 2 II V DS Cs T gds==×−λ μC n 0() V GS V T IeB = = ββ dVDS 2 L = 0 09××0.5 70 × 10−62 × 4(1.8 − 0.3). I(EB=β + 1)I β1+ VBE =28.47 s = I .e VT a β s Q.38 (d) µ 700× 10−3 −3 1 ()1.02() 10−−96×= 10 e 25× 10 R = on k (V− V ) = 1475 A n GS t W kn= μc n ox . Q.35 (c) µ L 1 L →∞ ↓↑ So, R on = I so L IOFF − L μn c ox W(V GS V t ) ∂V L →=r DS = d Q.39 (b) ∂IDμ n C ox W(V us − V t− V DS ) Qinv=−> k() V GS V t ,V GS V t So Lr↓↓d = qN if the channel length reduces, then Qinv threshold voltage also changes qN = k(V i V ) →LI↓↓ Given ON i GS − t

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Case (i) EE = 12 q( 2× 10 cm ) = k(0.8 V ) Et12+ Et 21 11 −2 t 4× 20 Case (ii) − = = 2.5 q( 4 × 10 cm ) = k(1.3 V ) ()4×+ 2 (20 × 1)

1.3− V11 −2 E1 4 t t C=⇒=2.5 ⇒ t = 1.6nm 2 = − II Eq 0.8− Vt ttEq Eq V = 1.3 V V = 0.3 Q.44 (6.65) t t 1.6‒2 × −11 dn t 2 10 −19 So, k = ××1.6 10 Icn≈ qAD 0.5 dx dn So, = −−19 11 19 qAμVnt 1.6×10 ×=××× Ni 4 10 1.6 10 (1.5) dx 14 N = 6 × 10 cm −−19 3 10− 0 =1.6 × 10 × 0.001 × 800 ×× 26 10 − 11 −2 × 4 i 0.5 10 Q.40 (d) Ic = 6.65mA Q.41 (1.2) From given conditions Q.45 (c) VDS GS — Vt , So transistor is linear ≤ V 2 As per the change carrier profile, VDS ID= k n() V GS —V t V DS − base – to – emitter junction is 2 reverse bias and base to collector ∂ ID junction is forward bias, so it works = kVn. DS ∂VGS in Inverse active. 0.5× 10−6 1 k= =×= 10−−3 10 52 A/ v n 50× 10−3 100 Q.46 (c) ∂I D If the reverse bias voltage across the So, = kn .( V V ) VDS base collector junction is increased, −−65GS − t 8×= 10 10 [2 − Vt ] then their effective base width will

Vt =−= 2 0.8 1.2V decrease and collector current will increase, therefore their common- Q.42 (a) emitter current gain increases. The semiconductor used in the MOSFET is n-type. At the surface the Q.47 (b) intrinsic level is above EF as it is found at the distance of below EF, So, Drain current in saturation is the surface is in inversion region. 1W 2 I=µ− C[] VV Q.43 (1.6) D2L n OX GS TH

EE12 . For transmitter T1 tt C = 12 I EE 12+ tt12

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission IID= D1 VVG1> TH , so transistor M1 is ON but

∂ID1 working in linear region. ggm= m1 = ∂VGS ω =µ−C() VV n OXL GS TH

For transmitter T2

W21= 2W = 2W −=− ()()VVGS TH21 2VV GS TH

=2V()GS − V TH 1 2W 2 ID2=µ− n C OX 2V() GS V TH 2L

= 8ID2

∂ID2 gm2 = ∂VGS2 2W =µ−C x2() V V n OXL GS TH

= 4gm1

Q.48 (c)

If VVVD≥− G TH , then the transistor is working in saturation region

So for M2 transistor

VVVD2>− G2 TH 3V>−() 2.5 1 V

Assume that M1 is working in saturation, so that

IID1= D2

VVVGS1−= TH GS2 − V TH

2V= VG2 − V S2

=2.5V − VS2

∴=VS2 V D1 = 0.5V

Now for M1 transistor to work in

saturation VVVD1≥− G1 TH ,but it is not satisfied by M1 transistor and

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 4 IC FABRICATION

4.1 CLASSIFICATION chip may contain as few as tens of components to several thousand Integrated circuits offer a wide range of components. The fabrication of discrete applications and could be broadly classified devices such as transistor, diode or an as: integrated circuit in general can be done by 1) Digital ICs the same technology. The various 2) Linear ICs processes usually take place through a Based upon the requirements, two single plane and therefore, the technology distinctly different IC technologies namely, is referred to as planar technology. A Monolithic technology and Hybrid simple circuit, when fabricated by silicon technology have been developed. In planar technology will have the cross monolithic integrated circuits, all circuit sectional view shown in Fig. components, both active and passive elements and their interconnections are manufactured into or on top of a single chip of silicon. In hybrid circuits, separate component parts are attached to a ceramic substrate and interconnected by means of either metallization pattern or wire bonds.

Complete cross sectional view when circuit is transformed into monolithic form An IC in general, consists of four distinct layers, as follows:

Layer No. 1 (~ 400 m) is a p-type silicon substrate upon which the integrated circuit 4.2 MONOLITHIC IC TECHNOLOGY is fabricated. μ

A monolithic circuit means a circuit Layer No. 2 (~ 5–25 m) is a thin n-type fabricated from a single stone or a single material grown as a single crystal extension crystal. The origin of the word ‘monolithic’ of the substrate usingμ epitaxial deposition is from the Greek word moons meaning technique. All active and passive ‘single’ and litho meaning ‘stone’. So components are fabricated within this layer monolithic integrated circuits are, in fact, using selective diffusion of impurities. made in a single piece of single crystal silicon. Layer No. 3 (0.02–2 m) is a very thin SiO2 A standard 10 cm diameter wafer can be layer for preventing diffusion of impurities divided into approximately 8000 wherever not μ required using rectangular chips of sides 1 mm. Each IC photolithographic technique.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Layer No. 4 (~ 1 m) is an aluminium layer rotated in opposite directions in order to used for obtaining interconnection produce ingots of circular cross-section. between components.μ The diameter of the ingot is controlled by the pulling rate and the melt temperature. 4.3 BASIC PLANER PROCESS Ingot diameter of about 10 to 15 cm is common and ingot length is generally of The basic processes used to fabricate ICs the order of 100 cm. Next the top and using silicon planar technology can be bottom portions of the ingot are cut off and categorized as follows: the ingot surface is ground to produce an 1) Silicon wafer (substrate) preparation exact diameter (D = 10, 12.5, 15 cm). The 2) Epitaxial growth ingot is also ground flat slightly along the 3) Oxidation length to get a reference plane. The ingot is 4) Photolithography then sliced using a stainless steel saw blade 5) X ray & electron beam lithography with industrial diamonds embedded into 6) Diffusion the inner diameter cutting edge. This 7) Ion implantation produces circular wafers or slices as shown 8) Isolation techniques in figure. The orientation flat portion 9) Metallization serves as a useful reference plane for the 10) Assembly processing and packaging various processes described later. The silicon wafers so obtained have very rough 4.3.1 SILICON WAFER PREPARATION surface due to slicing operation. These wafers undergo a number of polishing The following steps are used in the steps to produce a flat surface. Then one preparation of Si-wafers: side of the wafer is given a final mirror- 1) Crystal growth and doping smooth highly polished finish, whereas the 2) Ingot trimming and grinding other side is simply lapped on an abrasive 3) Ingot slicing lapping machine to obtain an acceptable 4) Wafer polishing and etching degree of flatness. Finally, the wafers are 5) Wafer cleaning thoroughly rinsed and dried. A raw cut slice of thickness 23-40 mils produces wafers of The starting material for crystal growth is 16–32 mils thickness after all the polishing highly purified (99.99999) polycrystalline steps. These silicon wafers will contain silicon. The Czochralski crystal growth several hundred rectangular chips, each process is the most often used for one containing a complete integrated producing single crystal silicon ingots. The circuit. polycrystalline silicon together with an appropriate amount of dopant is put in a quartz crucible and is then placed in a furnace. The material is then heated to a temperature in excess of the silicon melting point of 1420°C. A small single crystal rod of silicon called a seed crystal is then dipped into the silicon-melt and slowly pulled out as shown in Fig. 1.5. As the seed crystal is pulled out of the melt, it brings with it a solidified mass of silicon with the same crystalline structure as that of seed crystal. During the crystal pulling process, the seed crystal and the crucible are

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission various gases required for the growth of desired epitaxial layers are introduced into the system through a control console.

4.3.3 OXIDATION

SiO2 has the property of preventing the diffusion of almost all impurities through it. After all the IC fabrication processes are It serves two very important purposes. complete, these wafers are sawed into 100 1. SiO2 is an extremely hard protective to 8000 rectangular chips having side of 10 coating and is unaffected by almost all to 1 mm. Each chip is a single IC and may re-agents except hydrofluoric acid. contain hundreds of components. The Thus, it stands against any wafer thickness therefore is so chosen that contamination. it is possible to separate chips without 2. By selective etching SiO2, diffusion of breaking and at the same time, it gives impurities through carefully defined sufficient mechanical strength to the IC windows in the SiO2 can be chip. accomplished to fabricate various components. 4.3.2 EPITAXIAL GROWTH The silicon wafers are stacked up in a quartz boat and then inserted into quartz The word epitaxial is derived from furnace tube. The Si-wafers are raised to a Greek word epic meaning ‘upon’ and the high temperature in the range of 950 to past tense of the word Tenino meaning 1115°C and at the same time, exposed to a ‘arranged’. So, one could describe epitaxial gas containing O2 or H2O or both. The as, arranging atoms in single crystal fashion chemical reaction is upon a single crystal substrate, so that the Si+ 2H2 O →+ SiO 22 2H resulting layer is an extension of the This oxidation process is called thermal substrate crystal structure. The basic oxidation because high temperature is used chemical reaction used for the epitaxial to grow the oxide layer. The thickness of growth of pure silicon is the hydrogen the film is governed by time, temperature reduction of silicon tetrachloride. and the moisture content. The thickness of

SiCl42++ 2H 1200°CSi 4HCl oxide layer is usually in the order of 0.02 to Mostly, epitaxial films with specific 2 m. impurity concentration are required. This is accomplished by introducing phosphine 4.3.4μ PHOTOLITHOGRAPHY (PH3) for the n-type and bi-borne (B2H6) for p-type doping into the silicon- With the help of photolithography, it has tetrachloride hydrogen gas stream. The become possible to produce process is carried out in a reaction microscopically small circuit and device chamber consisting of a long cylindrical patterns on Si-wafers. As many as 10,000 quartz tube encircled by an RF induction transistors can be fabricated on a 1 cm × 1 coil. Figure 1.7 shows the diagrammatic cm chip. The conventional representation of the system used. The photolithographic process uses ultraviolet silicon wafers are placed on a rectangular light exposure and device dimension or line graphite rod called a boat. width as small as 2 mm can be obtained. This boat is then placed in the reaction However, with the advent of latest chamber where the graphite is heated technology using X-ray or electron beam inductively to a temperature 1200°C. The lithographic techniques, it has become

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission possible to produce device dimension outlines the pattern cutting through the red down to sub-micron range (<1 m). mylar without damaging the clear layer Photolithography involves two processes, underneath. namely: μ This rubylith pattern of individual mask is 1) Making of a photographic mask photographed and then reduced in steps by 2) Photo etching a factor of 5 or 10 several times to finally The making of a photographic mask obtain the exact image size. The final image involves the following sequence of also must be repeated many times in a operations—first the preparation of initial matrix array, so that many ICs will be artwork and secondly, its reduction. The produced in one process. The photo initial layout or artwork of an IC is repeating is done with a step and repeat normally done at a scale several hundred camera. This is an imaging device with a times larger than the final dimensions of photographic plate on a movable platform. the finished monolithic circuit. This is Between exposures, the plate is moved in because, for a tiny chip, larger the artwork, equal steps so that successive images form more accurate is the final mask. For in an array. When the exposed plate is example, it is often required to make an developed, it becomes a master mask. The opening of width about 1 mil (25 m). masks, actually used in IC processing are Obviously, this cannot be managed by any made by contact printing from the master. draftsman even with his thinnest of sketchμ These working masks wear out with use pens. So the drawings are made magnified and are replaced as required. and often by a factor of 500. With this Photo-etching is used for the removal of magnification, it is easy to see that a width SiO2 from desired regions so that the of one mil is magnified to a width of 500 desired impurities can be diffused. The mils, that is, about 1.2 cm. Therefore, for a wafer is coated with a film of finished monolithic chip of area 50 mils × photosensitive emulsion (Kodak 50 mils, the artwork will be made on an Photoresist KPR). The thickness of the film area of about 60 cm × 60 cm. is in the range of 5000–10000 Å as shown This initial layout is then decomposed into in fig. (a). The mask negative of the desired several mask layers, each corresponding to pattern) as prepared by steps described a process step in the fabrication schedule, earlier is placed over the photoresist e.g., a mask for base diffusion, another for coated wafer as shown in Fig. (b). This is collector diffusion, another for now exposed to ultraviolet light, so that metallization and so on. KPR becomes polymerized beneath the For photographic purpose, artwork should transparent regions of the mask. The mask not contain any line drawings but must be is then removed and the wafer is developed of alternate clear and opaque regions. This using a chemical (trichloroethylene) which is accomplished by the use of clear Mylar dissolves the unexposed/unpolymerized coated with a sheet of red photographically regions on the photoresist and leaves the opaque Mylar (trade name-Rubylith). The pattern as shown in fig. (c). The red layer can be easily peeled off thus polymerized photoresist is next fixed or exposing clear areas with a knife edge from cured, so that it becomes immune to the regions where impurities have to be certain chemicals called etchants used in diffused. The artwork is usually produced subsequent processing steps. The chip is on a precision drafting machine, known as immersed in the etching solution of coordinatograph. The coordinatograph has hydrofluoric acid, which removes the SiO2 a cutting head that can be positioned from the areas which are not protected by accurately and moved along two KPR as shown in fig.(d). After diffusion of perpendicular axes. The coordinatograph impurities, the photoresist is removed with

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission a chemical solvent (hot H2SO4 ) and This is what puts an upper limit on the IC mechanical abrasion. device density using UV photolithography. The etching process described is a wet With the advent of X-ray and electron beam etching process and the chemical reagents lithography techniques, it has become used are in liquid form. A new process used possible to produce device dimensions these days is a dry etching process called down to submicron range (< 1 m). This is plasma etching. A major advantage of the due to much shorter wavelengths involved. dry etching process is that it is possible to With these techniques, MOSFETμ with gate achieve smaller line openings ( m) length as small as 0.25 m have been made. compared to wet process. ≤ 1μ 4.3.6 DIFFUSION μ

Another important process in the fabrication of monolithic ICs is the diffusion of impurities in the silicon chip. This uses a high temperature furnace having a flat temperature profile over a useful length (about 20” length). A quartz boat containing about 20 cleaned wafers is pushed into the hot zone with temperature maintained at about a 1000°C. Impurities to be diffused are rarely used in their elemental forms. Normally, compounds such as B2O3 (Boron oxide), BCl3 (Boron chloride) are used for Boron and P2O5 (Phosphorous pentaoxide) and POCl3 (Phosphorous oxychloride) are used as sources of Phosphorous. A carrier gas, such as dry oxygen or nitrogen is normally used for sweeping the impurity to the high temperature zone. The depth of diffusion depends upon the time of diffusion which normally extends to 2 hours. The diffusion of impurities normally takes place both laterally as well as vertically. Therefore, the actual junction profiles will be curved as shown in Fig. 1.9. However, for the sake of simplicity, lateral diffusion will be omitted in all the drawings. 4.3.5 XRAY & ELECTRON BEAM LITHOGRAPHY

With conventional ultraviolet (UV) photolithography process in which the UV wavelengths used are in the range, 0.3 to 0.4 m, the minimum device dimensions or line widths limited by diffraction effects to aroundμ five wavelengths or about 2 m.

μ

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 4.3.7 ION IMPLANTATION circuit, the diodes will be reverse biased providing electric isolation between these Ion implantation is the other technique islands. The different components are used to introduce impurities into a silicon fabricated in these isolation islands. The wafer. In this process, silicon wafers are concentration of the acceptor atoms in the placed in a vacuum chamber and are region between isolation islands is usually scanned by a beam of high-energy dopant kept much higher (p+) than the p-type ions (boron for p-type and phosphorus for substrate. This prevents the depletion n-type) as shown in Fig. 1.10. These ions region of the reverse biased diode from are accelerated by energies between 20 kV penetrating more into p+ region and to 250 kV. As the ions strike the silicon possibly connecting the isolation islands. wafers, they penetrate some small distance There is, however, one undesirable by- into the wafer. The depth of penetration of product of this isolation process. It is the any particular type of ion increases with presence of a transition capacitance at the increasing accelerating voltage. Ion isolating pn junctions, resulting in an implantation technique has two important inevitable capacitor coupling between the advantages. components and the substrate. These 1) It is performed at low temperatures. parasitic capacitances limit the Therefore, previously diffused regions performance of the circuit at high have a lesser tendency for lateral frequencies. But being economical, this spreading. technique is commonly used for general 2) In diffusion process, temperature has to purpose ICs. be controlled over a large area inside the oven, whereas in ion implantation technique, accelerating potential and the beam current are electrically controlled from outside.

4.3.8 ISOLATION

Since a number of components are fabricated on the same IC chip, it becomes 2) DIELECTRIC ISOLATION necessary to provide electrical isolation Here a layer of solid dielectric such as between different components and silicon dioxide or ruby completely interconnections. Various types of isolation surrounds each component, thereby techniques have been developed. However, producing isolation, both electrical and we shall discuss here only two commonly physical. This isolating dielectric layer is used techniques thick enough so that its associated capacitance is negligible. Also, it is possible 1) P-N JUNCTION ISOLATION to fabricate both pep and nap transistor In this isolation technique, p+ type within the same silicon substrate. Since this impurities are selectively diffused into the method requires additional fabrication n-type epitaxial layer so as to reach p-type steps, it becomes more expensive. The substrate as shown in Fig. 1.11 (a). This technique is mostly used for fabricating produces islands surrounded by p-type professional grade ICs required for moats. It can be seen that these regions are specialized applications via, aerospace and separated by two back-to-back p-n junction military, where higher cost is justified by diodes. If the p-type substrate material is superior performance. Figure 1.11 (b) held at the most negative potential in the shows such a structure.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission photolithographic process and aluminum is etched away from unwanted places by using etchants like phosphoric acid (H3PO4).

4.3.10 ASSEMBLY PROCESSING & PACKAGING Each of the wafer processed contains several hundred chips, each being a complete circuit. So, these chips must be 4.3.9 METALLIZATION separated and individually packaged. A The purpose of this process is to produce a common method called scribing and thin metal film layer that will serve to make cleaving used for separation makes use of a interconnections of the various diamond tipped tool to cut lines into the components on the chip. Aluminum is surface of the wafer along the rectangular usually used for the metallization of most grid separating the individual chips. Then ICs as it offers several advantages. the wafer is fractured along the scribe lines 1. It is relatively a good conductor. and the individual chips are physically 2. It is easy to deposit aluminum films separated. Each chip is then mounted on a using vacuum deposition. ceramic wafer and attached to a suitable 3. Aluminum makes good mechanical package. There are three different package bonds with silicon. configurations available: 4. Aluminum forms low resistance, non- 1) Metal can package rectifying (i.e., holmic) contact with p- 2) Ceramic flat package type silicon and the heavily doped n- 3) Dual-in-line (ceramic or plastic type) type silicon. package. The film thickness of about 1 mm and conduction width of about 2 to 25 mm 4.4 FABRICATION OF A TYPICAL CIRCUIT are commonly used. The process takes We shall here show the various steps place in a vacuum evaporation chamber utilized in converting the circuit into as shown in Fig. 1.12. The pressure in monolithic IC the chamber is reduced to the range of about 10–6 to 10–7 torr (1 atmosphere STEP-1 WAFER PREPARATION = 760 torr = 760 mm Hg). The material Refer Fig. (a). The starting material called to be evaporated is placed in a the substrate is a p-type silicon wafer resistance heated tungsten coil or prepared as discussed in Sec. 1.5.1. The basket. A very high power density wafers are usually of 10-cm diameter and electron beam is focused at the surface 0.4 mm (~ 400 m) thickness. The of the material to be evaporated. This resistivity is approximately 10 W-cm heats up the material to very high corresponding to concentrationμ of acceptor temperature and it starts vaporizing. 15 3 atom, NA = 1.4 × 10 atoms/cm . These vapors travel in straight line paths. The evaporated molecules hit the STEP-2 EPITAXIAL GROWTH substrate and condense there to form a An n-type epitaxial film (5–25 m) is grown thin film coating. on the p-type substrate as shown in Fig. After the thin film metallization is done, (b). This ultimately becomes μthe collector the film is patterned to produce the region of the transistor, or an element of required interconnections and bonding the diode a nd diffused pad configuration. This is done by capacitor associated with the circuit. So, in

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission general it can be said that all active and epitaxial layer and reach the p-type passive components are fabricated within substrate. The areas under the SiO2 are n- this layer. The resistivity of n-epitaxial type islands that are completely layer is of the order of 0.1 to 0.5 cm. surrounded by p-type moats. As long as the pn junctions between the isolation islands STEP-3 OXIDATION Ω − are held at reverse bias, that is, the p-type Refer Fig. (c). A SiO2 layer of thickness of substrate is held at a negative potential the order of 0.02 to 2 m is grown on theN- with respect to the n-type isolation islands, epitaxial layer. these regions are electrically isolated from μ each other by two back-to-back diodes, providing the desired isolation. The concentration of acceptor atoms (NA 5 × 1020cm–3 ) in the region between isolation islands is generally kept higher≅ than p-type substrate for whichNA = 1.4 × 1015atoms/cm3 . This ensures that the depletion region of the reverse biased diode will not extend into p+ region to the extent of electrically connecting the two isolation islands. There will, however, be a significant amount of barrier or transition capacitance present as a byproduct of the isolation diffusion. The top view of the isolation islands is depicted in Fig. (e). STEP-5 BASE DIFFUSION Refer to Fig. (f). A new layer of SiO2 is grown over the entire wafer and a new pattern of openings is formed using photolithographic technique. Now, p-type impurities, such as boron, are diffused through the openings into the islands of n- type epitaxial silicon. The depth of this diffusion must be controlled so that it does not penetrate through n-layer into the substrate. This diffusion is utilized to form base region, of the transistor, resistor, and the anode of the diode and junction capacitor.

STEP-4 ISOLATION DIFFUSION If in the circuit four components have to be fabricated, so we require four islands which are isolated. For this, SiO2 is removed from five different places using photolithographic technique. Refer Fig. (d). The wafer is next subjected to heavy p-type diffusion for a long time interval so that p- type impurities penetrate the n-type

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission STEP-6 EMITTER DIFFUSION

Refer to Fig. (g) A new layer of SiO2 is again grown over the entire wafer and selectively etched to open a new set of windows and n- type impurity (phosphorus) is diffused through them. This forms transistor emitter and cathode region of diode. Windows (W1, W2 etc.) are also etched into n-region where contact is to be made to the n-type layer. Heavy concentration of phosphorus (n ) is diffused into these regions simultaneous+ ly with the emitter diffusion. The reason for using heavily- doped n-regions can be explained as follows: Aluminum, normally used for making interconnections, is a p-type impurity in silicon, and can produce an unwanted rectifying contact with the lightly-doped n- material. However, heavy concentration of phosphorous ( ~ 2 × 1020cm–3 ) doping causes a high degree of damage to the Si- lattice at the surface, thus effectively making it semi-metallic. This n+ layer thus makes a good ohmic contact with the Al- layer.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission ASSIGNMENT QUESTIONS

Q.1 At room temperature, the current in a) A change in open circuit voltage an intrinsic semiconductor is due to b) A change in short-circuit current a) Holes b) Electrons c) A reduction of resistance c) Ions d) Holes and electrons d) An increase of resistance

Q.2 Match List I with List II and select Q.4 A sample of N-type semiconductor the correct answer using the codes has electron density of 6.25  given below the lists: 1018/cm3 at 300 K. If the intrinsic List I (List of materials) concentration of carriers in this A) Conductor sample is 2.5  1013/cm3, at this B) Semiconductor temperature, the hole density works C) Insulator out to be List II (Energy-band diagram) a) 106/cm3 b) 108/cm3 1) c) 1010/cm3 d) 1012/cm3

Q.5 If the drift velocity of holes under a field gradient of 100 V/m is 5m/s their mobility (in the same SI units) 2) is a) 0.05 b) 0.5 c) 50 d) 500

Q.6 Which of the following statements relate to the Hall effect? 1. A potential difference is 3) developed across a current- carrying metal strip when the strip is placed in a transverse magnetic field. 2. The Hall effect is very weak in metals but is large in Codes: semiconductors. A B C 3. The Hall effect is very weak in a) 1 3 2 semiconductors but is large in b) 3 1 2 metals. c) 1 2 3 4. It is applied in the measurement d) 2 3 1 of the magnetic field intensity. Select the correct answer using the codes given below: Q.3 For a photoconductor with equal a) 1, 2 and 3 b) 2 and 4 electron and hole mobilities and c) 1, 3 and 4 d) 1, 2 and 4 perfect ohmic contacts at the ends, an increase in the intensity of optical illumination results in

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.7 The conductivity of a semiconductor current I is placed in a magnetic crystal due to any current carrier is field B to develop Hall voltage VH in NOT proportional to a direction perpendicular to I and B. a) Mobility of the carrier VH is NOT proportional to b) Effective density of states in the a) B b) I conduction Band c) 1/w d) 1/d c) Electronic charge d) Surface states in the Q.12 In switching diode fabrication, a semiconductor dopant is introduced into silicon which introduces additional trap Q.8 Consider a semiconductor bar levels in the material thereby having square cross-section. Assume reducing the mean life time of that holes drift in the positive x- carriers. This dopant is: direction and a magnetic field is a) Aluminum b) Platinum applied perpendicular to the c) Gold d) Copper direction in which holes drift(+ve z direction) . The sample will show Q.13 Match List I (Equation) with List II a) A negative resistance in positive (Relation between/Description) and y-direction. select the correct answer using the b) A positive voltage in positive y codes given below the lists: direction List I (Equation) c) A negative voltage in positive y- a) Continuity direction b) Einstein’s equation d) A magnetic field in positive y- c) Poisson’s equation direction. d) Diffusion equation List II (Relation between Q.9 A resistance thermometer has a /Description) temperature coefficient of 1) Relates diffusion constant with resistance 10-3 per degree and its mobility. resistance at 0oC is 1.0. At what 2) Relates charge density with temperature is its resistance 1.1 ? electric field a) 10oC b) 100oC 3) Relates flow with rate of change c) 120oC d) -10oC of Concentration in space 4) Rate of change of minority Q.10 Calculate V and I assume diode drop carrier Density with time of 0.7V. Codes: A B C D a) 4 1 3 2 b) 4 1 2 3 c) 1 4 2 3 d) 1 4 3 2

Q.14 Match List I (Material) with List II (Band Gap) and select the correct answer using the codes given below a) 1.4 V & 720μA b) 1.4 V &720mA the lists: c) 0.7 V & 720μA d) 0.7 V & 720mA List I (Material) a) Metal Q.11 A semiconductor specimen of b) Semimetal breadth d, width w and carrying

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission c) Semiconductor c) 10-4 cm d) 104 mho cm-1 d) Insulator Q.19 The intrinsic concentration in a List II (Band Gap) semiconductor at 300 K is 1013 cm-3. 1) 9 eV When it is doped with donor type 2) 0.05 eV impurities, the majority carrier 3) 1.5 eV concentration becomes 1017 cm-3. 4) 0 or less What is the value of its minority Codes: carrier density? A B C D a) 0.999’ 1017 cm-3 b) 1017 cm-3 a) 4 2 3 1 c) 104 cm-3 d) 109 cm-3 b) 4 3 2 1 c) 1 3 2 4 Q.20 Which one of the following is the d) 1 2 3 4 correct relationship between the band gap of a material used in a Q.15 A copper wire is 1 meter long and photo detector and the energy of the has a uniform cross-section of 0.1 incident photon? (the symbols have mm2. The resistance of the wire at usual meanings) room temperature is 0.171 ohm. 23 a) Eg h c / b) h v / l E  g What is the resistivity of the 1 material? c) h v E g d) h v E g 6 7 2 a) 1 . 7 1 1 0 . m b)1 . 7 1 1 0 . m 8 c) 1.7110.m Q.21 Two pure specimen of a d) .1 10719 .m semiconductor material are taken. One is doped with 1018 cm-3number of donors and the other is doped with 1016 cm-3number of acceptors. Q.16 What is the approximate mobility of The minority carrier density in the holes in Germanium at room first specimen is107 cm-3. What is temperature? the minority carrier density in the a) 4500 cm2/V.s b) 2400 cm2/V.s other specimen ? c) 1800 cm2/V.s d) 900 cm2/V.s a) 1016cm-3 b) 1027 cm-3 c) 1018cm-3 d) 109 cm-3 Q.17 The mobility of electrons in a semiconductor is defined as the Q.22 Match List I (Type of Conductor) a) Diffusion velocity per unit with List II (Position of Fermi Level) electric field. and select the correct answer using b) Diffusion velocity per unit the code given below the lists: magnetic field. List I (Type of Conductor) c) Drift velocity per unit magnetic a) n-type semiconductor field b) p-type semiconductor d) Drift velocity per unit electric c) Intrinsic semiconductor field d) Degenerate n-type S.C List II (Position of Fermi Level) Q.18 The free electron density in a 1)Middle of band gap conductor is (1/1.6)  1022 cm-3. The 2)Above conduction band electron mobility is 10 cm2/V s. 3)Near but below conduction band What is the value of its resistivity? 4)Near but above valance band. a) 10-4Wm b) 1.6’ 102Wm Code: A B C D

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission a) 1 2 3 4 and 1 eV = 1.602  10-19 J, the energy b) 3 4 1 2 gap in GaAs is c) 1 4 3 2 a) 0.18eV b) 0.7eV d) 3 2 1 4 c) 1.43eV d) 2.39 eV

Q.23 Diffusion of impurities in a Q.27 Calculate V and I. Assume voltage semiconductor is carried out in a drop across the diode of 0.7 V furnace through which a steady stream of impurity atoms is passed during the entire diffusion process. What would be the type of profile of the impurity atoms inside the semiconductor? a) Linear b) Gaussian c)Complementary error function a) 2.3 V & 2.3mA b) 1 V & 1mA d) Exponential c) 2 V & 2mA d) 3 V & 3mA

Q.24) Which one of the following Q.28 Match List I (Crystal type) with List statements is correct in respect of II (Name of the solid) and select the the use of Direct Gap (DG) and correct answer using the codes Indirect Gap (IG) semiconductors in given below the lists: fabrication of Light Emitting Diode? List I a) Both DG and IG semiconductors a) Ionic are suitable. b) Covalent b) Only DG semiconductor is c) Metallic suitable. d) Van der Wall’s c) DG semiconductor is suitable List II and some IG materials having 1) Solid argon proper dopants are also used. 2) Copper d) Only IG semiconductors are 3) Silicon suitable. 4) Sodium chloride Codes: Q.25 The basic function of buried n+ layer A B C D in an n-p-n transistor fabricated in a) 3 4 2 1 IC is to b) 4 3 1 2 a) Reduce the magnitude of the c) 3 4 1 2 base spreading resistance. d) 4 3 2 1 b) Reduce the collector series resistance Q.29 The carrier mobility in a 2 c) Reduce the base width of the semiconductor is 0.4m /Vs. Its transistor diffusion constant at 300 K will be 2 d) Increase the gain of the (in m /s) transistor. a) 0.43 b) 0.16 c) 0.04 d) 0.01 Q.26 The wavelength of light emitted by a GaAs laser is 8670  10-10 m. Given Q.30 Silicon diode is less suited for low voltage rectifier operation because Plank’s constant = 6.626  10-34Js, velocity of light = 2.998  108 ms-1

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission a) It can withstand high d) Independent of bias voltage and temperatures temperature. b) Its reverse saturation current is low Q.36 A combination of two diodes c) Its cut-in voltage is high connected in parallel when d) Its breakdown voltage is high compared to a single diode can withstand Q.31 Gold is often diffused into silicon PN a) Twice the value of peak inverse junction devices to voltage. a) Increase the recombination rate b) Twice the value of maximum b) Reduce the recombination rate forward current c) Makes silicon a direct gap c) A larger leakage current semiconductor d) Twice the value of cut-in voltage. d) Make silicon semi-metal Q.37 The light emitting diode (LED) emits Q.32 Silicon is not suitable for fabrication light of a particular color because of light emitting diodes because it is a) It is fabricated from a a) An indirect band gap fluorescent material. semiconductor b) Transition between energy b) A direct band gap semiconductor levels of the carriers takes place c) A wide band gap semiconductor while crossing the p-n junction d) A narrow band gap c) Heat generated in the diode is semiconductor converted into light. d) The band gap of the semi- Q.33 The change in barrier potential of a conductor material used in the silicon p-n junction with fabrication of the diode is equal hc temperature is to the energy of the light a) 0.025 Volts per degree C λ b) 0.250 Volts per degree C photon. c) 0.030 Volts per degree C Q.38 Depletion capacitance in a diode d) 0.014 Volts per degree C depends on: 1. Applied Junction voltage. Q.34 The diffusion capacitance of a p-n 2. Junction built-in potential. junction diode 3. Current through junction a) Increases exponentially with 4. Doping profile across the junction forward bias voltage. Select the correct answer using the b) Decreases exponentially with codes given below: forward bias voltage a) 1 and 2 b) 1 and 3 c) Decreases linearly with forward c) 1, 2 and 4 d) 2, 3 and 4 bias voltage. d) Increase linearly with forward Q.39 The depletion region in a bias voltage. semiconductor p-n junction diode has Q.35 The reverse current of a silicon a) Electrons and holes diode is : b) Positive and negative ions on a) Highly bias voltage sensitive. either side b) Highly temperature sensitive c) Neither electrons nor ions c) Both bias voltage and d) No holes temperature sensitive.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.40 When a junction diode is used in diffused junctions would be switching applications, the forward respectively. recovery time is: 1 1 1 1 1 1 a) b) a) Of the order of the reverse 2 3 2 . 5 3 2 5.2 recovery time. 1 1 1 1 1 1 c) d) b) Negligible in comparison to the 2 5.23 3 5.22 reverse recovery time. c) Greater than the reverse Q.44 A p-n junction diode’s dynamic recovery time. conductance is directly proportional d) Equal to the mean carrier life to time  for the excess minority a) the applied voltage carriers. b) the temperature c) its current Q.41 Match List I (Diode) with List II d) the thermal voltage (Application) and select the correct answer using the codes given below Q.45 When a junction transistor is the lists: operated under saturated List I (Diode) conditions a) Varactor diode a) Both the CB and EB junctions are b) Tunnel diode forward biased. c) Photodiode b) The CB junction is forward d) Zener diode biased but the EB junction is List II (Application) reverse biased. 1) To charge auxiliary storage c) The CB junction is reverse biased batteries but the EB junction is forward 2) Reference voltage biased. 3) High frequency tuning circuits d) Both the CB junction are reverse 4) High frequency switching circuit. biased. Codes: A B C D Q.46) The collector to emitter cut-off a) 2 1 4 3 current (ICEO) of a transistor is b) 3 1 4 2 related to collector to base cut-off c) 3 4 1 2 current (ICBO) as ( is the CB current d) 2 4 1 3 gain of the transistor) a) II b) II Q.42 The junction capacitance of a p-n CEO CBO CEOCBO junction depends on ICBO ICBO c) ICEO  d) IECO  a) Doping concentration only 1 1 b) Applied voltage only c) Both doping concentration and Q.47 A bipolar junction transistor has a applied voltage. common base forward short circuit d) Barrier potential only current gain of 0.99. Its common emitter forward short circuit Q.43 In a p-n junction, the space charge current gain will be capacitance is proportional to 푉−푛 a) 50 b) 99 where V is the applied bias voltage c) 100 d) 200 and ‘n’ is a constant. The value of ‘n’ for step, linearly graded and Q.48 A bipolar junction transistor is in saturation region. Given VCC = 10V,

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission RC = 1k, hFE = 100 and VCE sat = a) 55mA b) 160 mA 0.3 V. What is the collector current c) 180 mA d) 270 mA in saturation? Q.53 In a junction transistor, the collector a) 10 mA b) 9.7 mA cut-off current ‘ICBO’ reduce c) 0 mA d) 1 mA considerably by doping the a) Emitter with high level of Q.49 Match List I (Regions of bipolar impurity transistor in a monolithic IC) with b) Emitter with low level of List II (Physical properties) and impurity select the correct answer using the c) Collector with high level of codes given below the lists: impurity List I d) Collector with low level of A. Emitter impurity B. Base C. Collector Q.54 Thermal runaway will take place if D. Substrate the quiescent point is such that List II 1 a) VV b) VV 1. Moderate resistivity CECC 2 C E C C 2. Very high resistivity 1 3. Large size c) VCECC 2 V d) VVCECC 4. Very high conductivity 2 Codes: Q.55 The drain source output V-I A B C D characteristics of an n-channel a) 1 4 2 3 depletion FET has b) 4 1 2 3 a) IDS = 0 at VGS = 0 c) 4 1 3 2 b) IDS = positive maximum at VGS = 0 d) 1 4 3 2 c) IDS = negative maximum at VGS = 0 d) IDS = independent of VGS Q.50 If α = 0.995, IE = 10mA and Ico= 0.5µA, then ICEO will be Q.56 The output V-I characteristics of an a) 100A b) 25A enhancement type MOSFET has c) 10.1 mA d) 10.5mA a) Only an ohmic region b) Only a saturation region Q.51 In a transistor amplifier, the reverse c) An ohmic region at low voltage saturation current ICO value followed by a saturation a) Doubles for every 10oC rise in region at higher voltage. temperature. d) An ohmic region at large voltage b) Doubles for every 1oC rise in values preceded by a saturation temperature. region at lower voltages. c) Increase linearly with temperature Q.57 For an n-channel JFET, having drain- d) Doubles for every 5oC rise in source voltage constant if the gate temperature. source voltage is increased (more negative) pinch -off would occur for Q.52 A transistor emitter base voltage a) High values of drain current (VEB) of 20 mV has a collector b) Saturation value of drain current current (IC) of 5 mA. For VEB of 30 c) Zero drain current mV, IC is 30 mA. If VEB is 40 mV, then d) Gate current equal to the drain the IC will be current

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.58 In modern MOSFETs, the material c) the drain current increases used for the gate is d) the mobility increases. a) High purity silicon b) High purity silica Q.63 The diode has threshold voltage of c) Heavily doped polycrystalline 0.5 V and forward resistance of 1Ω. silicon The current I and voltage drop 푉푑 d) Epitaxial grown silicon across diode are.

Q.59 A FET a better chopper than a BJT because it has a) Lower off-set voltage b) Higher series ON resistance a) 5mA & 0.5V c) Lower input current b) 5mA & 5V d) Higher input impedance c) 4.469mA & 0.5 V d) 4.496mA & 5V Q.60 The output current versus input voltage transfer characteristic of an Q.64 The voltage gain of a given common n-channel JFET is such that there is source JEFT amplifier depends on its a) Zero current flow at zero input a) Input impedance voltage bias b) Amplification factor b) Current flow only when a c) Dynamic drain resistance positive input threshold voltage d) Drain load resistance is crossed. c) Current flow only when a Q.65 The threshold voltage of an n- negative input cut-off voltage channel enhancement mode bias is crossed. MOSFET is 0.5V. When the device is d) No cut-off input voltage biased at a gate voltage of 3V. Pinch off would occur at a drain voltage of Q.61 In an MOS transistor, the gate a) 1.5V b) 2.5V source input impedance is c) 3.5V d) 4.5V 1. Lower than the input impedance of a BJT Q.66 Consider the following devices: 2. Higher than the input impedance 1. BJT in CB mode. of a BJT 2. BJT in CE mode 3. Lower than the input impedance 3. JEFT` of a JFET 4. MOSFET 4. Higher than the input impedance The correct sequence of these of a JFET devices in increasing order of their Select the correct answer using the input impedances is: codes given below: a) 1,2,3,4 b) 2,1,3,4 Codes: c) 2,1,4,3 d) 1,3,2,4 a) 1 alone b) 2 and 3 c) 4 alone d) 2 and 4 Q.67 In a biased JFET, the shape of the channel is as shown in the given Q.62 Thermal runaway is not possible in figure because FET because as the temperature of FET increases a) the mobility decreases b) thetransconductance increases

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission is developed. If the heated end is a) It is the property of the material positive, the semiconductor is used a) p-type b) n-type b) The drain end is more reverse c) Intrinsic d)Highly degenerate biased than source end c) The drain end is more forward Q.73 Why does the mobility of electrons biased than source end in a semiconductor decrease with d) The impurity profile varies with increasing donor density? the distance from source. a) Doping increases the effective mass of electrons Q.68 What is the correct sequence of the b) Doping decreases the relaxation following step in the fabrication of a time of electrons monolithic, bipolar junction c) Electrons are trapped by the transistor? donors 1. Emitter diffusion d) More holes are generated so that 2. Base diffusion the effective mobility decreases 3. Buried layer formation 4. Epi-layer formation Q.74 An intrinsic semiconductor with Select the correct answer using the energy gap 1 eV has a carrier codes given below: concentration N at temperature 200 a) 3, 4, 1, 2 b) 4, 3, 1, 2 K. Another intrinsic semiconductor c) 3, 4, 2, 1 d) 4, 3, 2, 1 has the same value of carrier concentration N at temperature 600 Q.69 In an integrated circuit, the SiO2 K. What is the energy gap value for layer provides the second semiconductor? a) Electrical connection to external a) (1/3) eV b) (3/2) eV circuit c) 3 eV d) 9 eV b) Physical length c) Isolation d) Conducting path Q.75 An intrinsic semiconductor is doped lightly with P – type impurity. It is Q.70 As the Fermi energy of silver is found that the conductivity actually 8.810-19 joule, the velocity of the decreases till a certain doping level fastest electron in silver at 0K is reached. Why does the occur? (Given : Rest mass of electron = a) The mobility of holes decreases -31 b) The mobility of both electrons 9.110kg. )is and holes decreases 5 7 a) 3.33 10 m/s b) 4.40 10 m/s c) The hole density actually reduces c) 1.39106 / sm d) 3108 / sm d) Effect of reduction in electrons due to increase in holes Q.71 Electron mobility and life-time in a compensates more than the effect of semiconductor at room temperature increase in holes on conductivity are respectively 0.36m2/(Vs) and 340 s. The diffusion length is Q.76 Consider the following statements a) 3.13 mm b) 1.77 mm with regard to semiconductors: c) 3.55 mm d) 3.13 cm 1. In n type material free electron concentration is nearly equal to Q.72 When a semiconductor bar is heated density of donor atoms. at one end, a voltage across the bar

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 2. 1 part in 108 donor type Where EFis Fermi energy and ED is impurity added to Ge improves donor level energy. its conductivity at 30oC by a Which of these statements is/are factor 12. correct 3. Phosphorus is an example of n a) 1 and 2 b) 2 and 3 type impurity. c) 4 only d) 1, 2 and 3 Which of these statements are correct? Q.81 Consider the following statements: a) 1, 2 and 3 b) 1 and 3 onl A semiconductor to be used in c) 2 and 3 only d) 1 and 2 only optoelectronic devices should have 1. Direct energy band gap. Q.77 In which one of the following ways 2. Indirect energy band gap. can the Hall voltage across an 3. Any value of forbidden energy impurity semiconductor crystal be band gap. increased? 4. Right value of band gap a) By increasing the thickness of corresponding to light the crystal wavelength. b) By increasing the concentration Which of the statement is /are of impurity atoms in the crystal correct? c) By increasing the width of the a) 1 only b) 1 and 4 crystal c) 2 and 3 d) 2 and 4 d) By increasing the current flowing through the crystal Q.82 Which one of the following is the correct statement? Q.78 The Fermi function for an electron is The type of majority charge carriers f(E),where E is energy. Then, the in a semiconductor can be found by Fermi function for a hole is a) Hall effect a) f(E) b) 1 –f(E) b) Piezoelectric effect c) 1/f(E) d) 1 + f(E) c) Photoelectric effect d) Meissner effect

Q.79 The initial temperature of a Q.83 Assuming the Fermi level EF to be specimen of silicon is 푇1 = 300퐾. By independent of temperature, EF may what factor does the intrinsic be defined as the level with an concentration 푛푖 increase if the electron occupancy probability of temperature increase by 10 ℃ a) 0% b) 50% (18℉)? Assume the band gap at c) 75% d) 100% both temperatures is 퐸퐺 = 1.11푒푉. a) 3 b) 1/3 Q.84 Which of the following has the c) 1/2 d) 2 greatest mobility? a) Positive ion b) Negative ion c) Electron d) Hole Q.80 Consider the following statements Q.85 An intrinsic semiconductor at a for an n-type semiconductor: temperature of absolute zero 1. EF lies below ED at a room behaves like an insulator because of temperature (T) a) Non-availability of free electrons 2. EF lies above ED as T  0 b) Non-recombination of electrons 3. EF = ED at some intermediate with holes temperature. c) Low drift velocity of free electrons 4. EF is invariant with temperature.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission d) Low (almost zero) electron energy Q.90 A MOs capacitor has tox = 5nm.If the maximum depletion layer width Q.86 With an increase in temperature, the is 61nm, the minimum capacitance Fermi level in an intrinsic is. (3.9)(12) semiconductor SiO0Si02 a) Moves closer to the conduction mF a) 1.74 b) 2 band edge m2 b) Moves closer to the valence band edge c) 1.39 d) 6.9 c) Moves into the conduction ban d) Remains at the centre of the Q.91 In a forward biased photo diode, an forbidden gap increase in incident light intensity causes the diode current to Q.87 On which of the following factors a) Increase does the electrical conductivity of a b) Remain constant semiconductor depend? c) Decrease 1. Carrier concentration d) Remain constant while the 2. Carrier mobility voltage drop across the diode 3. Sign of the carrier increases Select the correct answer using the codes given below: Q.92 The junction capacitance of a a) 1 and 2 b) 1 and 3 linearly graded junction varies with c) 2 and 3 d) 1, 2 and 3 the applied reverse bias Vr as 1  1 2 Q.88 An LED made using GaAs emits a) Vr b) Vr 1 1 radiation in:  3 2 a) Visible region c) Vr d) Vr b) Ultraviolet region c) Infra red region Q.93 A PN junction in series with a 100 d) Microwave frequency region. ohm resistor is forward biased so that a current of 100mA flows. If Q.89 Assertion (A): An unbiased p-n voltage across the combination is junction develops a built-in instantaneously reversed to 10V at potential at the junction with the n- time t= 0, the reverse current that side positive and the p-side flows through the junction at t = 0 is negative. approximately given by Reason (R): The p-n junction a) 0 mA b) 200 mA behaves as a battery and supplies c) 50 mA d) 100 mA current to a resistance connected across its terminals. Q.94 The development of barrier a) Both A and R are individually potential in the depletion zone of a true and R is the correct PN junction is consequent to explanation of A a) Diffusion of majority carriers b) Both A and R are individually across junction true but R is not the correct b) Drift of minority carriers across explanation of A junction c) A is true but R is false c) Generation of minority carriers d) A is false but R is true due to thermal energy

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission d) Initial flow of conduction current Q.98 The conductivity of the intrinsic germanium at 300oK when, ni at Q.95 The current flowing in a certain PN 300oK = 2.5 X 1013/cm and µn and µp junction at room temperature 300 K in germanium are 3800 and 1800 is 2 10−7 A when a large reverse cm2/Vs respectively. bias voltage is applied. The current a) 0.224 S/cm b) 0.0224 S/cm flowing when a forward bias of 0.1 V c) 2.24 S/cm d) 0.00224 S/cm is applied will be 19 Q.99 For the circuit shown in the above 7 1.6  10  0.1 a) 2 10 exp figure, by assuming =200 and VBE 1.38 1023 300  =0.7 V, the best approximation for 19 7 1.6100.1 the collector current Ic in the active b) 210 23 1.3810300 region is 23 7 1.3810300 c) 210exp 19 1.6100.1 1.381030023 d) 210 7 1.6100.119  a) 1 mA b) 2.4 mA c) 3 mA d) 9.6 mA Q.96 Which of the following main properties of a bipolar junction Q.100 Early effect in BJT refers to transistor, make it necessary for the a) Avalanche breakdown transistor to have bias stabilization? b) Thermal runway 1. Variation of VBE with temperature c) Base narrowing 2. Variation of hFE with temperature d) Zener breakdown 3. Variation of ICO with temperature 4. Variation of hFE with transistor Q.101 Almost all resistors are made in a replacement monolithic integrated circuit 5. Variation VBE with transistor a) During the emitter diffusion replacement b) While growing the epitaxial layer 6. Variation of ICO with transistor c) During the base diffusion replacement. d) During the collector diffusion Select the correct answer using the codes given below: Q.102 The main disadvantage of JFET is a) 1, 2 and 6 b) 1, 3 and 4 a) Low gain bandwidth product c) 2, 3 and 5 d) 3, 4, 5 and 6 b) High noise level c) High cost Q.97 The p-type epitaxial layer grown d) Low gain over an n-type substrate for fabricating a bipolar transistor will Q.103 The current amplification factor β function as can never be a) The collector of a p-n-p transistor a) = 100 b) > 1 b) The base of an n-p-n transistor c) < 1 d) none of these c) The emitter of a p-n-p transisto d) The collector contact for a p-n-p Q.104 In a common base transistor circuit, transistor the current gain is 0.98. On changing emitter current by 5.00 mA, the change in collector current is:

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission a) 0.196 mA b) 2.45 mA accumulation condition is shown by c) 4.90 mA d) 5.10 mA the point

Q.105 In a P-N junction having depletion layer of thickness 10-6 m, the potential across it is 0.1V. The electric field is a) 107 V/m b) 10-6 V/m c) 105 V/m d) 10-5 V/m a) p b) q c) s d) t Q.106 The cut-in voltage VT and the thermal voltage VT for the diode D in fig. are 0.498 V and 2 mV, Q.110 The diffusion constant and mobility respectively. If the value of resistor for electrons in a semiconductor R is 20Ω, the current flowing material at a given temperature are 2 2 through the diode is 20 cm /s and 1600 cm /V-s, respectively. The thermal voltage VT for a diode made of this material at the same temperature is a) 125 mV b) 32 mV c) 12.5 mV d) 3.2 mV a) 275mA b) 250mA c) 200mA d) less than 200mA Q.111 In a P – well fabrication process, the Q.107 TheI −VGS characteristics shown in D substrate is fig is of a) N-type semiconductor and is used to build P-channel MOSFET b) P-type semiconductor and is used to build P-channel MOSFET c) N-type semiconductor and is used to build N-channel MOSFET d) P-type semiconductor and is a) an enhancement type P MOSFET used to build N-channel NOSFET b) an enhancement type N MOSFET c) a depletion type PMOSFET Q.112 At a given temperature, a d) a depletion type NMOSFET semiconductor with intrinsic carrier concentration ni = 1016/m3 is doped Q.108 A magnetic field B of 2 T is normal with a donor dopant of to a copper strip 0.5 mm thick concentration ND = 1026/m3. carrying an electron current of 40 A. Temperature remaining the same, If the electron density is 10.0 × 1028 the hole concentration in the doped per cubic metre, then voltage across semiconductor is the strip in micro volt is a) 1026/m3 b) 1016/m3 a) 40 b) 30 c) 1014/m3 d) 106/m3 c) 20 d) 10 Q.113 In a MOS capacitor with n-type Q.109 The high-frequency C-VGS silicon substrate, the Fermi

characteristic of a MOSFET is shown potential  F = - 0.41V and the flat – in fig. In the curve, the

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission band voltage VFB = 0V. The value of (i) mobility of majority and the threshold voltage VT is minority carriers to be the same a) -0.82 V b) -0.41 V KT (ii)  2 6m V at room temperature c) 0.41 V d) 0.82 V q

Q.114 In a semiconductor it is observe that Q.118 The donor concentration in n-type three quarter of the current is silicon is 1 atom per 108 atoms. Find carried by electrons and one the temperature at which the Fermi quarter by holes ,determine the level coincides withthe edge of the ratio of electrons to holes in the conduction band assuming that semiconductor . effective mass is equal to the true mass. Q.115 Calculate the diffusion current in a piece of germanium having 22 Q.119 An n-type semiconductor has its concentration gradient of 1.5 × 10 Fermi level 0.25 eV below the 3 2 electrons /푚 and 퐷푛 = 0.0012푚 /푠 conduction band edge. Estimate its dopant, majority, and minority Q.116 A sample of germanium is doped carrier concentrations in 20 3 with 10 donor atoms/푚 and 5 × equilibrium at room temperature. 21 3 16 3 10 acceptor atoms/푚 . Find the Assumeni = 1.6 × 10 /m . total conduction current density if

the resistivity of intrinsic Q.120 Calculate the minimum value of 푉퐷푆 germanium at 300 K is 0.6 Ωm with required for an nMOSFET to operate an applied field of 0.02 V/m. in the pinch-off when VGS = 1V with Determine the ratio of electrons and VT = −2Vand IDSS = 10 mA. holes if the mobility of electrons is two times the mobility of holes at Q.121 Two IGFET are connected in parallel 300K. to form composite IGFET as shown in Fig Obtain the gm of the Q.117 In a semiconductor at room composite IGFET if the drain current temperature (300K) the intrinsic of each IGFET is described as carrier concentration and resistivity V 2 16 3 3 3 GS are 1.5 × 10 /푚 and 2 × 10 Ω푚 ID  10  10 1  5 respectively. It is converted to a  extrinsic semiconductor with doping concentration of 1020/푚3 . For the extrinsic semiconductor calculate a) Minority carrier connect ration Q.122 Obtain the minimum value of VDS of b) Resistivity an n-channel JFET operating in the c) Shift in the Fermi level due to pinch –off region with V = doping po −4V, V = −2 V and I = 10mA . d) Minority carrier concentration GS DSS Calculate the corresponding value I when its temperature is D increased to a value at which the Q.123 For a JFET obtain change in the intrinsic concentration 푛 푖 drain current for V = 3V and doubles. DS corresponding change in the Assume VGSfrom−2V to − 1V.

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission leakage current is I 15nA at Q.124 Calculate the drain current of an CBO 25°C? nMOS transistor for VGS = 0 V, 1 V and 2 V with the device parameters Q.132 Accidentally the emitter and collector leads of an npn transistor as W5μ m ,L 1μ m , VDS 0 . 1 V , 2 have been connected in the inverse V1V,thnoxμC25μA/ V mode. The resulting emitter and base currents from this Q.125 What would be the output configuration are 5 mA and 1 mA. resistance at collector current of 1 What would be the value of a R and mA of a BJT having early voltage of β ? 200V? R

Q.126 Calculate the mobility of electron in an N-MOS transistor with the device parameters as W 1,V4VV1.99V, L GSth o (V4VDSoxε3.97ε,I144μA,t400A)oD ox

Q.127 An enhancement –type transistor W with C μ0.2μA,V2V and oxn L th λ = 0.02/V operators VGS = 4V Obtain drain current for (VDS = 2V and 5V and the drain resistance at this value of VGS.

Q.128 Calculate contact potential of a Ge diode having donor impurity 22 3 concentratio ND  10 / m acceptor 243 impurity concentration N10/A  m and intrinsic concentration 2.5 × 1019/m3

Q.129 If IB and IC of any BJT are 1mA and 100 mA respectively, determine its current amplification ratio in CB and CE configurations.

Q.130 If the quiescent collector current of an n-p-n transistor for the base

emitter voltage V0.7BE  is I1mAC 

what would be the new value of VBE

at I0.1mAC  ?

Q.131 What would be the value of leakage current of a transistor at 75°퐶 ,if the

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission ANSWER KEY:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 (d) (a) (c) (b) (a) (d) (b) (c) (b) (c) (d) (c) (b) (a) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (c) (c) (d) (d) (d) (c) (d) (b) (c) (b) (b) (c) (a) (d) 29 30 31 32 33 34 35 36 37 38 39 40 41 42 (d) (c) (a) (a) (a) (a) (b) (c) (d) (c) (b) (b) (c) (c) 43 44 45 46 47 48 49 50 51 52 53 54 55 56 (a) (C) (a) (c) (b) (b) (c) (a) (a) (c) (a) (d) (b) (c) 57 58 59 60 61 62 63 64 65 66 67 68 69 70 (c) (c) (a) (d) (d) (a) (c) (c) (b) (a) (b) (c) (c) (c) 71 72 73 74 75 76 77 78 79 80 81 82 83 84 (b) (b) (b) (a) (d) (a) (d) (b) (d) (d) (a) (a) (b) (c) 85 86 87 88 89 90 91 92 93 94 95 96 97 98 (a) (d) (a) (c) (c) (c) (b) (c) (d) (a) (b) (b) (a) (b) 99 100 101 102 103 104 105 106 107 108 109 110 111 112 (a) (c) (c) (a) (c) (c) (c) (b) (a) (d) (d) (c) (c) (d) 113 114 115 116 117 118 119 120 121 122 123 124 125 126 (d) * * * * * * * * * * * * * 127 128 129 130 131 132 * * * * * *

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission EXPLANATIONS

Q.1 (d) Q.7 (b) In intrinsic semiconductor n=p & σ = nqμn + pqμp both take part in conduction. n(electron concentration) depends on Nc Q.2 (a) (density of states in conduction 1) For conductors and conduction band) band and valence band overlaps at room temperature. Q.8 (c) 2) For insulators the forbidden gap is larger than for semiconductors.

Q.3 (c) With increase in intensity more number of electrons and holes are generated and conductivity increases i.e. resistance decreases. Holes will experience a force in downward direction, a positive Q.4 (b) voltage in negative y direction and According to mass action law negative voltage in positive y n2 direction. p  i n Q.9 (b) 13 2  2.510 ℃  R(T)R(0)(1αT) 6.2510 18 1.1 = 1(1 + αT) 10/8 cm3 0.10.1 αT0.1T 100℃ α10 3 Q.5 (a) V E=100 Q.10 (c) m m V5 d s V 5m2 μ d 0.05 E100Vsec 

Q.6 (d) V=0.7 V 1 R  5 0.7 0.7 H nq I=  720μA 5K For metals n(electron concentration ) is Q.11 (d) very large as compared to BIRH semiconductor. VH  w Therefore, RH is small

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission ∴ the hall voltage is not Q.21 (d) proportional to d. 101018 16 107 N, N,p  DAcmcmcm3 3 3 Q.12 (c) 2 2 p n / N p n / N Gold is used as a recombination iD iA p N p N agent. AD n  n NDA N Q.13 (b) 107 10 18 10 9  1016 cm3 Q.14 (a) Q.22 (b) Q.15 (c) l=1m Q.23 (c) A=0.1× (10−3)2 = 10−7m2 Complementary error function R=0.171Ω ρ l R A  Q.24 (b) R= ρ Al Only DG semiconductor is suitable 7 because in direct band gap 0.17110 8  1.7110 Ωm semiconductors, during 1 recombination energy is released in the form of light. Q.16 (c) 1800 cm2/V.s Q.25 (b)

Q.17 (d) V μ  d E

Q.18 (d) 11 ρ  AnN+ buried layer is used in the σ nqμn collector to reduce the collector 1  series resistance. 1 10101.61022 19 Q.26 (c) 1.6 1 1.24 10000mhocm EG  λ(μm) Q.19 (d) 1.24 4 1.43ev 101013 17 867010 μm n,n i cmcm33 Q.27 (a) 13 2 n 10  109 p i  n 1017 cm3

Q.20 (c) A photon having hv ≥ Eg will only be able to break covalent bonds & generate free charge carriers

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission .A C  D and D will not conduct. T 2 3 211 V=3-0.7=2.3V VV0RB 2 . 3 qNNAD And I=  2 . 3mA 1K Q.39 (b) Q.28 (d) Positive and negative ions on either side Q.29 (d) Q.40 (b) D  μVT 3  0 . 4 2 5 1 0 Q.41 (c) =0.01 Zener diode has constant voltage across it when used in Reserve bias. Q.30 (c) Tunnel diode is used in switching Its cut-in voltage is high circuit. Varactor diode is used in tunning Q.31 (a) circuit. Increase the recombination rate Q.42 (c) Q.32 (a) .A Cj  Q.33 (a) 211 VV0RB dV qNN d 2.5mV0.0025 AD dT Q.43 (a) Q.34 (a) Vd Q.44 (c) nVT τIe 0 As C  If D g  nVT nVT ∴ CD increases exponentially with Vd Q.45 (a) Both the CB and EB junctions are Q.35 (b) forward biased. Highly temperature sensitive because it is minority carrier Q.46 (c) current & minority carries I1CEO  βICBO concentration is sensitive to temperature. 1  ICBO 1α Q.36 (c) A larger leakage current Q.47 (b) α 0.99 α 0.99, β    99 Q.37 (d) 1α 0.01 hc E  G λ Q.48 (b) VV I  CC CE Q.38 (c) c RC

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission 100.3 Q.57 (c) 9.7mA 1000 Zero drain current

Q.49 (c) Q.58 (c) Polycrystalline silicon is used to Q.50 (a) reduce VT 10.5µA II CEO 1α10.995CO Q.59 (a) Lower off-set voltage I 1CEO 0 0 µ A Q.60 (d) Q.51 (a) No cut-off input voltage Double for every 10oC rise in temperature. Q.61 (d) In MOSFET, there is isolation (SiO2) Q.52 (c) in between gate and source. VBE I I e VT cco Q.62 (a) 2 0m V V IDis due to majority charge carries 5mA  Ie T co and their mobility decreases with 3 0m V temperature VT 30mA  Ieco 20mV Q.63 (c ) 5mA IeVT  co 30mA 30mV VT Ieco 2030 1  e VT 6 V5.6mVa T 50.5 I0 4.496mA Now, for VEB  40mV 1K1 Ω 40mV V0.54.496mA1d  Ω I I e VT c co ≈ 0.5V 20 5mA IeVT  co  0 . 0 2 8 a Q.64 (c) I 40 c VT Dynamic drain resistance Ieco Ic = 177mA ≈ 180mA Q.65 (b) Pinch off would occur at Q.53 (a) VVVDSsat GS T Q.54 (d) 30.52.5V 1 VVCE CC Q.66 (a) 2 BJT in CB mode ⟹ R ≈ 10Ω Q.55 (b) i BJT in CE mode ⟹ Ri = few KΩ IDS = positive maximum at VGS = 0 6 8 JFET⟹ Ri = 10 to 10 Ω MOSFET⟹ R = 1010 to 1015 Q.56 (c) i

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.67 (b) decrease in electrons concentration The drain end is more reverse conductivity decrease upto certain biased than source end doping level.

Q.68 (c) Q.76 (a)

Q.77 (d) B I R V  H so VI H w H

Q.78 (b) Collector is a part of epitaxial layer 1 –f(E) & base & emitter are diffused into epi layer. Q.79 (d) Let, T1 =300K be the initial Q.69 (c) temperature andT2=310K the initial Isolation temperature At, 300K, Q.70 (c) T 300 kT 1 0.0259V 1 2 1 1160011600 E mE  V 2 T 310 kT 2 0.0267V 2EFm 2 V= 13910 6 1160011600 msec The factor by which ni increases is calculate from eq 3 Q.71 (b) 2 EG nATexpi0  L = √Dτ 2kT D = μVT 3 E 2 G L μVτ Texp2  T n 2k i2  T2 0.360.025634010 6 n 3 V i1 Texp2 G L=1.77mm  1  2kT1 3 Q.72) (b) 3101.11112    exp  When n-type semiconductor heated 30020.02670.0259 at one end, the electrons gain more  2 . 0 energy and move to the other end of the material & the heated end Q.80 (d) becomes positive. Q.81 (a) Q.73 (b) Doping decreases the relaxation Q.82 (a) time of electrons Q.83 (b) Q.74 (a) Q.84 (c) Q.75 (d) Positive and negative ions do not Mobility of holes is less than move. mobility of electrons, due to

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.85 (a) Vd Non-availability of free electrons I If0 e x p  VT Q.86 (d) KT VT  Remains at the centre of the q forbidden gap qVd I If0 e x p  KT Q.87 (a) Both positive and negative charge Q.96 (b) carries take part in conduction and total conductivity is addition of Q.97 (a) conductivity due to both. Q.98 (b) Q.88 (c) 13 n2.510,in μ3800, μ 1n 8 0 0

Q.89 (c) σ n q μinn μ   =0.0224 S/cm Q.90 (c)  SiO2 mF Q.99 (a) C6.9ox  2 tmox As b is large, neglect IB and IC ≈ IE 12 -1.2V+0.7V+I ×0.45kΩ=0 3.98.8510 C  1.20.7 5nm I  C 0.45kΩ Si CDmin  = 1mA xdmax 128.8510mF12 Q.100 (c) 1.74 61nmm 2 1mF Q.101 (c) C 1.39 min 11 m2 All the resistors are made due to  base diffusion because base has high CC oxDmin resistivity

Q.91 (b) Q.102 (a)

Q.92 (c) Q.103 (c)

Q.93 (d) Q.104 (c) Upto saturation time the diode will α = 0.98 conduct heavily and the current dIC through diode will be approximately α  dICE  αdI dI 100 mA but in reserve direction. E =0.98× 5 Q.94 (a) = 4.9mA

Q.95 (b) Q.105 (c) V 0.1 The reserve current when large E  reserve voltage is applied is called W 106 reserve saturation current 7 I0  2 10

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission Q.106 (b) I nnnn q v A and Ipnp p q v A InqvAnv n3v nnnnn np IpqvApvpvpnpnpnp 3n (3/4)I  n 3 p(1/4)In 5 . 5 0 . 4 9 8 I  =250mA nn = pn 20 The ratio of electros to holes present in the semiconductor is equal. Q.107 (a) Q.115 (2.28) Q.108 (d)  B=2 Tesla, w=0.5mm, I=40A dn 2 JqDamp/m n  11 dx RH  19 28 qn 1.6 10  10  10 1.6100.00121.51019 22 BIR 2 V10H μV  2 . 2 8 A/ m H w Q.116 (0.05) Q.109 (d) σiinp n q ( μ μ ) Q.110 (c) 2.5101.610(219 19 μμ ) D20 pp V12.5mVT 11 μ1600 3μ  p 0.602.51.62.4 1 Q.111 (c) μ0.1389m/ V 2 In p-well fabrication, a p-well pS7.2 diffused in n-substrate. The p-well is 2 μ20.1389m/nS V then used as substrate for n-channel 2 MOSFET  0.2778m/ V S Also Q.112 (d) 1920 pnNN51010AD 16 2 n2 10 19 19 3 p= i 10/6 m3  10  5  10   5  10 / m N10 26 D 2 19 2 38 npn2.5106.2510i  = 0 Q.113 (d) 38 6.25 10 19 VT = VFB − 2∅F p   5  10 = 0 − 2 × −0.41 p =0.82V Or, p52  10  p19 6.25 100A38 Q.114 () p 1.035 1019 / m 3 Total current = I = In + Ip npNN 3I I  AD As per question I  and I  n 4 p 4 1.035  1019   5  1019  v 3v 19 3 np 6.035 10 / m

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission JJJn μpμqE 16 2 npnp    2 1 . 5 1 0  6.0350.27781.0350.138910  19 1020 12 3 1  . 6 1 0 0 .19 0 2 9 1 0 a t o m s/ m 1.6770.1440.032 Q.118 (0.226)  0 . 0 5 8 2 A/ m 2 510 28 N  510atom20 / m 3 D 110 8 Q.117 () The Fermi level (a) minority × majority carrier 2 EFCDC E forN N concentrations = ni Hence, minority carrier It is known that 213/23 concentration N4.8210T/mC  2 20 21 3/2 3 1  . 5 1 0 16 5 10  4.82  10 T / m  20 1020 3/2 510 T 21 0.1037 12 3 4.8210 2.2510atom/m T0.10730.1073 2/3 0.666 σiinp n q μ μ   16 19  0 . 2 2 6 K 1.5101.6102  μn 3 2.4102 μn Q.119 ()

EECF  σi KT μ  nN e n 2.4210 3 n C 1 2πmKT 3/2 2  330.104m/ V S N2C  2 4.810210 h (b) Conductivity of extrinsic ECF E 0.25eV, semiconductor = σ = nqμ n n N(300K)2.910/ m 253 Since doping concentration C 0.25  >>minority concentration only 25 8.62 103005 n2.910en  doping concentration will be used. 0.25  Hence 2.910e 25 8.62 103005 20 19 25 σ101.6100.1042n  2.910 2.910e 259.66744 1.67mho / m e9.66744 1 25 resistivity0.6Ωm 2.9 10 213  14 1.83 10 / m σn 1.5795 10 2 32 n n 2.56 10 11 3 (c) EEKTIn o p i  1.39  10 / m Fi  n n 1.83 1021 ni n 20 Q.120 (3) 3 10 26 10In 16 It is known that foran N-MOSFET 1.5 10 the Vp is a negative number. Hence, 0.026In 6.67 102 0.23eV   the minimum values of VDS required (d) Minority carrier concentration to keep it in saturation is

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission V ≥ V − V = 1 − (−2) = 3V 2 DS GS p 3 1 10101  4 Q.121 () 1010.255.625mA.2 2 Since both IGFETs are connected in  parallel, the resulting drain current II5.625mA3.6mAD2DI of the composite IGFET is  2 . 0 2 5 mA 2 3 VGS I'210101D   5 Q.124 () For V 0V  V  1V Hence, GS th δ I ' channel does not form ,ID = 0 g  D m For V = 2 V > V = 1 V, δVGS GS th channel forms and the equation of 3 VGS 1 2210101  I is 55 D

As VDSGSth V V  , therefore it is 3 VGS  8  1 0 1  5 operating in linear region. 2 W VDS IDnoxGSthDS μCVVV   Q.122 (2.5) L2 2 VVV242VDSGSpo   5 0.1 2510216 0.1 2  V 12 II1GS DDSS  125100.10.0056 Vp  2 12511.875 μA 3 1 10101  2 Q.125 (200) 101010.52.5mA3  2 Vλ 200 ro  200KΩ I1mAC Q.123 (2.02) For Q.126 (405) V1V,VVV  GS pGSDS ε 3.978.8541014 C ox  1V3V4V  ox 8 t40010ox  Similarly, 0.08810 6 For VGS   2V,Vp   3V   5V As VDS > VGS − Vth it is operating 2  in saturation VGS IDI I DSS  1  W 2 Vp  IDμ n C ox (V GS V th ) 2 L 3 2 6 2 10101  0.088  10 μn  4  1.99  5 144 2 2 2 1010.43.6mA. μ405cmn  / s  0.355 2 V I I 1 GS D2 DSS  Q.127 (125) Vp

© Copyright Reserved by Gateflix.in No part of this material should be copied or reproduced without permission VV422V β 1 0 0 GSth α  1β 1 0 1 VSaturationDS 0 . 9 9 0 0 9 9 0 . 9 9 1W 2 IC μVV1λV  DoxnGSth2L DS Q.130 (0.64) 0.2 2 2   1  0.02  2  V/VBET 0.7/0.026 2 ICS I e x p , 1 I e xS p 26.923 11  0 . 4 (1 . 0 4 ) Iexp4.9310ISS = 0.416mA 15 ∴ IS  2 10 A 1W 2 IC μVV1λV  I I e x p V/0.026B DSoxnGSth2L DS CS 2 1015 expVB /0.026 0.2 2   210.025   2 ⇒ 0 . 1 1 0 3  0 . 4 (1 . 1) = 0.44mA ⇒ VBE  0.026  24.6353  0.64V

Increase in IIDD 0.440.4160.024mA, Q.131 ()

Kt21 V  DS 5  2 3 V ICBO1CO I e x p ,

3V Kt22 IIexp,CBO2CO rd 125KΩ 0.024mA I CBO2  exp,K(tt221 ) I Q.128 (0.43) CBO1 IIexp K221 (tt ) NN CBO2CBO1 VVIn DA 0T 2 I15nAexp 0.07 50 ni CBO2 10102224 15nAexp151033.123.5 9  0.026In 6.2510 38 0.510A6 108  0.026In 6.25 Q.132 (0.833) 8 II5 0.026 In10 In6.25 β5,αCC0.833 RRII51  = 0.026(8 × In10 − In6.25) BE = 0.026(8 × 2.3 − 1.83) = 0.026 × 16.57 = 0.431 V

Q.129 (0.99)

IcβI B  1  β  ICO   1  β  IB β1mA100mA ∴ β = 100 The current amplification ratio in CE = β = 100 The current amplification ratio in CB =∝ and it is expressed as

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