(37-023) Programming in Assembler Basics

Eidgenössische Technische Hochschule Zürich

Programming in Systems (37-023)

Programming in Assembler Basics of Operating Systems Models of Computer Architecture Lecturer today: Prof. Thomas M. Stricker Text-/Reference-Books: R.P.Paul: SPARC Architecture... and C Sun SPARC V8 Manual and K&R C Reference Topics of Today: • Simple Computer Architectures • Stack Machines • Register Machines

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Simple Pocket Calculator

Evaluation of an equation with a four function calculator (a pocket calculator for dummies)

()x – 1 × ()x – 7 x =10 y = ------(3.1) ()x – 11 Requires storage of intermediate results:

()10– 1 = 9 (3.2)

()10– 7 = 3 (3.3)

()93× = 27 (3.4)

()10– 11 = –1 (3.5)

27⁄ ()– 1 = –27 (3.6) Pocket calculator does only have an ALU (Arithmetic Logic Unit) No memory for the storage of data!

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The RPN Pocket Calculator

First-in, Last out: a data structure that allows access only to the topmost element in storage. Elementary Operations: • Push on stack: data item -> (stack) • Pop from stack: data item <- (stack) Advantage: • No addressing of data necessary • Simple commands: enter: Display register stored to stack explicit push

+, -, *,/: Operation of the two topmost elements in the stack and storage of the result into topmost register.

implicit pop

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Evaluation of an expression

()x – 1 × ()x – 7 x =10 y = ------(3.7) ()x – 11

10 enter 1 - 10 enter 7 - * 10 enter 11 - / Representation of the stacks

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The stack architecture

• B5000 - 1963 introduced by Burroughs • Does not have additional register • push and pop operations on the stack • push (address) • pop (address) • Program-counter / instruction register Design with stack including the ALU

tos tos-1 ALU + / * -

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Advantage stack: no addressing no exchange commands (e.g. x<>y). Disadvantage stack: not suited for the efficient storage of intermediate results. Solution to the problem Introduction of addressable storage (register) Commands

• sto : store into Register • rcl : load into Register

Evaluation of the expression: 10 sto 0 1- rcl 0 7 - REG ALU + / * - Block * R1 R2 R3 R4 rcl 0 11 - / Adressen

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Instruction Set • Rockwell 6502: 8bit • Intel 8086: 16bit • MIPS/SPARC/Dec Alpha/Pentium 32bit • LIW 96bit, VLIW 256bit-512bit Layout of an instruction (word): • Classic 32bit - 3 operand structure 31 15 10 5 0 OPt OPc Rsrc Rsrc Rdst ALU Op Op Rslt Op A B Register machines • normally about 16-64 register • SPARC has a window of 32 registers (5 bits needed to address a register)

10/31/01 - 7 37-023-01 © Alonso/Stricker RISC vs. CISC: (a key question)

CISC: Complex Instruction Set Computers DEC VAX, IBM 370, Intel 80x86... Idea: do as much as possible with one instr. Problem: it is almost impossible to make this fast (>100 MHz) - or maybe not... see Intel. RISC: Reduced Instruction Set Computers MIPS (Nintendo64), SPARC (Sun), DEC-Alpha, IBM R6000 Idea: Make instruction so simple that they can be executed as 1 Clock = 1 Instruction. Implementation: Compose more complex operations from multiple instructions. RISC by John Cocke [IBM], D.Patterson [Berkeley], J.Hennessey [Stanford] Timeframe: 1980-1985.

• First general purpose computer ENIAC (1946) with 18000 vacuum tubes. • Architecture: 20 register (10 digits) • Integration of program- and data-storage • Addressable memory (core-memory) Von Neumann cycle pc = 0; do { instruction = memory[pc++]; decode(intruction); fetch (operands); execute; store(results); } while (intruction !=halt);

PC: Programm counter

Before: Programs on punched tape, ﬁlm or oder separate medium.

Alternatives: Harvard architecture

Parts:

Composition of register and ALU

...put it all together