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The SPARC Architecture Manual The SPARC Architecture Manual Version 9 SPARC International, Inc. San Jose, California David L. Weaver / Tom Germond Editors SAV09R1459912 PTR Prentice Hall, Englewood Cliffs, New Jersey 07632 SPARC® is a registered trademark of SPARC International, Inc. The SPARC logo is a registered trademark of SPARC International, Inc. UNIX® is a registered trademark of UNIX System Laboratories, Inc. Copyright © 1994 SPARC International, Inc. Published by PTR Prentice Hall Prentice-Hall, Inc. A Paramount Communications Company Englewood Cliffs, New Jersey 07632 The publisher offers discounts on this book when ordered in bulk quantities. For more information, contact: Corporate Sales Department PTR Prentice Hall 113 Sylvan Avenue Englewood Cliffs, NJ 07632 Phone: (201) 592-2863 Fax: (201) 592-2249 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the copyright owners. Restricted rights legend: use, duplication, or disclosure by the U. S. Government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and in similar clauses in the FAR and NASA FAR Sup- plement. Printed in the United States of America 109 87654321 ISBN 0-13-825001-4 PRENTICE-HALL INTERNATIONAL (UK) LIMITED, London PRENTICE-HALL OF AUSTRALIA PTY. LIMITED, Sydney PRENTICE-HALL CANADA INC., Toronto PRENTICE-HALL HISPANOAMERICANA, S.A., Mexico PRENTICE-HALL OF INDIA PRIVATE LIMITED, New Delhi PRENTICE-HALL OF JAPAN, INC., Tokyo SIMON & SCHUSTER ASIA PTE. LTD., Singapore EDITORA PRENTICE-HALL DO BRASIL, LTDA., Rio de Janeiro Contents Introduction ............................................................................................................. xiii 0.1 SPARC .................................................................................................... xiii 0.2 Processor Needs for the 90s and Beyond ................................................ xiv 0.3 SPARC-V9: A Robust RISC for the Next Century ................................ xiv 0.3.1 64-bit Data and Addresses ....................................................... xiv 0.3.2 Improved System Performance ................................................ xv 0.3.3 Advanced Optimizing Compilers ............................................ xvi 0.3.4 Advanced Superscalar Processors ............................................ xvii 0.3.5 Advanced Operating Systems .................................................. xvii 0.3.6 Fault Tolerance ........................................................................ xviii 0.3.7 Fast Traps and Context Switching ........................................... xviii 0.3.8 Big- and Little-Endian Byte Orders ......................................... xix 0.4 Summary ................................................................................................. xix Editors’ Notes .......................................................................................................... xxi Acknowledgments ............................................................................................... xxi Personal Notes .................................................................................................... xxi 1 Overview ............................................................................................................ 1 1.1 Notes About this Book ............................................................................ 1 1.1.1 Audience .................................................................................. 1 1.1.2 Where to Start .......................................................................... 1 1.1.3 Contents ................................................................................... 1 1.1.4 Editorial Conventions .............................................................. 3 1.2 The SPARC-V9 Architecture ................................................................. 4 1.2.1 Features .................................................................................... 4 1.2.2 Attributes .................................................................................. 5 1.2.3 System Components ................................................................ 6 1.2.4 Binary Compatibility ............................................................... 6 1.2.5 Architectural Definition ........................................................... 7 1.2.6 SPARC-V9 Compliance .......................................................... 7 2 Definitions .......................................................................................................... 9 3 Architectural Overview .................................................................................... 15 3.1 SPARC-V9 Processor ............................................................................. 15 3.1.1 Integer Unit (IU) ...................................................................... 15 3.1.2 Floating-Point Unit (FPU) ...................................................... 16 3.2 Instructions .............................................................................................. 16 3.2.1 Memory Access ....................................................................... 17 3.2.2 Arithmetic/Logical/Shift Instructions ...................................... 19 3.2.3 Control Transfer ....................................................................... 19 3.2.4 State Register Access ............................................................... 20 3.2.5 Floating-Point Operate ............................................................. 20 3.2.6 Conditional Move .................................................................... 20 3.2.7 Register Window Management ................................................ 20 3.3 Traps ....................................................................................................... 21 4 Data Formats ..................................................................................................... 23 4.1 Signed Integer Byte ................................................................................. 23 4.2 Signed Integer Halfword ......................................................................... 24 4.3 Signed Integer Word ............................................................................... 24 4.4 Signed Integer Double ............................................................................ 24 4.5 Signed Extended Integer ......................................................................... 24 4.6 Unsigned Integer Byte ............................................................................ 24 4.7 Unsigned Integer Halfword ..................................................................... 24 4.8 Unsigned Integer Word ........................................................................... 25 4.9 Unsigned Integer Double ........................................................................ 25 4.10 Unsigned Extended Integer ..................................................................... 25 4.11 Tagged Word .......................................................................................... 25 4.12 Floating-Point Single Precision .............................................................. 25 4.13 Floating-Point Double Precision ............................................................. 26 4.14 Floating-Point Quad Precision ................................................................ 26 5 Registers ............................................................................................................. 29 5.1 Nonprivileged Registers .......................................................................... 30 5.1.1 General Purpose r Registers ..................................................... 30 5.1.2 Special r Registers ................................................................... 34 5.1.3 IU Control/Status Registers ..................................................... 35 5.1.4 Floating-Point Registers .......................................................... 36 5.1.5 Condition Codes Register (CCR) ............................................ 40 5.1.6 Floating-Point Registers State (FPRS) Register ...................... 42 5.1.7 Floating-Point State Register (FSR) ........................................ 43 5.1.8 Address Space Identifier Register (ASI) ................................. 50 5.1.9 TICK Register (TICK) ............................................................. 50 5.2 Privileged Registers ................................................................................ 51 5.2.1 Processor State Register (PSTATE) ........................................ 51 5.2.2 Trap Level Register (TL) ......................................................... 54 5.2.3 Processor Interrupt Level (PIL) ............................................... 54 5.2.4 Trap Program Counter (TPC) .................................................. 55 5.2.5 Trap Next Program Counter (TNPC) ....................................... 55 5.2.6 Trap State (TSTATE) .............................................................. 56 5.2.7 Trap Type Register (TT) .......................................................... 56 5.2.8 Trap Base Address (TBA) ....................................................... 57 5.2.9 Version Register (VER) ..........................................................
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