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Computer Architecture and Assembly Language

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Computer Architecture and Assembly Language Computer Architecture and Assembly Language Gabriel Laskar EPITA 2015 License I Copyright c 2004-2005, ACU, Benoit Perrot I Copyright c 2004-2008, Alexandre Becoulet I Copyright c 2009-2013, Nicolas Pouillon I Copyright c 2014, Joël Porquet I Copyright c 2015, Gabriel Laskar Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with the Invariant Sections being just ‘‘Copying this document’’, no Front-Cover Texts, and no Back-Cover Texts. Introduction Part I Introduction Gabriel Laskar (EPITA) CAAL 2015 3 / 378 Introduction Problem definition 1: Introduction Problem definition Outline Gabriel Laskar (EPITA) CAAL 2015 4 / 378 Introduction Problem definition What are we trying to learn? Computer Architecture What is in the hardware? I A bit of history of computers, current machines I Concepts and conventions: processing, memory, communication, optimization How does a machine run code? I Program execution model I Memory mapping, OS support Gabriel Laskar (EPITA) CAAL 2015 5 / 378 Introduction Problem definition What are we trying to learn? Assembly Language How to “talk” with the machine directly? I Mechanisms involved I Assembly language structure and usage I Low-level assembly language features I C inline assembly Gabriel Laskar (EPITA) CAAL 2015 6 / 378 I Programmers I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts Gabriel Laskar (EPITA) CAAL 2015 7 / 378 I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts I Programmers Gabriel Laskar (EPITA) CAAL 2015 7 / 378 I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts I Programmers C/C++ Gabriel Laskar (EPITA) CAAL 2015 7 / 378 I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts I Programmers C/C++, Objective-C Gabriel Laskar (EPITA) CAAL 2015 7 / 378 I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts I Programmers C/C++, Objective-C, C# Gabriel Laskar (EPITA) CAAL 2015 7 / 378 I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts I Programmers C/C++, Objective-C, C#, Java Gabriel Laskar (EPITA) CAAL 2015 7 / 378 I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts I Programmers C/C++, Objective-C, C#, Java, JS/AS Gabriel Laskar (EPITA) CAAL 2015 7 / 378 I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts I Programmers at any level: (C/C++, Objective-C, C#, Java, JS/AS, etc.) Gabriel Laskar (EPITA) CAAL 2015 7 / 378 Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts I Programmers at any level: (C/C++, Objective-C, C#, Java, JS/AS, etc.) I Wise managers Gabriel Laskar (EPITA) CAAL 2015 7 / 378 Introduction Outline 1: Introduction Problem definition Outline Gabriel Laskar (EPITA) CAAL 2015 8 / 378 Introduction Outline Course outline I Processor architecture I Memory I Memory mapping I Execution flow I Object file formats I Assembly programming I Focus on x86 I Focus on RISC processors I CPU-aware optimizations I Multi-/Many-core, heterogeneous systems Gabriel Laskar (EPITA) CAAL 2015 9 / 378 Processor architecture Part II Processor architecture Gabriel Laskar (EPITA) CAAL 2015 10 / 378 Processor architecture Overview 2: Processor architecture Overview Inside the processor Processor units Instructions Instruction flow Pipeline processor CISC & RISC architectures Gabriel Laskar (EPITA) CAAL 2015 11 / 378 Let’s design it! Processor architecture Overview What a processor is... A processor must be able to perform the following basic tasks: I Execute instructions I Read operands I Store results It needs several basic units to perform those tasks: I A control unit I An arithmetic and logical unit (ALU) I A register bank Gabriel Laskar (EPITA) CAAL 2015 12 / 378 Processor architecture Overview What a processor is... A processor must be able to perform the following basic tasks: I Execute instructions I Read operands I Store results It needs several basic units to perform those tasks: I A control unit I An arithmetic and logical unit (ALU) I A register bank Let’s design it! Gabriel Laskar (EPITA) CAAL 2015 12 / 378 Processor architecture Overview Basic architecture R0 R1 R2 = 0123 R3 = 0100 R4 = 0023 R5 Registers ALU Control Unit Gabriel Laskar (EPITA) CAAL 2015 13 / 378 Unfortunately, I Internal memory is expensive and hard to design I There is no communication I Updating the program may not be easy We need an access to memory, external devices, etc. Processor architecture Overview Basic architecture (2) In this model, the system state is entirely contained in the processor. I This might be sufficient for a very basic processor I More features could be leveraged by adding registers or program steps Gabriel Laskar (EPITA) CAAL 2015 14 / 378 We need an access to memory, external devices, etc. Processor architecture Overview Basic architecture (2) In this model, the system state is entirely contained in the processor. I This might be sufficient for a very basic processor I More features could be leveraged by adding registers or program steps Unfortunately, I Internal memory is expensive and hard to design I There is no communication I Updating the program may not be easy Gabriel Laskar (EPITA) CAAL 2015 14 / 378 Processor architecture Overview Basic architecture (2) In this model, the system state is entirely contained in the processor. I This might be sufficient for a very basic processor I More features could be leveraged by adding registers or program steps Unfortunately, I Internal memory is expensive and hard to design I There is no communication I Updating the program may not be easy We need an access to memory, external devices, etc. Gabriel Laskar (EPITA) CAAL 2015 14 / 378 It needs several basic units to perform those tasks: I A control unit I An arithmetic and logical unit (ALU) I A register bank I A program memory access I A data memory access Processor architecture Overview Revised processor model A processor must be able to perform the following basic tasks: I Fetch instructions from an external entity and understand them (fetch and decode) I Execute instructions I Store results to registers or external memory Gabriel Laskar (EPITA) CAAL 2015 15 / 378 Processor architecture Overview Revised processor model A processor must be able to perform the following basic tasks: I Fetch instructions from an external entity and understand them (fetch and decode) I Execute instructions I Store results to registers or external memory It needs several basic units to perform those tasks: I A control unit I An arithmetic and logical unit (ALU) I A register bank I A program memory access I A data memory access Gabriel Laskar (EPITA) CAAL 2015 15 / 378 Processor architecture Overview Revised processor model (2) R0 R1 R2 = 0123 R3 = 0100 R4 = 0023 R5 Registers ALU Control Unit Instruction @ Code Command R Data Data @ W Data Gabriel Laskar (EPITA) CAAL 2015 16 / 378 Processor architecture Overview Processor physical layout A processor is composed of many different units: I Caches, MMU I Integer unit, Control unit, Floating-point unit Each unit is: I implemented as an hardware component I made of switchable parts (transistors) In old processors: I Units used to be independent chips I Some were even optional “coprocessors” Today, processors are embedded on a single chip. Gabriel Laskar (EPITA) CAAL 2015 17 / 378 Processor architecture Inside the processor 2: Processor architecture Overview Inside the processor Processor units Instructions Instruction flow Pipeline processor CISC & RISC architectures Gabriel Laskar (EPITA) CAAL 2015 18 / 378 Processor architecture Inside the processor Processor package Gabriel Laskar (EPITA) CAAL 2015 19 / 378 Processor architecture Inside the processor Processor physical layout Gabriel Laskar (EPITA) CAAL 2015 20 / 378 Processor architecture Inside the processor Processor physical layout Gabriel Laskar (EPITA) CAAL 2015 21 / 378 Processor architecture Inside the processor Processor physical layout Transistor details Gabriel Laskar (EPITA) CAAL 2015 22 / 378 Processor architecture Processor units 2: Processor architecture Overview Inside the processor Processor units Instructions Instruction flow Pipeline processor CISC & RISC architectures Gabriel Laskar (EPITA) CAAL 2015 23 / 378 Processor architecture Processor units Units R0 R1 R2 = 0123 R3 = 0100 I Control unit fetches and R4 = 0023 decodes the instruction R5 Registers I Registers gives the data I ALU implements the operation ALU I Some instructionsControl Unit access external data Instruction @ Code Command R Data Data @ W Data Gabriel Laskar (EPITA) CAAL 2015 24 / 378 Processor architecture Processor units Registers May be seen as variables located inside the processor I 8, 16, 32, 64, 128, ... -bits large I General-purpose registers: I integer (int) I floating point (float, double) I Specialized registers: I flags I Zero, I Negative, I Carry, I Overflow, I etc. I system I Mode, I IRQ masking, I etc. Gabriel Laskar (EPITA) CAAL 2015 25 / 378 Processor architecture Processor units ALU: Arithmetic and Logical Unit An unit without registers! I Logical operations I AND, OR, XOR, NOT, NOR I Arithmetic operations I addition, subtraction, multiplication,
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