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Ultrasparc Architecture 2007 UltraSPARC Architecture 2007 One Architecture ... Multiple Innovative Implementations Draft D0.9.4, 27 Sep 2010 Privilege Levels: Hyperprivileged, Privileged, and Nonprivileged Distribution: Public Part No.No: 950-5554-15 ReleaseRevision: 1.0, Draft 2002 D0.9.4, 27 Sep 2010 Oracle Corporation 4150 Network Circle Santa Clara, CA 95054 U.S.A. 650-960-1300 ii UltraSPARC Architecture 2007 • Draft D0.9.4, 27 Sep 2010 Copyright © 2007, 2011, Oracle and/or its affiliates. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective owners. AMD, Opteron, the AMD logo, and the AMD Opteron logo are trademarks or registered trademarks of Advanced Micro Devices. Intel and Intel Xeon are trademarks or registered trademarks of Intel Corporation. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. UNIX is a registered trademark licensed through X/Open Company, Ltd.. Comments and "bug reports” regarding this document are welcome; they should be submitted to email address: [email protected] iv UltraSPARC Architecture 2007 • Draft D0.9.4, 27 Sep 2010 Contents Preface. i 1 Document Overview . 1 1.1 Navigating UltraSPARC Architecture 2007 . 1 1.2 Fonts and Notational Conventions . 2 1.2.1 Implementation Dependencies . 3 1.2.2 Notation for Numbers. 3 1.2.3 Informational Notes . 3 1.3 Reporting Errors in this Specification . 4 2 Definitions . 5 3 Architecture Overview. 15 3.1 The UltraSPARC Architecture 2007. 15 3.1.1 Features. 15 3.1.2 Attributes . 16 3.1.2.1 Design Goals . 17 3.1.2.2 Register Windows . 17 3.1.3 System Components . 17 3.1.3.1 Binary Compatibility. 17 3.1.3.2 UltraSPARC Architecture 2007 MMU . 17 3.1.3.3 Privileged Software . 17 3.1.4 Architectural Definition . 18 3.1.5 UltraSPARC Architecture 2007 Compliance with SPARC V9 Architecture 18 3.1.6 Implementation Compliance with UltraSPARC Architecture 2007 18 3.2 Processor Architecture . 18 3.2.1 Integer Unit (IU) . 18 3.2.2 Floating-Point Unit (FPU). 19 3.3 Instructions. 19 3.3.1 Memory Access . 19 3.3.1.1 Memory Alignment Restrictions . 20 3.3.1.2 Addressing Conventions . 20 3.3.1.3 Addressing Range . 20 3.3.1.4 Load/Store Alternate . 20 3.3.1.5 Separate Instruction and Data Memories . 21 3.3.1.6 Input/Output (I/O) . 21 3.3.1.7 Memory Synchronization . 21 3.3.2 Integer Arithmetic / Logical / Shift Instructions . 21 3.3.3 Control Transfer . 22 3.3.4 State Register Access . 22 3.3.4.1 Ancillary State Registers. 22 3.3.4.2 PR State Registers . 22 i 3.3.4.3 HPR State Registers . 23 3.3.5 Floating-Point Operate. 23 3.3.6 Conditional Move . 23 3.3.7 Register Window Management. 23 3.3.8 SIMD. 23 3.4 Traps. .23 3.5 Chip-Level Multithreading (CMT) . 24 4 Data Formats. 25 4.1 Integer Data Formats . 26 4.1.1 Signed Integer Data Types . 26 4.1.1.1 Signed Integer Byte, Halfword, and Word. 27 4.1.1.2 Signed Integer Doubleword (64 bits) . 27 4.1.1.3 Signed Integer Extended-Word (64 bits) . 27 4.1.2 Unsigned Integer Data Types . 27 4.1.2.1 Unsigned Integer Byte, Halfword, and Word . 28 4.1.2.2 Unsigned Integer Doubleword (64 bits). 28 4.1.2.3 Unsigned Extended Integer (64 bits) . 28 4.1.3 Tagged Word (32 bits). 28 4.2 Floating-Point Data Formats . 29 4.2.1 Floating Point, Single Precision (32 bits) . 29 4.2.2 Floating Point, Double Precision (64 bits) . 29 4.2.3 Floating Point, Quad Precision (128 bits). 30 4.2.4 Floating-Point Data Alignment in Memory and Registers . 31 4.3 SIMD Data Formats . 31 4.3.1 Uint8 SIMD Data Format . 32 4.3.2 Int16 SIMD Data Formats . 32 4.3.3 Int32 SIMD Data Format . 32 5 Registers . 33 5.1 Reserved Register Fields . 34 5.2 General-Purpose R Registers. 35 5.2.1 Global R Registers. 36 5.2.2 Windowed R Registers. 36 5.2.3 Special R Registers . 39 5.3 Floating-Point Registers . 40 5.3.1 Floating-Point Register Number Encoding . 42 5.3.2 Double and Quad Floating-Point Operands . 43 5.4 Floating-Point State Register (FSR) . 44 5.4.1 Floating-Point Condition Codes (fcc0, fcc1, fcc2, fcc3). 44 5.4.2 Rounding Direction (rd) . 45 5.4.3 Trap Enable Mask (tem) . 45 5.4.4 Nonstandard Floating-Point (ns) . 45 5.4.5 FPU Version (ver) . 45 5.4.6 Floating-Point Trap Type (ftt). 46 5.4.7 Accrued Exceptions (aexc) . 48 5.4.8 Current Exception (cexc) . 48 5.4.9 Floating-Point Exception Fields . 49 5.4.10 FSR Conformance . 50 5.5 Ancillary State Registers . 50 5.5.1 32-bit Multiply/Divide Register (Y) (ASR 0) . 52 5.5.2 Integer Condition Codes Register (CCR) (ASR 2) . 52 5.5.2.1 Condition Codes (CCR.xcc and CCR.icc) . 52 5.5.3 Address Space Identifier (ASI) Register (ASR 3). 53 5.5.4 Tick (TICK) Register (ASR 4) . 54 5.5.5 Program Counters (PC, NPC) (ASR 5) . 55 ii UltraSPARC Architecture 2007 • Draft D0.9.4, 27 Sep 2010 5.5.6 Floating-Point Registers State (FPRS) Register (ASR 6). 55 5.5.7 General Status Register (GSR) (ASR 19). 56 5.5.8 SOFTINTP Register (ASRs 20, 21, 22) . ..
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