DOCSLIB.ORG

A Security Architecture for Microprocessors

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

A Security Architecture for Microprocessors Doctoral Thesis J¨orgPlatte Genehmigte Dissertation zur Erlangung des akademischen Grades eines Doktors an der Fakult¨atf¨urElektrotechnik und Informationstechnik Technischen Universit¨atDortmund Abteilung Informationstechnik Institut f¨urRoboterforschung 06.11.2008 II Acknowledgements It is my pleasure to thank all the people who supported me to make this thesis possible. Pr¨ufungskommission: • Prof. Dr.-Ing. Christian Rehtanz (Vorsitzender) • Prof. Dr.-Ing. Uwe Schwiegelshohn (Referent) • Prof. Dr.-Ing. Christian Grimm (Korreferent) • Dr.-Ing. Wolfgang Endemann III Abstract The Security Architecture for Microprocessors (SAM ) is a lightweight and high-performance combined hard- and software security extension for microprocessors. SAM has been designed to provide a secure remote code execution environment. It can be used to implement effective copy-protection schemes and provides mechanisms to prevent data and algorithm disclosure. SAM provides protection even if an attacker has full access to both the operating system and hardware. SAM uses an enhanced processor core which can be used as a drop in replacement for a standard processor to provide transparent encryption and hashing of memory contents to prevent external tampering and sniffing attacks. Further internal security-related extensions support a secure operating system implementation. Both the hardware and software design are presented in this thesis. IV Contents List of Figures E List of Tables F List of Algorithms G 1 Introduction 1 I Software Protection Schemes 5 2 Computer and Operating System Architecture 6 2.1 Processor Overview . 6 2.1.1 Instruction Set Protection Mechanisms . 7 2.1.2 Virtual Memory . 7 2.1.3 Memory Hierarchy . 7 2.1.4 Interrupts . 8 2.2 Operating Systems . 9 2.2.1 Memory Layout . 9 2.2.2 Interrupts . 10 2.2.3 Virtual Memory Handling . 10 2.3 Protection Mechanisms . 11 2.3.1 Multiuser Environment . 11 2.3.2 File System . 11 2.3.3 Process Management . 11 2.3.4 Administrator Access . 12 2.3.5 Sophisticated Access Control . 12 3 Security Issues 13 3.1 Hardware Access . 13 3.2 Software-Based Attacks . 14 3.3 Side Channel Attacks . 15 3.4 Program Analysis . 15 3.5 Copy Protection . 17 3.6 Sandbox Security . 17 A B CONTENTS 4 Cryptography 19 4.1 Symmetric Cryptography . 19 4.1.1 Random Number Generation . 19 4.1.2 Algorithms . 20 4.1.3 Modes of Operation . 20 4.2 Data Integrity . 21 4.3 Asymmetric Cryptography . 22 4.4 Key Exchange Protocols . 23 4.5 Cryptographic Attacks . 23 4.5.1 Brute Force . 23 4.5.2 Known Plaintext . 24 4.5.3 Related-Key Attack . 24 4.5.4 Replay Attacks . 24 4.5.5 XOR Security Considerations . 24 4.5.6 Man-in-the-Middle . 25 4.5.7 Other Attacks . 25 4.6 Standard Protocols . 25 5 Security Architectures 26 5.1 Memory Protection Schemes . 26 5.1.1 Hash Trees . 26 5.1.2 Memory Encryption . 27 5.1.3 Hiding Address Information . 27 5.2 Security Architectures . 28 5.2.1 Smart Cards . 28 5.2.2 Secure Co-Processors . 28 5.2.3 LaGrande . 29 5.2.4 Digital Rights Management . 29 5.2.5 X-Box . 30 5.2.6 XOM . 30 5.2.7 AEGIS . 31 II The Security Architecture for Microprocessors (SAM ) 35 6 SAM Design Goals 36 6.1 Motivation . 36 6.2 Requirements for Secure Computing . 37 6.2.1 Hardware Requirements . 38 6.2.2 Software Requirements . 39 7 Processor Architecture 40 7.1 Overview . 40 7.2 Cryptographic Keys . 40 7.3 Tamper Detection Unit . 42 7.4 RSA Unit and SAM Configurator . 42 7.5 Cryptographic Functions . 42 CONTENTS C 7.6 Security-Aware Cache . 42 7.7 Memory Layout . 42 7.7.1 Memory Views . 44 7.8 Protected Operating System . 44 7.8.1 Protected TRAP Table . 45 7.8.2 Sparse Hash Tree . 46 7.9 SAM Instruction Set . 47 7.10 Speculative Execution . 48 7.10.1 Memory Decryption Attack . 48 7.10.2 Secure Speculative Execution . 48 8 Memory Protection 50 8.1 Memory Integrity Verification . 50 8.2 Memory Encryption . 53 9 SAM Implementations 55 9.1 SAM for SPARC . 55 9.1.1 Register Protection . 56 9.1.2 Instruction Set . 57 9.1.3 Context Switches . 61 9.1.4 TRAP Modifications . 61 9.1.5 Memory-Mapped Configuration Registers . 61 9.1.6 Cache . 62 9.1.7 Further Changes . 62 9.2 SAM for IA-32 Processors . 62 9.2.1 Register Protection . 63 9.2.2 Context Handling and Configuration . 63 9.2.3 Privilege Level Transitions . 64 9.2.4 Instruction Set . 65 9.3 Multiprocessor Support . 65 10 SAM Operating System Design 67 10.1 Threats . 67 10.2 Protected Kernel . 68 10.2.1 Limitations . 69 10.2.2 Loading Protected Programs . 69 10.2.3 Hash Tree Handling . 70 10.2.4 User-Supervisor Mode Transitions . 71 10.2.5 Protected Compartment . 72 10.2.6 System Calls . 72 10.2.7 Multi Threading and Signal Handling . 73 11 Cache Architecture 74 11.1 Comparison with other Caches . 74 11.2 L1 Data Cache . 74 11.3 L1 Instruction Cache . 78 11.4 L2 Cache . 78 D CONTENTS 11.4.1 TAG RAM . ..
Recommended publications
  • Risc I: a Reduced Instruction Set Vlsi Computer

    Risc I: a Reduced Instruction Set Vlsi Computer

    RISC I: A REDUCED INSTRUCTION SET VLSI COMPUTER DAVID A. PATTERSON and CARLO H. SEQUIN Computer Science Division University of California Berkeley, California ABSTRACT to implement CISC is the best way to use this “scarce” resource. The Reduced Instruction Set Computer (RISC) Project investigates an alternatrve to the general trend toward computers wrth increasingly complex instruction sets: With a The above findings led to the Reduced Instruction Set proper set of instructions and a corresponding architectural Computer (RISC) Project. The purpose of the project is design, a machine wrth a high effective throughput can be to explore alternatives to the general trend toward achieved. The simplicity of the instruction set and addressing architectural complexity. The hypothesis is that by modes allows most Instructions to execute in a single machine cycle, and the srmplicity of each instruction guarantees a short reducing the instruction set, VLSI architecture can be cycle time. In addition, such a machine should have a much designed that uses the scarce resources more effectively shorter design trme. than CISC. We also expect this approach to reduce design time, the number of design errors, and the This paper presents the architecture of RISC I and its novel execution time of individual instructions. hardware support scheme for procedure call/return. Overlapprng sets of regrster banks that can pass parameters directly to subrouttnes are largely responsible for the excellent Our initial version of such a computer is called RISC I. performance of RISC I. Static and dynamtc comparisons To meet our goals of simplicity and effective single-chip between this new architecture and more traditional machines implementation, we placed the following “constraints” are given.
  • Computer Architecture and Assembly Language

    Computer Architecture and Assembly Language

    Computer Architecture and Assembly Language Gabriel Laskar EPITA 2015 License I Copyright c 2004-2005, ACU, Benoit Perrot I Copyright c 2004-2008, Alexandre Becoulet I Copyright c 2009-2013, Nicolas Pouillon I Copyright c 2014, Joël Porquet I Copyright c 2015, Gabriel Laskar Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with the Invariant Sections being just ‘‘Copying this document’’, no Front-Cover Texts, and no Back-Cover Texts. Introduction Part I Introduction Gabriel Laskar (EPITA) CAAL 2015 3 / 378 Introduction Problem definition 1: Introduction Problem definition Outline Gabriel Laskar (EPITA) CAAL 2015 4 / 378 Introduction Problem definition What are we trying to learn? Computer Architecture What is in the hardware? I A bit of history of computers, current machines I Concepts and conventions: processing, memory, communication, optimization How does a machine run code? I Program execution model I Memory mapping, OS support Gabriel Laskar (EPITA) CAAL 2015 5 / 378 Introduction Problem definition What are we trying to learn? Assembly Language How to “talk” with the machine directly? I Mechanisms involved I Assembly language structure and usage I Low-level assembly language features I C inline assembly Gabriel Laskar (EPITA) CAAL 2015 6 / 378 I Programmers I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts Gabriel Laskar (EPITA) CAAL
  • VME for Experiments Chairman: Junsei Chiba (KEK)

    VME for Experiments Chairman: Junsei Chiba (KEK)

    KEK Report 89-26 March 1990 D PROCEEDINGS of SYMPOSIUM on Data Acquisition and Processing for Next Generation Experiments 9 -10 March 1989 KEK, Tsukuba Edited by H. FUJII, J. CHIBA and Y. WATASE NATIONAL LABORATORY FOR HIGH ENERGY PHYSICS PROCEEDINGS of SYMPOSIUM on Data Acquisition and Processing for Next Generation Experiments 9 - 10 March 1989 KEK, Tsukuba Edited H. Fiflii, J. Chiba andY. Watase i National Laboratory for High Energy Physics, 1990 KEK Reports are available from: Technical Infonnation&Libraiy National Laboratory for High Energy Physics 1-1 Oho, Tsukuba-shi Ibaraki-ken, 305 JAPAN Phone: 0298-64-1171 Telex: 3652-534 (Domestic) (0)3652-534 (International) Fax: 0298-64-4604 Cable: KEKOHO Foreword This symposium has been organized to foresee the next generation of data acquisition and processing system in high energy physics and nuclear physics experiments. The recent revolutionary progress in the semiconductor and computer technologies is giving us an oppotunity to extend our idea on the experiments. The high density electronics of LSI technology provides an ideal front-end electronics such as readout circuits for silicon strip detector and multi-anode phototubes as well as wire chambers. The VLSI technology has advantages over the obsolite discrete one in the various aspects ; reduction of noise, small propagation delay, lower power dissipation, small space for the installation, improvement of the system reliability and maintenability. The small sized front-end electronics will be mounted just on the detector and the digital data might be transfered off the detector to the computer room with optical fiber data transmission lines. Then, a monster of bandies of signal cables might disappear from the experimental area.
  • MIPS Assembly Language Programming Using Qtspim

    MIPS Assembly Language Programming Using Qtspim

    MIPS Assembly Language Programming using QtSpim Ed Jorgensen, Ph.D. Version 1.1.50 July 2019 Cover image: MIPS R3000 Custom Chip http://commons.wikimedia.org/wiki/File:RCP-NUS_01.jpg Spim is copyrighted by James Larus and distributed under a BSD license. Copyright (c) 1990-2011, James R. Larus. All rights reserved. Copyright © 2013, 2014, 2015, 2016, 2017 by Ed Jorgensen You are free: To Share — to copy, distribute and transmit the work To Remix — to adapt the work Under the following conditions: Attribution — you must attribute the work in the manner specified by the author or licensor (but not in any way that suggests that they endorse you or your use of the work). Noncommercial — you may not use this work for commercial purposes. Share Alike — if you alter, transform, or build upon this work, you may distribute the resulting work only under the same or similar license to this one. Table of Contents 1.0 Introduction...........................................................................................................1 1.1 Additional References.........................................................................................1 2.0 MIPS Architecture Overview..............................................................................3 2.1 Architecture Overview........................................................................................3 2.2 Data Types/Sizes.................................................................................................4 2.3 Memory...............................................................................................................4
  • Design of the RISC-V Instruction Set Architecture

    Design of the RISC-V Instruction Set Architecture

    Design of the RISC-V Instruction Set Architecture Andrew Waterman Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2016-1 http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.html January 3, 2016 Copyright © 2016, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley Committee in charge: Professor David Patterson, Chair Professor Krste Asanovi´c Associate Professor Per-Olof Persson Spring 2016 Design of the RISC-V Instruction Set Architecture Copyright 2016 by Andrew Shell Waterman 1 Abstract Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman Doctor of Philosophy in Computer Science University of California, Berkeley Professor David Patterson, Chair The hardware-software interface, embodied in the instruction set architecture (ISA), is arguably the most important interface in a computer system. Yet, in contrast to nearly all other interfaces in a modern computer system, all commercially popular ISAs are proprietary.
  • Computer Architectures an Overview

    Computer Architectures an Overview

    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
  • Ultrasparc Architecture 2007

    Ultrasparc Architecture 2007

    UltraSPARC Architecture 2007 One Architecture ... Multiple Innovative Implementations Draft D0.9.4, 27 Sep 2010 Privilege Levels: Hyperprivileged, Privileged, and Nonprivileged Distribution: Public Part No.No: 950-5554-15 ReleaseRevision: 1.0, Draft 2002 D0.9.4, 27 Sep 2010 Oracle Corporation 4150 Network Circle Santa Clara, CA 95054 U.S.A. 650-960-1300 ii UltraSPARC Architecture 2007 • Draft D0.9.4, 27 Sep 2010 Copyright © 2007, 2011, Oracle and/or its affiliates. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective owners. AMD, Opteron, the AMD logo, and the AMD Opteron logo are trademarks or registered trademarks of Advanced Micro Devices. Intel and Intel Xeon are trademarks or registered trademarks of Intel Corporation. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. UNIX is a registered trademark licensed through X/Open Company, Ltd.. Comments and "bug reports” regarding this document are welcome; they should be submitted to email address: [email protected] iv UltraSPARC Architecture 2007 • Draft D0.9.4, 27 Sep 2010 Contents Preface. i 1 Document Overview . 1 1.1 Navigating UltraSPARC Architecture 2007 . 1 1.2 Fonts and Notational Conventions . 2 1.2.1 Implementation Dependencies . 3 1.2.2 Notation for Numbers. 3 1.2.3 Informational Notes . 3 1.3 Reporting Errors in this Specification . 4 2 Definitions . 5 3 Architecture Overview. 15 3.1 The UltraSPARC Architecture 2007. 15 3.1.1 Features. 15 3.1.2 Attributes . 16 3.1.2.1 Design Goals .
  • Processor Architectures

    Processor Architectures

    CS143 Handout 18 Summer 2008 30 July, 2008 Processor Architectures Handout written by Maggie Johnson and revised by Julie Zelenski. Architecture Vocabulary Let’s review a few relevant hardware definitions: register: a storage location directly on the CPU, used for temporary storage of small amounts of data during processing. memory: an array of randomly accessible memory bytes each identified by a unique address. Flat memory models, segmented memory models, and hybrid models exist which are distinguished by the way locations are referenced and potentially divided into sections. instruction set: the set of instructions that are interpreted directly in the hardware by the CPU. These instructions are encoded as bit strings in memory and are fetched and executed one by one by the processor. They perform primitive operations such as "add 2 to register i1", "store contents of o6 into memory location 0xFF32A228", etc. Instructions consist of an operation code (opcode) e.g., load, store, add, etc., and one or more operand addresses. CISC: Complex instruction set computer. Older processors fit into the CISC family, which means they have a large and fancy instruction set. In addition to a set of common operations, the instruction set has special purpose instructions that are designed for limited situations. CISC processors tend to have a slower clock cycle, but accomplish more in each cycle because of the sophisticated instructions. In writing an effective compiler back-end for a CISC processor, many issues revolve around recognizing how to make effective use of the specialized instructions. RISC: Reduced instruction set computer. Many modern processors are in the RISC family, which means they have a relatively lean instruction set, containing mostly simple, general-purpose instructions.
  • Paper on Xbox Cluster

    Paper on Xbox Cluster

    Building a large low-cost computer cluster with unmodified Xboxes B.J. Guillot, B. Chapman and J.-F. Pâris Department of Computer Science University of Houston Houston, TX, 77204-3010 [email protected], {chapman, paris}@cs.uh.edu Abstract We propose to build a large low-cost computer cluster in order to study error recovery techniques for today and tomorrow’s large computer clusters. The Xbox game console is an inexpensive computer whose internal architecture is very close to that of a conventional Intel-based personal computer. In addition, it can be rebooted as a Linux computing node through software exploits without having to purchase any additional hardware or even opening the Xbox. We built a four-node cluster consisting of four unmodified Xboxes running Debian Linux and found out that a cluster of Xboxes linked by a Fast Ethernet would constitute a scaled down version of a current generation supercomputer with the same number of nodes. As a result, it would provide a cost-effective testbed for investigating novel distributed error-recovery algorithms and testing how they would scale up. Keywords: computer clusters, game console, Linux, distributed error recovery. 1. Introduction Improvements in technology as well as pricing trends have enabled the construction of clusters with increasingly larger node counts. However, the reliability of the cluster decreases in rough correspondence to the number of configured nodes, greatly reducing the attractiveness of such systems, especially for large or long-running jobs. In general, dealing with faults is a matter for the application developer, who must insert checkpoints into each application and thus periodically save all pertinent data.
  • Computer Architecture

    Computer Architecture

    Computer Architecture Adrian Crăciun January 9, 2018 1 Contents 1 Computer Architecture - Overview and Motivation 6 1.1 The Structured Organization of Computers . 6 1.2 Milestones in Computer Architecture . 14 1.3 The Computer Zoo . 21 1.4 Computer Families . 26 2 Computer Systems Organization 30 2.1 Processors . 31 2.2 Primary Memory / Secondary Memory / Input/Output (Old Slides) 40 3 The Digital Logic Level 73 3.1 Gates and Boolean Algebra . 73 3.2 Basic Digital Logic Circuits . 80 3.3 Memory . 88 3.4 CPU Chips and Buses . 96 3.5 Example CPUs . 102 4 The Microarchitecture Level 109 4.1 An Example Microarchitecture . 109 4.2 An Example ISA: IJVM . 116 4.3 Implementation of the Instruction Set . 122 4.4 Designing the Microarchitecture Level . 127 4.5 Improving Performance . 135 4.6 Example Microarchitectures . 141 5 The Instruction Set Architecture Level 144 5.1 Overview of the Instruction Set Architecture Level . 144 5.2 Memory models . 146 5.3 Registers . 147 5.4 Data Types . 150 5.5 Instruction Formats . 152 5.6 Addressing . 155 5.7 Instruction types . 158 5.8 Flow of control . 162 5.9 Example ISAs . 166 5.10 Comparison of the Instruction Sets . 167 6 The Operating System Machine Level 170 6.1 Virtual Memory . 170 6.2 Virtual I/O Instructions . 172 6.3 Virtual Instructions for Parallel Processes . 173 6.4 Example Operating Systems . 175 7 The Assembly Language Level 177 2 List of Figures 1 Moving between language levels. 7 2 A multilevel machine. 9 3 A multilevel machine with 6 levels.
  • OVERLAPPED REGISTER WINDOWS CISC Versus RISC

    OVERLAPPED REGISTER WINDOWS CISC Versus RISC

    What is RISC? OVERLAPPED REGISTER WINDOWS CISC versus RISC What is RISC? • RISC? RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. • History The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors: – one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called PIPELINING – pipelining: a techique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions; – large number of registers: the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory Reduced Instruction Set Computer (RISC) lMajor characteristics of a RISC architecture »1) Relatively few instructions »2) Relatively few addressing modes »3) Memory access limited to load and store instruction »4) All operations done within the registers of the CPU »5) Fixed-length, easily decoded instruction format »6) Single-cycle instruction execution »7) Hardwired rather than microprogrammed control – RISC Instruction • Only use LOAD and STORE instruction when communicating between memory and CPU • All other instructions are executed within the registers of the CPU without referring to memory Program to evaluate X = ( A + B ) * ( C + D ) R1 M[A] LOAD R1, A R2 M[B] LOAD R2, B R3 M[C] LOAD R3, C R4 M[D] LOAD R4, D R1 R1 R2 ADD R1, R1, R2 R3 R3 R4 ADD R3, R3, R4 R1 R1 R3 MUL R1, R1, R3 M[X ] R1 STORE X, R1 •Load instruction transfers the operand from memory to CPU Register.
  • The Design of a Reduced Instruction Set Computer Using a Silicon Compiler

    The Design of a Reduced Instruction Set Computer Using a Silicon Compiler

    AN ABSTRACT OF THE THESIS OF Licheng Zhang for the degree of Master of Science in Electrical and Computer Engineering presented on June 7, 1989. Title: The Design of A Reduced Instruction Set Computer UsingA Silicon Compiler. Redacted for Privacy Abstract appro ed- John Muff The objective of this thesisisto describe the design and implementation of a VSLI reduced instruction set computer(RISC). The RISC machine constitutes a new style of computerarchitecture. Itdifferssignificantly from the complex instructionset computer architectures(CISC)ofthepast.RISCarchitecturesare characterized by their high performance, simple instructionsets, minimal hardware requirements, and their abilityto support block structured programming languages adequately. In this thesis a 16-bit single chip RISC was designed using the Genesil Silicon Compiler. It has 14 instructions, anoverlapped register window structure,and on chip memory.Itcan execute most instructions in a single clock cycle,including procedure calls and returns. The peak performance of this chip is approximately6 MIPS. The chip was implemented in 2 micron CMOS technology. The chip sizeis 516.54 X 514.27 mils. This chip has not been fabricated. THE DESIGN OF A REDUCED INSTRUCTION SET COMPUTER USING A SILICON COMPLIER By Licheng Zhang A THESIS submittedto Oregon State University in partial fulfillment of the requirement for the degree of Master of Science Completed June 7, 1989 Commencement June,1990. APPROVED: Redacted for Privacy ssor of Electrical and Comp ter gineering in charge of major Redacted for Privacy Head of Department of Electrical and Computer Engineering Redacted for Privacy Dean of Gradua eSchool Date thesis is presented: June 7, 1989. TABLE OF CONTENTS 1.