AN ABSTRACT OF THE THESIS OF Licheng Zhang for the degree of Master of Science in Electrical and Computer Engineering presented on June 7, 1989. Title: The Design of A Reduced Instruction Set Computer UsingA Silicon Compiler. Redacted for Privacy Abstract appro ed- John Muff The objective of this thesisisto describe the design and implementation of a VSLI reduced instruction set computer(RISC). The RISC machine constitutes a new style of computerarchitecture. Itdifferssignificantly from the complex instructionset computer architectures(CISC)ofthepast.RISCarchitecturesare characterized by their high performance, simple instructionsets, minimal hardware requirements, and their abilityto support block structured programming languages adequately. In this thesis a 16-bit single chip RISC was designed using the Genesil Silicon Compiler. It has 14 instructions, anoverlapped register window structure,and on chip memory.Itcan execute most instructions in a single clock cycle,including procedure calls and returns. The peak performance of this chip is approximately6 MIPS. The chip was implemented in 2 micron CMOS technology. The chip sizeis 516.54 X 514.27 mils. This chip has not been fabricated. THE DESIGN OF A REDUCED INSTRUCTION SET COMPUTER USING A SILICON COMPLIER By Licheng Zhang A THESIS submittedto Oregon State University in partial fulfillment of the requirement for the degree of Master of Science Completed June 7, 1989 Commencement June,1990. APPROVED: Redacted for Privacy ssor of Electrical and Comp ter gineering in charge of major Redacted for Privacy Head of Department of Electrical and Computer Engineering Redacted for Privacy Dean of Gradua eSchool Date thesis is presented: June 7, 1989. TABLE OF CONTENTS 1. INTRODUCTION 1 2. REDUCED INSTRUCTION SET COMPUTER ARCHITECTURE 7 2.1.From CISC to RISC 7 2.2.Characteristics of RISC Architectures 10 2.3.Overlaped Register Windows and Overflow/Underflow Handling 12 3. DESIGN ENVIRONMENT AND METHODOLOGY 1 8 3.1.An Overview of the Genesil Silicon Compiler 1 8 3.2.Chip Design Methodology Using the Genesil Silicon Compiler 19 4. SYSTEM DESIGN AND IMPLEMENTATION 2 5 4.1.System Overview 2 5 4.2.Instruction Set Design 2 5 4.3.Instruction Format 2 5 4.4.Pipelining 3 0 4.5.DatapathImplementation 3 2 4.6.ControllerImplementation 3 8 4.6.1. The Instruction Register 3 8 4.6.2. The Instruction Decoder and Finite State Machine 41 4.6.3. Flags and Pointers 4 2 4.7.Memory 4 3 4.8.Chip Netlisting, Floorplanning, and Simulation 4 3 4.9.Chip Performance 4 8 5. CONCLUSIONS 51 6. BIBLIOGRAPHY 5 5 7. APPENDICES A. Views of Silicon Compiler Functional Blocks 5 6 B. Description of Decoder, FSM, ROM and RAM 7 0 C Test Program 8 8 D. Test Vectors and Test Results 9 2 E Chip Timing Analysis 105 TABLE OF FIGURES Figure Page 1.1.A Single Chip RISC Machine 2 2.1.Register Windows 15 2.2.Overlaped Register Windows 16 3.1.Genesil Design Hierarchy 20 3.2.Chip Hierarchy 24 4.1.System Block Diagram 26 4.2.InstructionSet 27 4.3.Instruction Format 29 4.4.Pipeline Timing 31 4.5.Datapath Block Diagram 33 4.6.Overlaped Register Window 36 4.7.Timing for Overflow and Underflow 37 4.8.Controller 39 4.9.InstructionRegister 40 4.10. Memory 44 4.11. Memory Map 45 4.12. History of the Implementation Process 46 4.13. Chip Floorplan 49 4.14. Chip Pinout 50 THE DESIGN OF A REDUCED INSTRUCTION SET COMPUTER USING A SILICON COMPLIER 1. INTRODUCTION. The reduced instruction set computer or "RISC" computer is a new styleof computer architecture which was developedinthe late 70's and early 80's. RISC computers possess a small, simple instructionset.All instructions have the same format, and can be executed efficiently. Due to their simplicity, they are ideally suited to VLSI implementation. RISC architectureshave become more popular over the years primarily due totheir high performance capabilities. This thesisdeals with the architecture and design of a single chip 16-bit RISC computer. Itissimilar to the RISC architecture originally conceived at the University of California, Berkeley [1].It implements 14 instructions and containsathree-busdatapath,a controller,aregisterfile,and on-chip RAM and ROM. The architecture block digram of thissingle chip RISCisshown in figure1.1. Until recently,the strategy used for making fast computers was to implement a complexinstruction set machine. Such complex instructionset computers or "CISC" computers wereintended to efficiently support high level languages, so that complexoperations couldbeachievedbyexecutingasingleinstruction,instead of 2 7 ALU RAM R Shifter 0 M R F Address PC Datapath aDecoder A Address Bus Control Signals Data Bus Decoder I R Control Signals Controller V V Address Control Bus Signals V Data Bus Fig. 1.1. A Single Chip RISC Machine 3 several simple instructions. Researchinthelate1970'sshowed that although CISC machines can execute complex operations in one instruction, overall system performance is not necessarily high as a result. A number of studies indicate that in CISC systems such as the DEC VAX, certain instructions such as the move, call subroutine, and conditional branch, are executed much more frequently than other instructions. This situation was found to be true over a wide range of user application programs. It was alsofound that some of the instructionsthat are executed most frequently are more time consuming to execute than other instructions of this class. These studiesshowedstatisticallythatsystem performancedepends more on efficiently executing the instructionswhich are executed most frequentlythaninhavinga wide repertoireof complex instructions. Additional reasons for re-examination of the CISC paradigm included problems associated with CISC implementation. Among theseproblemsarethefactthatindividual CISC instruction complexity varies widely. Itis therefore not possible to make all instructionsuseasingleword instructionformat.Multi-word instructionsrequire,bydefinition, additional memory access cycles. Fetching these additional instruction words from memory degrades system performance significantly. This fact, coupled with thewiderangeofpossibleinstructionformats,makesthe 4 instruction decoding process very complicated.Secondly, CISC machines require very complex controller hardware duetothe sheer volume of instructions. Typical CSIC machines contain 100- 300 multi-word instructions. In contrast, RISC machines typically include 30-70 single-word instructions. The wide range of possible instruction addressing modes found in CISC machines compounds the hardware problem to an even greater degree. CISC machines are also difficultto pipeline without incurring extraordinary chip area overhead penalties due to the specializedpipeline hardware required. The additionalhardware requiredin CISC machines increasesoverallchipareaandreducessystem performance. Finally,itis a time consuming, expensive, and error-prone process to develop CISC CPUs due to their sheer complexity [2]. Withtheseconsiderationsin mind,thenewRISC architectures were developed in late 70's and early 80's. The key motivationforthese RISC computer implementations stemmed from aferventbeliefthatsimpler VLSI-based RISC machines wouldyieldhigher performanceinmostapplicationcontexts. These RISC machines optimize the execution of simple, frequently usedinstructionsthroughtheuseofspecializedhardware mechanisms. In practice,the assumptions of the RISC pioneers have provencorrect. A large number of computing machines recently released and currently under development employ RISC architecturalprinciples. 5 Itis important to note that when building computer systems, current programming language structuresand available software developmenttechnologiesare a keyconsideration. At approximately the same timethat RISC hardware architectures werebeingintroducedintothemarketplace,programming languagecompilertechnologies becameavailablewhich were capable of transforming complex high level languageoperations intosimple RISC instructionsefficiently.These new compiler technologies were able to deal with the difficult compilationissues introduced bysuch highlypipelinedmachines. Thus,software development technologies came into existence simultaneouslywith the emerging RISC hardware architectures. The main functional characteristics of RISC computers are as follows: 1) RISC computers execute one instruction per clockcycle. This includes jump, call, and return instructions. 2) All instructions are the same size.All instructions have the same format. 3) Only certaininstructions(e.g.loadandsave)access memory.Allotherinstructionsperformregistertoregister operations. 4) Many RISC computerscontainhardwarefeaturesto optimizeblockstructuredprogramminglanguageexecution. 6 Examples include large register arrays and register windows for efficient subroutine (procedure) implementation. In order to design and implement a RISC computer ina reasonable amount of time with the minimum possible chip area, it was necessary to take advantageof the latest in computer-aided design technology. A commercial silicon compiler was usedfor this purpose. The silicon compiler is asoftware package which allows a designer to implement digital systems on silicon from well-defined parameterized building blocks contained in the compiler's library. The silicon compiler also provides the designer with the capability to functionally (logically) simulate theoperation of the resulting chip,establishthe chip's performance, and send the chip design file, via electronic mail, to a silicon foundry for fabrication. 7 2. REDUCED INSTRUCTION SET COMPUTER ARCHITECTURE. 2.1.