Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
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18-447 Computer Architecture Lecture 6: Multi-Cycle and Microprogrammed Microarchitectures
18-447 Computer Architecture Lecture 6: Multi-Cycle and Microprogrammed Microarchitectures Prof. Onur Mutlu Carnegie Mellon University Spring 2015, 1/28/2015 Agenda for Today & Next Few Lectures n Single-cycle Microarchitectures n Multi-cycle and Microprogrammed Microarchitectures n Pipelining n Issues in Pipelining: Control & Data Dependence Handling, State Maintenance and Recovery, … n Out-of-Order Execution n Issues in OoO Execution: Load-Store Handling, … 2 Reminder on Assignments n Lab 2 due next Friday (Feb 6) q Start early! n HW 1 due today n HW 2 out n Remember that all is for your benefit q Homeworks, especially so q All assignments can take time, but the goal is for you to learn very well 3 Lab 1 Grades 25 20 15 10 5 Number of Students 0 30 40 50 60 70 80 90 100 n Mean: 88.0 n Median: 96.0 n Standard Deviation: 16.9 4 Extra Credit for Lab Assignment 2 n Complete your normal (single-cycle) implementation first, and get it checked off in lab. n Then, implement the MIPS core using a microcoded approach similar to what we will discuss in class. n We are not specifying any particular details of the microcode format or the microarchitecture; you can be creative. n For the extra credit, the microcoded implementation should execute the same programs that your ordinary implementation does, and you should demo it by the normal lab deadline. n You will get maximum 4% of course grade n Document what you have done and demonstrate well 5 Readings for Today n P&P, Revised Appendix C q Microarchitecture of the LC-3b q Appendix A (LC-3b ISA) will be useful in following this n P&H, Appendix D q Mapping Control to Hardware n Optional q Maurice Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Manchester Univ. -
A 4.7 Million-Transistor CISC Microprocessor
Auriga2: A 4.7 Million-Transistor CISC Microprocessor J.P. Tual, M. Thill, C. Bernard, H.N. Nguyen F. Mottini, M. Moreau, P. Vallet Hardware Development Paris & Angers BULL S.A. 78340 Les Clayes-sous-Bois, FRANCE Tel: (+33)-1-30-80-7304 Fax: (+33)-1-30-80-7163 Mail: [email protected] Abstract- With the introduction of the high range version of parallel multi-processor architecture. It is used in a family of the DPS7000 mainframe family, Bull is providing a processor systems able to handle up to 24 such microprocessors, which integrates the DPS7000 CPU and first level of cache on capable to support 10 000 simultaneously connected users. one VLSI chip containing 4.7M transistors and using a 0.5 For the development of this complex circuit, a system level µm, 3Mlayers CMOS technology. This enhanced CPU has design methodology has been put in place, putting high been designed to provide a high integration, high performance emphasis on high-level verification issues. A lot of home- and low cost systems. Up to 24 such processors can be made CAD tools were developed, to meet the stringent integrated in a single system, enabling performance levels in performance/area constraints. In particular, an integrated the range of 850 TPC-A (Oracle) with about 12 000 Logic Synthesis and Formal Verification environment tool simultaneously active connections. The design methodology has been developed, to deal with complex circuitry issues involved massive use of formal verification and symbolic and to enable the designer to shorten the iteration loop layout techniques, enabling to reach first pass right silicon on between logical design and physical implementation of the several foundries. -
Embedded Multi-Core Processing for Networking
12 Embedded Multi-Core Processing for Networking Theofanis Orphanoudakis University of Peloponnese Tripoli, Greece [email protected] Stylianos Perissakis Intracom Telecom Athens, Greece [email protected] CONTENTS 12.1 Introduction ............................ 400 12.2 Overview of Proposed NPU Architectures ............ 403 12.2.1 Multi-Core Embedded Systems for Multi-Service Broadband Access and Multimedia Home Networks . 403 12.2.2 SoC Integration of Network Components and Examples of Commercial Access NPUs .............. 405 12.2.3 NPU Architectures for Core Network Nodes and High-Speed Networking and Switching ......... 407 12.3 Programmable Packet Processing Engines ............ 412 12.3.1 Parallelism ........................ 413 12.3.2 Multi-Threading Support ................ 418 12.3.3 Specialized Instruction Set Architectures ....... 421 12.4 Address Lookup and Packet Classification Engines ....... 422 12.4.1 Classification Techniques ................ 424 12.4.1.1 Trie-based Algorithms ............ 425 12.4.1.2 Hierarchical Intelligent Cuttings (HiCuts) . 425 12.4.2 Case Studies ....................... 426 12.5 Packet Buffering and Queue Management Engines ....... 431 399 400 Multi-Core Embedded Systems 12.5.1 Performance Issues ................... 433 12.5.1.1 External DRAMMemory Bottlenecks ... 433 12.5.1.2 Evaluation of Queue Management Functions: INTEL IXP1200 Case ................. 434 12.5.2 Design of Specialized Core for Implementation of Queue Management in Hardware ................ 435 12.5.2.1 Optimization Techniques .......... 439 12.5.2.2 Performance Evaluation of Hardware Queue Management Engine ............. 440 12.6 Scheduling Engines ......................... 442 12.6.1 Data Structures in Scheduling Architectures ..... 443 12.6.2 Task Scheduling ..................... 444 12.6.2.1 Load Balancing ................ 445 12.6.3 Traffic Scheduling ................... -
Visualization Assisted Hardware Configuration for Bioinformatics Algorithms Priyesh Dixit Advisors: Drs. K. R. Subramanian, A. Mukherjee, A
Visualization assisted hardware configuration for Bioinformatics algorithms Priyesh Dixit Advisors: Drs. K. R. Subramanian, A. Mukherjee, A. Ravindran May 2005 1 Special Thanks I would like to thank Dr. Subramanian for his faith in my abilities and for selecting me to do this project. I also thank Dr. Mukherjee and Dr. Ravindran for their patience and support throughout the year and making this project possible. Thanks to Josh Foster and Nalin Subramanian for help with the FLTK and VTK. And also I would like to especially thank Jong-Ho Byun for his all his help. 2 Table of Contents Chapter 1: Introduction...................................................................................................4 Chapter 2: Background...................................................................................................6 2.1 Bioinformatics.......................................................................................................6 2.2 Field Programmable Gate Arrays..........................................................................6 2.3 The Smith-Waterman algorithm............................................................................9 2.4 Visualization.......................................................................................................10 Chapter 3: System Description......................................................................................11 3.1 Overview.............................................................................................................11 3.2 Design flow.........................................................................................................12 -
Title: "Implementation of a PRRSV Strain Database" – NPB #04-118
Title: "Implementation of a PRRSV Strain Database" – NPB #04-118 Investigator: Kay S. Faaberg Institution: University of Minnesota Co-Investigators: James E. Collins, Ernest F. Retzel Date Received: August 1, 2006 Abstract: We describe the establishment of a PRRSV ORF5 database (http://prrsv.ahc.umn.edu/) in order to fulfill one objective of the PRRS Initiative of the National Pork Board. PRRSV ORF5 nucleotide sequence data, which is one key viral protein against which neutralizing antibodies are generated, was assembled from our diagnostic laboratory’s private collection of field samples. Searchable webpages were developed, such that any user can go from isolate sequence to generating alignments and phylogenetic dendograms that show nucleotide or amino acid relatedness to that input sequence with minimal steps. The database can be utilized for understanding PRRSV variation, epidemiological studies, and selection of vaccine candidates. We believe that this database will eventually be the only website in the world to obtain recent, as well as archival, and complete information that is critical to PRRS elimination. Introduction: This project was proposed to fulfill the stated directive of the PRRS Initiative to implement a National PRRSV Sequence Database. The organization that oversees the development, care and maintenance of the database is the Center for Computational Genomics and Bioinformatics at the University of Minnesota. The Center is not affiliated with any diagnostic laboratory or department, but is a fee-for-service facility that possesses high-throughput computational resources, and has developed databases for a number of nationwide initiatives. The database is now freely available to all PRRS researchers, veterinarians and producers for web-based queries concerning relationships to other sequences, RFLP analysis, year and state of isolation, and other related research-based endeavors. -
Biological Sequence Analysis
Biological Sequence Analysis CSEP 521: Applied Algorithms – Final Project Archie Russell (0638782), Jason Hogg (0641054) Introduction Background The schematic for every living organism is stored in long molecules known as chromosomes made of a substance known as DNA (deoxyribonucleic acid. Each cell in an organism has a complete copy of its DNA, also known as its genomewhich is conveniently modeled as a sequence of symbols (alternately referred to as nucleotides or bases) in the DNA alphabet {A,C,T,G}. In humans, and most mammals, this sequence is about 3 billion bases long. Through a process known as protein synthesis, instructions in our DNA, known as genes, are interpreted by machinery in our bodies and transformed first into intermediate molecules called RNA, and then into structures called proteins, which are the primary actors in living systems. These molecules can also be modeled as sequences of symbols. These genes determine core characteristics of the development of an organism, as well as its day-to-day operations. For example, the Hox1 gene family determines where limbs and other body parts will grow in a developing fetus, and defects in the BRCA1 gene are implicated in breast cancer. The rate of data acquisition has been immense. As of 2006, GenBank, the national public repository for sequence information, had accumulated over 130 billion bases of DNA and RNA sequence, a 200-fold increase over the 1996 total2. Over 10,000 species have at least one sequence in GenBank, and 50 species have at least 100,000 sequences3. Complete genome sequences, each roughly 3-gigabases in size, are available for human, mouse, rat, dog, cat, cow, chicken, elephant, chimpanzee, as well as many non-mammals. -
Introduction to Microcoded Implementation of a CPU Architecture
Introduction to Microcoded Implementation of a CPU Architecture N.S. Matloff, revised by D. Franklin January 30, 1999, revised March 2004 1 Microcoding Throughout the years, Microcoding has changed dramatically. The debate over simple computers vs complex computers once raged within the architecture community. In the end, the most popular microcoded computers survived for three reasons - marketshare, technological improvements, and the embracing of the principles used in simple computers. So the two eventually merged into one. To truly understand microcoding, one must understand why they were built, what they are, why they survived, and, finally, what they look like today. 1.1 Motivation Strictly speaking, the term architecture for a CPU refers only to \what the assembly language programmer" sees|the instruction set, addressing modes, and register set. For a given target architecture, i.e. the architecture we wish to build, various implementations are possible. We could have many different internal designs of the CPU chip, all of which produced the same effect, namely the same instruction set, addressing modes, etc. The different internal designs could then all be produced for the different models of that CPU, as in the familiar Intel case. The different models would have different speed capabilities, and probably different prices to the consumer. But the same machine languge program, say a .EXE file in the Intel/DOS case, would run on any CPU in the family. When desigining an instruction set architecture, there is a tradeoff between software and hardware. If you provide very few instructions, it takes more instructions to perform the same task, but the hardware can be very simple. -
A Characterization of Processor Performance in the VAX-1 L/780
A Characterization of Processor Performance in the VAX-1 l/780 Joel S. Emer Douglas W. Clark Digital Equipment Corp. Digital Equipment Corp. 77 Reed Road 295 Foster Street Hudson, MA 01749 Littleton, MA 01460 ABSTRACT effect of many architectural and implementation features. This paper reports the results of a study of VAX- llR80 processor performance using a novel hardware Prior related work includes studies of opcode monitoring technique. A micro-PC histogram frequency and other features of instruction- monitor was buiit for these measurements. It kee s a processing [lo. 11,15,161; some studies report timing count of the number of microcode cycles execute z( at Information as well [l, 4,121. each microcode location. Measurement ex eriments were performed on live timesharing wor i loads as After describing our methods and workloads in well as on synthetic workloads of several types. The Section 2, we will re ort the frequencies of various histogram counts allow the calculation of the processor events in 5 ections 3 and 4. Section 5 frequency of various architectural events, such as the resents the complete, detailed timing results, and frequency of different types of opcodes and operand !!Iection 6 concludes the paper. specifiers, as well as the frequency of some im lementation-s ecific events, such as translation bu h er misses. ?phe measurement technique also yields the amount of processing time spent, in various 2. DEFINITIONS AND METHODS activities, such as ordinary microcode computation, memory management, and processor stalls of 2.1 VAX-l l/780 Structure different kinds. This paper reports in detail the amount of time the “average’ VAX instruction The llf780 processor is composed of two major spends in these activities. -
Digital and System Design
Digital System Design — Use of Microcontroller RIVER PUBLISHERS SERIES IN SIGNAL, IMAGE & SPEECH PROCESSING Volume 2 Consulting Series Editors Prof. Shinsuke Hara Osaka City University Japan The Field of Interest are the theory and application of filtering, coding, trans- mitting, estimating, detecting, analyzing, recognizing, synthesizing, record- ing, and reproducing signals by digital or analog devices or techniques. The term “signal” includes audio, video, speech, image, communication, geophys- ical, sonar, radar, medical, musical, and other signals. • Signal Processing • Image Processing • Speech Processing For a list of other books in this series, see final page. Digital System Design — Use of Microcontroller Dawoud Shenouda Dawoud R. Peplow University of Kwa-Zulu Natal Aalborg Published, sold and distributed by: River Publishers PO box 1657 Algade 42 9000 Aalborg Denmark Tel.: +4536953197 EISBN: 978-87-93102-29-3 ISBN:978-87-92329-40-0 © 2010 River Publishers All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, mechanical, photocopying, recording or otherwise, without prior written permission of the publishers. Dedication To Nadia, Dalia, Dina and Peter D.S.D To Eleanor and Caitlin R.P. v This page intentionally left blank Preface Electronic circuit design is not a new activity; there have always been good designers who create good electronic circuits. For a long time, designers used discrete components to build first analogue and then digital systems. The main components for many years were: resistors, capacitors, inductors, transistors and so on. The primary concern of the designer was functionality however, once functionality has been met, the designer’s goal is then to enhance per- formance. -
An FPGA-Based Web Server for High Performance Biological Sequence Alignment
2009 NASA/ESA Conference on Adaptive Hardware and Systems An FPGA-Based Web Server for High Performance Biological Sequence Alignment Ying Liu1, Khaled Benkrid1, AbdSamad Benkrid2 and Server Kasap1 1Institute for Integrated Micro and Nano Systems, Joint Research Institute for Integrated Systems, School of Engineering, The University of Edinburgh, The King's Buildings, Mayfield Road, Edinburgh, EH9 3J, UK 2 The Queen’s University of Belfast, School of Electronics, Electrical Engineering and Computer Science, University Road, Belfast, BT7 1NN, Northern Ireland, UK (y.liu,k.benkrid)@ed.ac.uk Abstract algorithm [2], and the Smith-Waterman algorithm [3]. This paper presents the design and implementation of the The latter is the most commonly used DP algorithm FPGA-based web server for biological sequence which finds the most similar pair of sub-segments in a alignment. Central to this web-server is a set of highly pair of biological sequences. However, given that the parameterisable, scalable, and platform-independent computation complexity of such algorithms is quadratic FPGA cores for biological sequence alignment. The web with respect to the sequence lengths, heuristics, tailored to server consists of an HTML–based interface, a MySQL general purpose processors, are often introduced to reduce database which holds user queries and results, a set of the computation complexity and speed-up bio-sequence biological databases, a library of FPGA configurations, a database searching. The most commonly used heuristic host application servicing user requests, and an FPGA algorithm for pairwise sequence alignment, for instance, coprocessor for the acceleration of the sequence is the BLAST algorithm [4]. In general, however, the alignment operation. -
Eruca Sativa Mill.) Tomislav Cernava1†, Armin Erlacher1,3†, Jung Soh2, Christoph W
Cernava et al. Microbiome (2019) 7:13 https://doi.org/10.1186/s40168-019-0624-7 RESEARCH Open Access Enterobacteriaceae dominate the core microbiome and contribute to the resistome of arugula (Eruca sativa Mill.) Tomislav Cernava1†, Armin Erlacher1,3†, Jung Soh2, Christoph W. Sensen2,4, Martin Grube3 and Gabriele Berg1* Abstract Background: Arugula is a traditional medicinal plant and popular leafy green today. It is mainly consumed raw in the Western cuisine and known to contain various bioactive secondary metabolites. However, arugula has been also associated with high-profile outbreaks causing severe food-borne human diseases. A multiphasic approach integrating data from metagenomics, amplicon sequencing, and arugula-derived bacterial cultures was employed to understand the specificity of the indigenous microbiome and resistome of the edible plant parts. Results: Our results indicate that arugula is colonized by a diverse, plant habitat-specific microbiota. The indigenous phyllosphere bacterial community was shown to be dominated by Enterobacteriaceae, which are well-equipped with various antibiotic resistances. Unexpectedly, the prevalence of specific resistance mechanisms targeting therapeutic antibiotics (fluoroquinolone, chloramphenicol, phenicol, macrolide, aminocoumarin) was only surpassed by efflux pump assignments. Conclusions: Enterobacteria, being core microbiome members of arugula, have a substantial implication in the overall resistome. Detailed insights into the natural occurrence of antibiotic resistances in arugula-associated microorganisms showed that the plant is a hotspot for distinctive defense mechanisms. The specific functioning of microorganisms in this unusual ecosystem provides a unique model to study antibiotic resistances in an ecological context. Background (isothiocyanates) have also received scientific interest, as Plants are generally colonized by a vastly diverse micro- they might be involved in cancer prevention [31]. -
The Implementation of Prolog Via VAX 8600 Microcode ABSTRACT
The Implementation of Prolog via VAX 8600 Microcode Jeff Gee,Stephen W. Melvin, Yale N. Patt Computer Science Division University of California Berkeley, CA 94720 ABSTRACT VAX 8600 is a 32 bit computer designed with ECL macrocell arrays. Figure 1 shows a simplified block diagram of the 8600. We have implemented a high performance Prolog engine by The cycle time of the 8600 is 80 nanoseconds. directly executing in microcode the constructs of Warren’s Abstract Machine. The imulemention vehicle is the VAX 8600 computer. The VAX 8600 is a general purpose processor Vimal Address containing 8K words of writable control store. In our system, I each of the Warren Abstract Machine instructions is implemented as a VAX 8600 machine level instruction. Other Prolog built-ins are either implemented directly in microcode or executed by the general VAX instruction set. Initial results indicate that. our system is the fastest implementation of Prolog on a commercrally available general purpose processor. 1. Introduction Various models of execution have been investigated to attain the high performance execution of Prolog programs. Usually, Figure 1. Simplified Block Diagram of the VAX 8600 this involves compiling the Prolog program first into an intermediate form referred to as the Warren Abstract Machine (WAM) instruction set [l]. Execution of WAM instructions often follow one of two methods: they are executed directly by a The 8600 consists of six subprocessors: the EBOX. IBOX, special purpose processor, or they are software emulated via the FBOX. MBOX, Console. and UO adamer. Each of the seuarate machine language of a general purpose computer.