VME for Experiments Chairman: Junsei Chiba (KEK)
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
Risc I: a Reduced Instruction Set Vlsi Computer
RISC I: A REDUCED INSTRUCTION SET VLSI COMPUTER DAVID A. PATTERSON and CARLO H. SEQUIN Computer Science Division University of California Berkeley, California ABSTRACT to implement CISC is the best way to use this “scarce” resource. The Reduced Instruction Set Computer (RISC) Project investigates an alternatrve to the general trend toward computers wrth increasingly complex instruction sets: With a The above findings led to the Reduced Instruction Set proper set of instructions and a corresponding architectural Computer (RISC) Project. The purpose of the project is design, a machine wrth a high effective throughput can be to explore alternatives to the general trend toward achieved. The simplicity of the instruction set and addressing architectural complexity. The hypothesis is that by modes allows most Instructions to execute in a single machine cycle, and the srmplicity of each instruction guarantees a short reducing the instruction set, VLSI architecture can be cycle time. In addition, such a machine should have a much designed that uses the scarce resources more effectively shorter design trme. than CISC. We also expect this approach to reduce design time, the number of design errors, and the This paper presents the architecture of RISC I and its novel execution time of individual instructions. hardware support scheme for procedure call/return. Overlapprng sets of regrster banks that can pass parameters directly to subrouttnes are largely responsible for the excellent Our initial version of such a computer is called RISC I. performance of RISC I. Static and dynamtc comparisons To meet our goals of simplicity and effective single-chip between this new architecture and more traditional machines implementation, we placed the following “constraints” are given. -
Computer Architecture and Assembly Language
Computer Architecture and Assembly Language Gabriel Laskar EPITA 2015 License I Copyright c 2004-2005, ACU, Benoit Perrot I Copyright c 2004-2008, Alexandre Becoulet I Copyright c 2009-2013, Nicolas Pouillon I Copyright c 2014, Joël Porquet I Copyright c 2015, Gabriel Laskar Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with the Invariant Sections being just ‘‘Copying this document’’, no Front-Cover Texts, and no Back-Cover Texts. Introduction Part I Introduction Gabriel Laskar (EPITA) CAAL 2015 3 / 378 Introduction Problem definition 1: Introduction Problem definition Outline Gabriel Laskar (EPITA) CAAL 2015 4 / 378 Introduction Problem definition What are we trying to learn? Computer Architecture What is in the hardware? I A bit of history of computers, current machines I Concepts and conventions: processing, memory, communication, optimization How does a machine run code? I Program execution model I Memory mapping, OS support Gabriel Laskar (EPITA) CAAL 2015 5 / 378 Introduction Problem definition What are we trying to learn? Assembly Language How to “talk” with the machine directly? I Mechanisms involved I Assembly language structure and usage I Low-level assembly language features I C inline assembly Gabriel Laskar (EPITA) CAAL 2015 6 / 378 I Programmers I Wise managers Introduction Problem definition Who do I talk to? I System gurus I Low-level enthusiasts Gabriel Laskar (EPITA) CAAL -
MIPS Assembly Language Programming Using Qtspim
MIPS Assembly Language Programming using QtSpim Ed Jorgensen, Ph.D. Version 1.1.50 July 2019 Cover image: MIPS R3000 Custom Chip http://commons.wikimedia.org/wiki/File:RCP-NUS_01.jpg Spim is copyrighted by James Larus and distributed under a BSD license. Copyright (c) 1990-2011, James R. Larus. All rights reserved. Copyright © 2013, 2014, 2015, 2016, 2017 by Ed Jorgensen You are free: To Share — to copy, distribute and transmit the work To Remix — to adapt the work Under the following conditions: Attribution — you must attribute the work in the manner specified by the author or licensor (but not in any way that suggests that they endorse you or your use of the work). Noncommercial — you may not use this work for commercial purposes. Share Alike — if you alter, transform, or build upon this work, you may distribute the resulting work only under the same or similar license to this one. Table of Contents 1.0 Introduction...........................................................................................................1 1.1 Additional References.........................................................................................1 2.0 MIPS Architecture Overview..............................................................................3 2.1 Architecture Overview........................................................................................3 2.2 Data Types/Sizes.................................................................................................4 2.3 Memory...............................................................................................................4 -
Design of the RISC-V Instruction Set Architecture
Design of the RISC-V Instruction Set Architecture Andrew Waterman Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2016-1 http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.html January 3, 2016 Copyright © 2016, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley Committee in charge: Professor David Patterson, Chair Professor Krste Asanovi´c Associate Professor Per-Olof Persson Spring 2016 Design of the RISC-V Instruction Set Architecture Copyright 2016 by Andrew Shell Waterman 1 Abstract Design of the RISC-V Instruction Set Architecture by Andrew Shell Waterman Doctor of Philosophy in Computer Science University of California, Berkeley Professor David Patterson, Chair The hardware-software interface, embodied in the instruction set architecture (ISA), is arguably the most important interface in a computer system. Yet, in contrast to nearly all other interfaces in a modern computer system, all commercially popular ISAs are proprietary. -
Sony's Α5100 Is the World's Smallest Interchangeable
For Immediate Release For further information: Christine Law, 02 8353 5795 [email protected] Hausmann Communications Laura Hunter, 02 8873 9218 [email protected] Sony Australia Ltd Sharper shooting: Sony’s α5100 is the world’s smallest interchangeable lens camera with super-fast autofocus and pro quality pictures Fast Hybrid AF with widely-covered 179 focal plane phase-detection AF points for reliable tracking autofocus plus touch focusing and touch shutter release Large, high-sensitivity 24.3 megapixel APS-C size Exmor CMOS sensor and powerful BIONZ X processor for superb image quality Shoot cinematic Full HD movies with Fast Hybrid AF tracking Perfect selfie with 180° tiltable touch enabled LCD Monitor and Soft Skin Effect Expand your shooting fun with a host of downloadable PlayMemories Camera Apps to expand your creative possibilities One-touch image and movie sharing with Wi-Fi/NFC Sydney, 18 August 2014 – Sony claims another world’s best with the announcement of the α5100, the world’s smallest[1] interchangeable lens camera. The pocket-sized α5100 joins the α7 series, α5000 and α6000 in Sony’s growing stable of compact, power-packed interchangeable lens cameras. Fitting snugly in your hand, the α5100 boasts a big APS-C sensor plus a built-in flash and Wi-Fi. Despite its compact dimensions, it’s every inch the serious choice for anyone who’s moving up from their smartphone’s camera or point-and-shoot compact snapper. [1] Among interchangeable-lens digital cameras equipped with an APS-C equivalent image sensor, built-in flash and Wi-Fi as of August 2014, based on Sony research. -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
STD 7000 7802 6800 Processor Card USER's MANUAL
STD 7000 7802 6800 Processor Card USER'S MANUAL .: . o o NOTICE The information in this document is provided for reference only. Pro-Log does not assume any liability arising 0 out of the application or use of the information or products described herein. This document may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of Pro-Log, nor the rights of others. Printed in U.S.A. Copyright© 1981 by Pro-Log Corporation, Monterey, CA 93940. All rights reserved. However, any part of this document may be reproduced with Pro-Log Corporation cited as the source. STD 7000 7802 6800 Processor Card USER'S MANUAL o 2/82 aa uailUIlAIMIMIlIdIHI6IJYIWiiIIi&&iIlWiHiiiii1WGL&lil1l4JI£jj1, __ oGllI{fldf4IL1lfI[.JIilJI!1U1l4J!;;QI!IMf&bnUMliMJi1illldOif kLCH1LJ _"- _,L JLJ L _11 ____ ,BAGLin _ ta, _ h 'h41J1P i4I A;.u 4 FOREWORD This manual explains how to use Pro-Log's 7802 6800 Processor Card. It is structured to reflect the answers to o basic questions that you, the user, might ask yourself about the 7802. We welcome your suggestions on how we can improve our instructions. The 7802 is part of Pro-Log's Series 7000 STD BUS hardware. Our products are modular, and they are designed and built with second-sourced parts that are industry standards. They provide the industrial manager with the means of utilizing his own people to control the design, production, and maintenance of the company's products that use STD BUS hardware. -
The Political Economy of Independent Film: a Case Study of Kevin Smith Films
Florida State University Libraries Electronic Theses, Treatises and Dissertations The Graduate School 2009 The Political Economy of Independent Films: A Case Study of Kevin Smith Films Grace Kathleen Keenan Follow this and additional works at the FSU Digital Library. For more information, please contact [email protected] FLORIDA STATE UNIVERSITY COLLEGE OF COMMUNICATION THE POLITICAL ECONOMY OF INDEPENDENT FILMS: A CASE STUDY OF KEVIN SMITH FILMS By GRACE KATHLEEN KEENAN A Thesis submitted to the Department of Communication in partial fulfillment of the requirements for the degree of Master of Arts in Media Degree Awarded: Spring Semester, 2009 The members of the Committee approve the Thesis of Grace Kathleen Keenan defended on April 9, 2009. ____________________________________ Jennifer M. Proffitt Professor Directing Thesis ____________________________________ Stephen D. McDowell Committee Member ____________________________________ Andrew Opel Committee Member __________________________________________________ Stephen D. McDowell, Chair, Department of Communication __________________________________________________ Gary R. Heald, Interim Dean, College of Communication The Graduate School has verified and approved the above named committee members. ii For my parents, who have always seen me as their shining star iii ACKNOWLEGEMENTS Dr. Proffitt: Without your dedication to learning and students, this thesis would have been impossible. You truly have the patience of an angel. Much love. Dad: How do you put up with me? Thank you for all your emotional and financial support. Mom: You are always striving to understand. I think I get that from you. Newton Hazelbaker: Again, how do you put up with me? Thank you for your absolute and unconditional love. Laura Clements: Perhaps the most fun person I’ve ever met. -
Ultrasparc Architecture 2007
UltraSPARC Architecture 2007 One Architecture ... Multiple Innovative Implementations Draft D0.9.4, 27 Sep 2010 Privilege Levels: Hyperprivileged, Privileged, and Nonprivileged Distribution: Public Part No.No: 950-5554-15 ReleaseRevision: 1.0, Draft 2002 D0.9.4, 27 Sep 2010 Oracle Corporation 4150 Network Circle Santa Clara, CA 95054 U.S.A. 650-960-1300 ii UltraSPARC Architecture 2007 • Draft D0.9.4, 27 Sep 2010 Copyright © 2007, 2011, Oracle and/or its affiliates. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective owners. AMD, Opteron, the AMD logo, and the AMD Opteron logo are trademarks or registered trademarks of Advanced Micro Devices. Intel and Intel Xeon are trademarks or registered trademarks of Intel Corporation. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. UNIX is a registered trademark licensed through X/Open Company, Ltd.. Comments and "bug reports” regarding this document are welcome; they should be submitted to email address: [email protected] iv UltraSPARC Architecture 2007 • Draft D0.9.4, 27 Sep 2010 Contents Preface. i 1 Document Overview . 1 1.1 Navigating UltraSPARC Architecture 2007 . 1 1.2 Fonts and Notational Conventions . 2 1.2.1 Implementation Dependencies . 3 1.2.2 Notation for Numbers. 3 1.2.3 Informational Notes . 3 1.3 Reporting Errors in this Specification . 4 2 Definitions . 5 3 Architecture Overview. 15 3.1 The UltraSPARC Architecture 2007. 15 3.1.1 Features. 15 3.1.2 Attributes . 16 3.1.2.1 Design Goals . -
Stand-Alone VME Bus PC104 Bus ISA Bus STD Bus, & STD32
SYNCHRO / RESOLVER / LVDT CONVERTERS / BUS CARDS / AMPLIFIERS ABSOLUTE ENCODERS / READOUTS www.computerconversions.com 6 Dunton Court, East Northport, NY 11731 (631) 261-3300 Fax: (631) 261-3308 BUS CARD LEVEL PRODUCTS: SYNCHRO / RESOLVER / LVDT I/O VME Bus PC104 Bus Synchro / Resolver / LVDT I/O Synchro / Resolver / LVDT I/O Inputs: 1 - 12 Channels Synchro / Inputs: 1 - 4 Channels Synchro / Resolver, & 2-3 Wire LVDT Formats, Resolver and LVDT inputs with B-I-T & Forced Angle Self-Test Mods., B-I-T and Forced angle Self-Test, VBT True Wrap-Around Self-Test. Transformer Isolation opt.even on To 16 Bits, acc. 2', Tracking Rates to 60Hz. 200RPS. On-Board AC Reference Models., 16 Bits, 2.'acc.Tracking Rates options, Low cost Solid State and to 200RPS. Ultra Reliable and quick 100% Transformer Isolated models. delivery. AC Reference Supply Outputs: LVDT/ RVDT 1-12 Chan.s options. Synchro/Resolver: 1-4 Channels, high Outputs: 1-2 Channels Synchro / Res. power, output, drive 1.2 to 5VA, Low Low cost & Isol. mod's. 16 Bits, 1 - 4' Cost +/-12V. DC Bus powered & Reference acc. Loss detect, support for external Powered Converters. Transformer Isol ated Boosters upto 300VA. including I/O. Resolution: 14/16 Bits, accuracy 2'/ 4'. Disable control & BIT / Fault Report. All: A24/D16 6UH. Multispeed I/O, & All: No Violations, 0 - 70 and -40 - Mix & Match all I/O. 0 - 70 & -40 to +85C. +85C models. Software Demo w/ Conduction Cooled avail. PCI &COMPACT PCI ISA Bus All Plug and Play, with Software DLL's, PCI Same Selections 1-8 Inputs, Upto 4 High Power Output Channels, Transformer as on ISA Bus, CPCI Same Selections as on VME Bus. -
Processor Architectures
CS143 Handout 18 Summer 2008 30 July, 2008 Processor Architectures Handout written by Maggie Johnson and revised by Julie Zelenski. Architecture Vocabulary Let’s review a few relevant hardware definitions: register: a storage location directly on the CPU, used for temporary storage of small amounts of data during processing. memory: an array of randomly accessible memory bytes each identified by a unique address. Flat memory models, segmented memory models, and hybrid models exist which are distinguished by the way locations are referenced and potentially divided into sections. instruction set: the set of instructions that are interpreted directly in the hardware by the CPU. These instructions are encoded as bit strings in memory and are fetched and executed one by one by the processor. They perform primitive operations such as "add 2 to register i1", "store contents of o6 into memory location 0xFF32A228", etc. Instructions consist of an operation code (opcode) e.g., load, store, add, etc., and one or more operand addresses. CISC: Complex instruction set computer. Older processors fit into the CISC family, which means they have a large and fancy instruction set. In addition to a set of common operations, the instruction set has special purpose instructions that are designed for limited situations. CISC processors tend to have a slower clock cycle, but accomplish more in each cycle because of the sophisticated instructions. In writing an effective compiler back-end for a CISC processor, many issues revolve around recognizing how to make effective use of the specialized instructions. RISC: Reduced instruction set computer. Many modern processors are in the RISC family, which means they have a relatively lean instruction set, containing mostly simple, general-purpose instructions. -
Keeping Old Computers Alive for Deeper Understanding of Computer Architecture
Keeping Old Computers Alive for Deeper Understanding of Computer Architecture Hisanobu Tomari Kei Hiraki Grad. School of Information Grad. School of Information Science and Technology, Science and Technology, The University of Tokyo The University of Tokyo Tokyo, Japan Tokyo, Japan [email protected] [email protected] Abstract—Computer architectures, as they are seen by stu- computers retrospectively. Working hardware is a requisite for dents, are getting more and more monolithic: few years ago a software execution environment that reproduces behavior of student had access to x86 processor on his or her laptop, SPARC socially and culturally important computers. server in the backyard, MIPS and PowerPC on large SMP system, and Alpha on calculation server. Today, only architectures that This paper presents our information science undergraduate students experience writing program on are x86 64 and possibly course for teaching concepts and methodology of computer ARM. On one hand, this simplifies their learning, but on the architecture. In this class, historic computer systems are used other hand, this makes it harder to discover options that are by students to learn different design concepts and perfor- available in designing an instruction set architecture. mance results. Students learn the different instruction sets In this paper, we introduce our undergraduate course that teaches computer architecture design and evaluation that uses by programming on a number of working systems. This historic computers to make more processor architectures acces- gives them an opportunity to learn what characteristics are sible to students. The collection of more than 270 old computers shared among popular instruction set, and what are special that were marketed in 1979 to 2014 are used in the class.