DOCSLIB.ORG

Microsparc-II-Usersm

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Microsparc-II-Usersm Products Rights Notice: Copyright © 1991-2008 Sun Microsystems, Inc. 4150 Network Circle, Santa Clara, California 95054, U.S.A. All Rights Reserved You understand that these materials were not prepared for public release and you assume all risks in using these materials. These risks include, but are not limited to errors, inaccuracies, incompleteness and the possibility that these materials infringe or misappropriate the intellectual property right of others. You agree to assume all such risks. THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND OTHER CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS (INCLUDING ANY OF OWNER'S PARTNERS, VENDORS AND LICENSORS) BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Sun, Sun Microsystems, the Sun logo, Solaris, OpenSPARC T1, OpenSPARC T2 and UltraSPARC are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the U.S. and other countries. Products bearing SPARC trademarks are based upon architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the U.S. and other countries, exclusively licensed through X/Open Company, Ltd. The Adobe logo is a registered trademark of Adobe Systems, Incorporated. Part of the products covered by these materials may be derived from the Berkeley BSD systems licensed by the University of California. Sun Microsystems, Inc. has intellectual property rights relating to technology embodied in the product described in these materials. This distribution may include materials developed by third parties who have intellectual property rights therein. Products covered by and information contained in these materials may be controlled by U.S. Export Control laws and may be subject to the export or import laws in other countries. Nuclear, missile, chemical biological weapons or nuclear maritime end uses or end users, whether direct or indirect, are strictly prohibited. Export or reexport to countries subject to U.S. embargo or to entities identified on U.S. export exclusion lists, including, but not limited to, the denied persons and specially designated nationals lists may be prohibited. microSPARC-I1 User's Manual 3 Table of Contents Chapter 1: microSPARC-I1 Overview ...................................................15 1.1: Introduction .........................................................................................15 1.2. Key differences between microSPARC-I1 and microSPARC ............15 1.2.1: Overall .....................................................................................-15 1.2.2. IU: .............................................................................................15 1.2.3. FPU: ..........................................................................................16 1.2.4. Instruction Cache: ....................................................................-16 1.2.5. Data Cache: ...............................................................................16 1.2.6. MMU: .......................................................................................16 1.2.7. MEMIF: .................................................................................... 16 1.2.8. SBC: .........................................................................................17 1.2.9. Jtag operation ............................................................................ 17 1.3. microSPARC-I1 Memory Map ...........................................................17 1.4. Block diagram .................................................................................... 18 Chapter 2: CPU Performance ................................................................. 21 2.1 : Compiler Optimization Guidelines .................................................... 24 2.1.1 : Branches ................................................................................... 24 2.1.2. Guidelines for Branch Folding ................................................25 2.1.3. Multicycle Instructions ............................................................27 2.1.4. Interlocks .................................................................................27 2.1.5. Ocher Guidelines ......................................................................27 2.1.6. Floating Point ...........................................................................27 2.1.7. Loads and Stores .......................................................................30 2.1.8. General Techniques ................................................................-31 2.2: Improved microSPARC-I1 Performance using the 2 page hit registers31 Chapter 3: Integer Unit ...........................................................................33 3.1 : Overview ............................................................................................ 33 3.2. Instruction Pipeline ............................................................................ 35 3.3. Memory Operations ........................................................................... 36 3.3.1. Loads ........................................................................................ 36 3.3.2. Stores ....................................................................................... 37 3.3.3. Atomics .................................................................................... 38 3.4. ALUJShift Operations ........................................................................ 39 3.5. Integer Multiply ................................................................................. 40 3.6. Integer Divide .................................................................................... 40 3.7. CTI's .................................................................................................. 41 3.7.1. Branches ................................................................................... 41 3.7.2. JMPL ........................................................................................ 42 3.7.3. RETT ....................................................................................... 42 3.7.4. CALL ....................................................................................... 42 Sun Microsystems Rev 1. 1 July 1994 4 microSPARC-I1 User's Manual 3.8. Instruction Cache Interface ................................................................43 3.9. Data Cache Interface ..........................................................................43 3.10. Interlocks ........................................................................................-43 3.10.1. Load Interlock ........................................................................43 3.10.2. Floatingpoint Interlocks .....................................................44 3.10.3. Miscellaneous Interlocks .......................................................44 3.1 1: Traps and Interrupts .........................................................................44 3.11.1. Traps ......................................................................................44 3.1 1.2. Interrupts ................................................................................ 45 3.1 1.3. Reset Trap ..............................................................................46 3.1 1.4. Error Mode .............................................................................46 3.12. Floating Point Interface ....................................................................46 3.13 : Special Features ............................................................................... 47 3.14. Compliance with SPARC version 8 ................................................ 48 Chapter 4: Floating Point Unit ...............................................................49 4.1 : Overview ............................................................................................. 49 4.2. FPU Internal Information .................................................................... 54 4.3. Deviations from SPARC V8 ...............................................................56 4.4. Implementation Specific Features ..................................................... 57 4.5. Software Considerations ....................................................................58 4.6. FP Performance Factors ......................................................................60 Chapter 5: Memory Management Unit .................................................63 5.1: Overview ............................................................................................ 63 5.2. Translation Lookaside Buffer ............................................................. 65 5.2.1: TLB Replacement ....................................................................65 5.2.2. TLB Entry ................................................................................ -66 5.2.3.
Load more

Recommended publications
  • Sun Fire E2900 Server
    Sun FireTM E2900 Server Just the Facts February 2005 SunWin token 401325 Sun Confidential – Internal Use Only Just The Facts Sun Fire E2900 Server Copyrights ©2005 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Sun Fire, Netra, Ultra, UltraComputing, Sun Enterprise, Sun Enterprise Ultra, Starfire, Solaris, Sun WebServer, OpenBoot, Solaris Web Start Wizards, Solstice, Solstice AdminSuite, Solaris Management Console, SEAM, SunScreen, Solstice DiskSuite, Solstice Backup, Sun StorEdge, Sun StorEdge LibMON, Solstice Site Manager, Solstice Domain Manager, Solaris Resource Manager, ShowMe, ShowMe How, SunVTS, Solstice Enterprise Agents, Solstice Enterprise Manager, Java, ShowMe TV, Solstice TMNscript, SunLink, Solstice SunNet Manager, Solstice Cooperative Consoles, Solstice TMNscript Toolkit, Solstice TMNscript Runtime, SunScreen EFS, PGX, PGX32, SunSpectrum, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunStart, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. All other product or service names mentioned
    [Show full text]
  • Memory Profiling on Shared-Memory Multiprocessors
    MEMORY PROFILING ON SHARED-MEMORY MULTIPROCESSORS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Jeffrey S. Gibson June 2004 c Copyright by Jeffrey S. Gibson 2004 All Rights Reserved ii I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Dr. John Hennessy (Principal Advisor) I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Dr. Mark Horowitz I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and quality, as a dissertation for the degree of Doctor of Philosophy. Dr. Mendel Rosenblum Approved for the University Committee on Graduate Studies: iii Abstract Tuning application memory performance can be difficult on any system but is particularly so on distributed shared-memory (DSM) multiprocessors. This is due to the implicit nature of communication, the unforeseen interactions among the processors, and the long remote memory latencies. Tools, called memory profilers, that allow the user to map memory behavior back to application data structures can be invaluable aids to the programmer. Un- fortunately, memory profiling is difficult to implement efficiently since most systems lack the requisite hardware support. This dissertation introduces two techniques for efficient memory profiling, each requiring hardware support on either the processor or the system node controller.
    [Show full text]
  • The Supersparc Microprocessor
    The SuperSPARC™ Microprocessor Technical White Paper 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. © 1992 Sun Microsystems, Inc.—Printed in the United States of America. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A All rights reserved. This product and related documentation is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® and Berkeley 4.3 BSD systems, licensed from UNIX Systems Laboratories, Inc. and the University of California, respectively. Third party font software in this product is protected by copyright and licensed from Sun’s Font Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, are trademarks or registered trademarks of Sun Microsystems, Inc. UNIX and OPEN LOOK are registered trademarks of UNIX System Laboratories, Inc. All other product names mentioned herein are the trademarks of their respective owners. All SPARC trademarks, including the SCD Compliant Logo, are trademarks or registered trademarks of SPARC International, Inc. SPARCstation, SPARCserver, SPARCengine, SPARCworks, and SPARCompiler are licensed exclusively to Sun Microsystems, Inc.
    [Show full text]
  • Microsparc™-Iiep
    Preliminary STP1100BGA December 1997 microSPARC™-IIep DATA SHEET SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces DESCRIPTION The microSPARC-IIep 32-bit microprocessor is a highly integrated, high-performance microprocessor. Imple- menting the SPARC Architecture version 8 specification, it is ideally suited for low-cost uniprocessor embedded applications. It is built with leading edge CMOS technology, with the core operating at a low voltage of 3.3V for optimized power consumption. The microSPARC-IIep includes on chip: integer unit (IU), floating-point unit (FPU), large separate instruction and data caches, a 32-entry version 8 reference MMU, programmable DRAM controller, PCI controller, PCI bus interface, a 16-entry IOMMU, flash memory interface support, interrupt controller, 2 timers, internal and boundary scan through JTAG interface, power management and clock generation capabilities. The operating frequencies are 100 MHz. Features Benefits • Integrated 32-bit, 33 MHz PCI expansion bus controller • Connection to industry-standard expansion bus • Integrated 256 MByte DRAM controller • High-bandwidth memory controller to reduce latency • Built-in 16 MByte flash memory controller • Flash memory interface runs real-time operating systems that loads and runs code out of ROM • SPARC high-performance RISC architecture • Compatible with over 10,000 applications and existing development tools • Support for little and big endian byte ordering • Handles with ease PCI devices designed for DOS machines, along with UNIX® applications • 8-window,
    [Show full text]
  • SPARC Assembly Language Reference Manual
    SPARC Assembly Language Reference Manual 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. A Sun Microsystems, Inc. Business 1995 Sun Microsystems, Inc. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system, licensed from UNIX Systems Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun’s Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, SunSoft, the SunSoft logo, Solaris, SunOS, OpenWindows, DeskSet, ONC, ONC+, and NFS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. OPEN LOOK is a registered trademark of Novell, Inc.
    [Show full text]
  • Deliveringperformanceonsun:Optimizing Applicationsforsolaris
    DeliveringPerformanceonSun:Optimizing ApplicationsforSolaris TechnicalWhitePaper 1997-1999 Sun Microsystems, Inc. 901 San Antonio Road, Palo Alto, California 94303 U.S.A All rights reserved. This product and related documentation is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® and Berkeley 4.3 BSD systems, licensed from UNIX Systems Laboratories, Inc. and the University of California, respectively. Third party font software in this product is protected by copyright and licensed from Sun’s Font Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, Sun WorkShop, and Sun Enterprise are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. UltraSPARC, SPARCompiler, SPARCstation, SPARCserver, microSPARC, and SuperSPARC are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. All other product names mentioned herein are the trademarks of their respective owners. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc.
    [Show full text]
  • Sparcstation 4 Model 110 Service Manual
    SPARCstation 4 Model 110 Service Manual Sun Microsystems Computer Company A Sun Microsystems, Inc. Business 901 San Antonio Road Palo Alto, CA 94303-4900 USA 650 960-1300 fax 650 969-9131 Part No.: 802-6464-10 Revision A, July 1996 1997 Sun Microsystems, Inc., 901 San Antonio Road, Palo Alto, California 94303-4900 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system, licensed from Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. UNIX is a registered trademark in the United States and in other countries and is exclusively licensed by X/Open Company Ltd. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun’s suppliers. RESTRICTED RIGHTS: Use, duplication, or disclosure by the U.S. Government is subject to restrictions of FAR 52.227-14(g)(2)(6/87) and FAR 52.227-19(6/87), or DFAR 252.227-7015(b)(6/95) and DFAR 227.7202-3(a). Sun, Sun Microsystems, the Sun logo, and Solaris are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and in other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc.
    [Show full text]
  • Washington Apple Pi Journal, February 1986
    $ 2 50 Wa/hington Apple Pi The Journal of WashingtonG Apple Pi, Ltd. Volume.. 8 Februar lLl1986 number 2 Hiahliahtl- - Best (III) Picks in '86 Quad Thermometer 'EXCEL'ing With Your Mac HFS Follies New Apple Announcements In This Issue... Officers &Staff, Editorial •• • •• 3 Quad Thermometer ••• •• •••• Tom Riley 25 " President's Corner • Tom Warrick 4 "Print Using" for Forth . •• • Chester H. Page 32 Event Queue, General Information 5 Program Selector Review . • • • • • Barry Fox 34 New Meeting Format • ••••• 6 Pascal & Modula-2 Implementations . Robert C. Platt 36 WAP Calendar, SigNews • 7 Softviews. • • • • Oavid Morganstein 38 WAP Hotline . • ••••••••• 8 The View From Durham • • •• • Chris Klugewicz 40 December Meet ing Report • • • • Adrien Youell 9 Frede r ick Apple Core • • • • 43 EDSIG News ••• • •• Peter Combes 9 Mac i ntosh & Scientific Environment.Lynn R. Trusal 43 WAP Bulletin Board Systems. • • •• •• 9 Macintosh in the News, Etc . • Lynn R. Trusal 44 Q &A • •• • •• • • ••• • • Bruce F. Field 10 The New Mac - Is It an NBI? •• Lynn R. Trusal 45 Classifieds, Commercial Classifieds, Job Mart •• 12 Book Reviews •• • • •• Robert C. Platt 46 Letter to the Editor •• • • • •• ••• 12 Computer Mail as Entertainment •• Bro . Tom Sawyer 47 The Best (III) Picks in '86 • • • David Ottal i ni 14 Mac Q &A . •••• • •• • Jonathan E. Hardis 48 GAMESIG News ••• • ••••••• Barry Bedrick 16 OverVUE 2.0: Problem & Solution •• James J . Derhaag 51 Enchanted Scepters:A Review • • • Barry & Ben Bedrick 17 MacNo vice • • • • •• • • Ralph J. Begleiter 52 Mindwheel : A Review . ••• • • Steven Payne 17 'EXCEL'ing With Your Mac ••• David Morganstein 54 Playing "Time Zone" Steven Payne 18 Excel Power: Manipulating Cells .. Tom Warrick 56 Wildnerness: A Review Beryl Swarztrauber 18 HFS Follies •• • •••••• Tom Warrick 58 Baron: A Review .
    [Show full text]
  • Sun-4 Handbook - Home Page
    Sun-4 Handbook - Home Page Sun Internal ONLY !! The Sun-4 Handbook describes and illustrates the Sun-4 and Sun-4e products for service providers who service these products after the End of Support Life in April 1997. End of Support Life is the end of Sun's commitment to support the product. Sun may help customers locate alternative sources for support on a case-by-case basis if ongoing support is needed beyond 5 years. Spares availability after End of Support Life may be limited and repair service will be at Sun's discretion. http://lios.apana.org.au/~cdewick/sunshack/data/feh/1.4/wcd00000/wcd00036.htm (1 von 2) [25.04.2002 15:56:23] Sun-4 Handbook - Home Page [ Configurations ] [ CPU ] [ Memory ] [ Graphics ] [ IPI ] [ SCSI ] [ SCSI Disk ] [ Removable Media ] [ Communication ] [ Miscellaneous ] [ Backplane ] [ Slot Assignment ] [ Parts Introduction ] [ System ] [ Disk Options ] [ Removable Media Options ] [ Miscellaneous Options ] [ Board ] [ Input Device ] [ Monitor ] [ Printer ] [ CPU Trouble ] [ Disk Trouble ] [ Diagnostics ] [ Power Introduction ] [ AC Power ] [ DC Power ] The original hardcopy publication of the Sun-4 Handbook is part number 805-3028-01. © 1987-1999, Sun Microsystems Inc. http://lios.apana.org.au/~cdewick/sunshack/data/feh/1.4/wcd00000/wcd00036.htm (2 von 2) [25.04.2002 15:56:23] Sun4/II: DC Power - Contents DC Power Power Supplies 300-1020 -- Brown -- 575 Watts 300-1020 -- Fuji -- 575 Watts 300-1022 -- Summit -- 325 Watts 300-1022 -- Brown -- 325 Watts 300-1024 -- Fuji -- 850 Watts 300-1031 -- Delta -- 120 Watts
    [Show full text]
  • Table of Contents
    1 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. Safe Harbor Statement The following is intended to outline our general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle’s products remains at the sole discretion of Oracle. 2 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. Eine phatastische Reise ins Innere der Hardware Franz Haberhauer Stefan Hinker Oracle Hardware in 3D 5 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. T5 and M5 PCIe Carrier Card . Supports standard low-profile PCIe cards Air Flow PCIe Retimer x16 Connector (x8 electrical) 6 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. PCIe Data Paths: Full System . Two root complexes per T5 processor . Each PCIe port on a T5 processor controls a single PCIe slot 7 Copyright © 2013, Oracle and/or its affiliates. All rights reserved. T5-2 Block Diagram DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM DIMM BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB BoB T5-0 T5-1 CPU CPU TPM Host & CPU PCIe Debug CPU PCIe Debug Data Flash DC/DCs 0 1 Port DC/DCs 0 1 Port x8 x8 FPGA x8 x4 x8 x1 HDD0 DBG SAS/SATA x1 HDD0 IO Controller x4 x4 PCIe PCIe SP Module HDD0 get rid of all inside x8 x8 SAS/SATA smallSwitch boxes 0 Switch 1 FRUID HDD0 IO Controller Sideband Mgmt DRAM HDD0 USB 1.1 Keyboard Mouse Service SPI x8 USB 3.0 x8 USB 2.0 Storage Flash HDD0 Host Processor SATA DVD NAND USB 2.0 Hub USB USB 3.0 USB Internal USB Hub VGA VGA REAR IO Board USB2 USB3 VGA USB0 USB1 VGA Serial Enet Quad 10Gig Enet DB15 Mgmt Mgmt Slot 2 (8) 2 Slot (8) 3 Slot (8) 4 Slot (8) 5 Slot (8) 6 Slot (8) 7 Slot (8) 8 Slot Slot 1 (8) 1 Slot 10/100 FAN BOARD REAR IO 8 Copyright © 2013, Oracle and/or its affiliates.
    [Show full text]
  • High-Performance Workstation at an Entry-Level Price
    SPARCstation™ 5 High-performance workstation at an entry-level price. With its high-speed 170 MHz TurboSPARC chip, the SPARCstation™ 5 delivers enough horsepower to make even your most CPU-intensive applications run the way they’re supposed to — fast. With multiple configurations to choose from, workstation. The Model 170 provides a low you’re sure to find a SPARCstation 5 system that cost solution for developing Java™ applets as well suitstheworkyoudo.TheSPARCstation 5 Model as browsing and publishing online information 170 offers a choice in monitors and graphics. on internal intranets and on the Internet. The And inside every SPARCstation 5 system there’s newest SunPC™ card makes the SPARCstation 5 room for one floppy drive, two hard drives, Model 170 an excellent choice for the enterprise three SBus slots, and even a CD-ROM. Because desktop. These products allow users to run your desktop space is at a premium, we used a their UNIX® and Windows applications all in compact pizza-box design. The SPARCstation 5 one desktop at an affordable price. comes standard with 32-MB memory, expand- And the Solaris™ operating environment, able up to 256 MB. You can store large graphics the leader for enterprise-wide computing, com- files with up to 118 GB of mass storage. bines an easy-to-use graphical user interface Innovative multimedia capabilities include with sophisticated, network-aware personal 16-bit CD-quality audio, speaker, external micro- productivity tools, including multimedia elec- phone, the ShowMe™ whiteboard and shared tronic mail, calendar manager, and graphical applications software, and the SunVideo™ card, file manager.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]