Microsparc™-Iiep

Preliminary STP1100BGA December 1997 microSPARC™-IIep DATA SHEET SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces DESCRIPTION The microSPARC-IIep 32-bit microprocessor is a highly integrated, high-performance microprocessor. Imple- menting the SPARC Architecture version 8 specification, it is ideally suited for low-cost uniprocessor embedded applications. It is built with leading edge CMOS technology, with the core operating at a low voltage of 3.3V for optimized power consumption. The microSPARC-IIep includes on chip: integer unit (IU), floating-point unit (FPU), large separate instruction and data caches, a 32-entry version 8 reference MMU, programmable DRAM controller, PCI controller, PCI bus interface, a 16-entry IOMMU, flash memory interface support, interrupt controller, 2 timers, internal and boundary scan through JTAG interface, power management and clock generation capabilities. The operating frequencies are 100 MHz. Features Benefits • Integrated 32-bit, 33 MHz PCI expansion bus controller • Connection to industry-standard expansion bus • Integrated 256 MByte DRAM controller • High-bandwidth memory controller to reduce latency • Built-in 16 MByte flash memory controller • Flash memory interface runs real-time operating systems that loads and runs code out of ROM • SPARC high-performance RISC architecture • Compatible with over 10,000 applications and existing development tools • Support for little and big endian byte ordering • Handles with ease PCI devices designed for DOS machines, along with UNIX® applications • 8-window, 136-word register file • Fast interrupt response, procedure calls, and program execution • 16 KByte instruction cache and 8 KByte data cache • Decouples processor operation from slow external memory • Built-in floating-point unit • Supports concurrent execution of floating-point and integer instructions • On-chip memory management unit • Support for sophisticated operating systems with memory protection and virtual addressing • Operating voltage of 3.3V with 5V compatible I/O • Low-power core reduces power consumption and supports industry-standard peripherals • Integrated power management circuitry • Consumes minimal power during standby • IEEE 1149.1 (JTAG) boundary scan test bus • Ease of manufacturing tests 1 Preliminary microSPARC™-IIep STP1100BGA SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces PLL Clock IU FPU Generator 64 64 64 MMU I-Cache Write Buffer D-Cache 4 entry 32 entry 16K 8K TLB 64-Bit Cache Fill Bus PCI Flash Memory Interface Memory Interface Controller 64 up to 256MByte Address Bus 32-bit 33MHz PCI Bus of DRAM Figure 1. microSPARC-IIep Block Diagram Flash Memory microSPARC-IIep PCI Bus Up to 4 PCI Bus loads Local Bus Up to 32 MB DRAM SIMM Module 256 MB 32 MB DRAM SIMM Module DRAM 32 MB DRAM SIMM Module 32 MB DRAM SIMM Module SIMMs Figure 2. Typical microSPARC-IIep System Block Diagram 2 Sun Microsystems, Inc December 1997 microSPARC™-IIep Preliminary SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces STP1100BGA TECHNICAL OVERVIEW Integer Unit (IU) The microSPARC-IIep integer unit executes SPARC integer instructions defined in the SPARC Architecture Manual version 8. The IU contains 136 registers supporting 8-window registers and 8-global registers. It has numerous high performance features include instruction prefetching, branch folding and 5-stage instruction pipeline. The IU supports little- and big-endian byte ordering of data. Floating-Point Unit (FPU) The floating-point unit executes all single- and double-precision floating-point instructions defined in the SPARC Architecture Manual version 8. The FPU traps on quad-precision instructions and transfers their execution to software. The FPU contains a floating-point core based on Meiko design, a fast-multiplier, a 3-instruction deep instruction queue, and 32 32-bit floating-point registers. The floating-point core and fast multiplier allow parallel execution of floating multiplication (FPMUL) and another floating-point instruction while the instruction queue support concurrent execution of floating-point and integer instruction. Memory Management Unit (MMU) The microSPARC-IIep memory management unit translates 32-bit virtual addresses to 31-bit physical address. It maps physical address into 8 different address spaces. The MMU provides functionalities specified in the SPARC version 8 Reference MMU and implements hardware table-walk. It implements a 32-entry fully-associative translation lookaside buffer (TLB) and provides memory protection for 256 contexts. Instruction Cache The instruction cache is a 16 KByte, direct-mapped, virtually-indexed, virtually-tagged cache. The instruction cache is organized as 512 lines of 32 bytes plus 32 tag bits. To reduce read-miss latency, the instruction cache supports cache refill in two 32-bit words, streaming and bypass. Data Cache The data cache is an 8-KByte, direct-mapped, virtually-indexed, virtually-tagged cache. Cache write policy supported is write-through with no write-allocate. The data cache is organized as 512 lines of 16 bytes plus 32 tag bits. The data cache provides zero-penalty data accesses for cache hits. To reduce write latency, the data cache contains a 4-deep double-word store buffer. To reduce read-miss latency, the data cache supports cache refill in two 32-bit words, streaming and bypass. DRAM Interface The microSPARC-IIep DRAM interface supports industry standard fast-page mode DRAM and EDO DRAM that support fast-page mode. It supports 8 banks of memory up to a total of 256 MBytes of system memory. Each bank of memory can be consisted of 8 MBytes, 16 MBytes or 32 MBytes. The DRAM interface is programmable and support different memory speeds relative to the processor frequency. The DRAM data bus is 64 bits wide with two parity bits, each covering 32-bits of data. The parity bits can be disabled. The DRAM interface provides a programmable DRAM refresh controller that supports CAS-before-RAS refresh. December 1997 Sun Microsystems, Inc 3 Preliminary microSPARC™-IIep STP1100BGA SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces PCI Bus Interface The PCI bus interface complies with the industry standard PCI Local Bus Specification version 2.1. It provides a 32-bit 33MHz bus interface. Its features include endian conversion for different data byte ordering, PCI Host and Satellite mode, a dedicated 16-entry translation lookaside buffer (TLB) dedicated for I/O transactions, a PCI arbiter, and PCI clock, reset and interrupt handler. As a PCI Host, microSPARC-IIep performs PCI bus arbitration, PCI clock, reset and interrupt handling. As a PCI Satellite, microSPARC-IIep relinquishes the PCI Host functionalities to the external PCI Host. Other features supported by the PCI Bus interface include: • Programmed input/output (PIO) transactions between the microSPARC-IIep and external PCI devices. • PCI Host or Satellite mode selected by input pins during power-up. • Programmable configuration of external PCI devices (Type 0 and Type 1) while under PCI Host mode. • Programmable configuration by external PCI Host while under PCI Satellite mode. • Buffers with matching fill and drain rate allow extended burst transfers. • Direct transactions between PCI masters and PCI slaves. • Two PCI bus fairness access arbitration protocols: same-level round robin and three-level round robin. • Direct virtual memory access (DVMA) transactions between PCI masters and the microSPARC-IIep slave memory interface (referred to as PCI DVMA) using the software-controlled IOTLB to generate physical DRAM addresses. • Booting from the PCI Bus from address selected by user. • While under standby mode to reduce power consumption, the PCI interface consumes minimal power to support clock generation and wake-up when interrupted. • Two 32-bit timers or one 32-bit timer and one 64-bit counter available. • Interrupt handler supports up to eight programmable interrupt input/output lines. Flash Memory Interface Using an industry-standard programming algorithm, the microSPARC-IIep flash memory interface is compatible with 28FxxxXX flash memory devices. The interface has a programmable latency to allow flash memory access time of up to 45 processor clocks. After power-up, the default latency of the interface is 45 processor clocks. It can then be programmed to have an access latency from 6 to 45 processor clocks in increments of 3 processor clocks. The flash memory interface supports up to 16MBytes of data. It supports both 32-bit and 8-bit data accesses as selected by a boot-mode select input pin. microSPARC-IIep is pin-selectable to boot from the flash memory interface or the PCI address space. JTAG Test Bus Interface The microSPARC-IIep provides a five-wire test access port (TAP) interface to support boundary scan and clock control. This interface is compatible with IEEE 1149.1 specification, IEEE Standard Test Access Port and Boundary Scan Architecture. This allows efficient access to any single chip in a scan daisy-chain without board-level multiplexing. 4 Sun Microsystems, Inc December 1997 microSPARC™-IIep Preliminary SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces STP1100BGA TAP Controller The TAP controller is a synchronous finite state machine (FSM) which controls the sequence of operations of the JTAG test circuitry, in response to changes on the JTAG bus. The TAP controller is asynchronous with respect to the system clocks, and can therefore be used to control the clock control logic. The TAP FSM implements the state (16 states) diagram as detailed in the IEEE 1149.1 specification. Power Management microSPARC-IIep can detect system inactivity, and place itself in a standby mode to reduce power consumption. While in standby mode, the processor consumes minimal power. However, the PCI interface remains active and any PCI activity will wake up the processor. December 1997 Sun Microsystems, Inc 5 Preliminary microSPARC™-IIep STP1100BGA SPARC v8 32-Bit Microprocessor With PCI/DRAM Interfaces SIGNAL DESCRIPTIONS [1] PCI Signals Signal Type Note Description PCI_CLK[3:0] Out 2. Clock output pin. Under PCI Host mode, provide clock to other PCI devices. Under PCI Satellite mode, signal is unconnected. PCI_RST# I/O 2.

Load more