Microsparc-Iiep™ Validation Catalog

microSPARC-IIep™ Validation Catalog

Sun Microsystems, Inc. 901 San Antonio Road Palo Alto, CA 94303 USA 650 960-1300

Part No.: 851-2430 Revision: 01 July 1999 Copyright © 1999 Sun Microsystems, Inc. All rights reserved. The contents of this documentation is subject to the current version of the Sun Community Source License, microSPARC-II ("the License"). You may not use this documentation except in compliance with the License. You may obtain a copy of the License by searching for "Sun Community Source License" on the World Wide Web at http://www.sun.com. See the License for the rights, obligations, and limitations governing use of the contents of this documentation. Sun Microsystems, Inc. has intellectual property rights relating to the technology embodied in this documentation. In particular, and without limitation, these intellectual property rights may include one or more U.S. patents, foreign patents, or pending applications. Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, Solaris, Java and all Java-based trademarks and logos are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. microSPARC is a trademark or registered trademark of SPARC International, Inc. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. an architecture developed by Sun Microsystems, Inc.

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THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOGRAPHICAL ERRORS. CHANGES ARE PERIODICALLY ADDED TO THE INFORMATION HEREIN; THESE CHANGES WILL BE INCORPORATED IN NEW EDITIONS OF THE PUBLICATION. SUN MICROSYSTEMS, INC. MAY MAKE IMPROVEMENTS AND/OR CHANGES IN THE PRODUCT(S) AND /OR THE PROGRAM(S) DESCRIBED IN THIS PUBLICATION AT ANY TIME.

Please Recycle Contents

1. Introduction 1 1.1 microSPARC-IIep Blocks 1 1.2 microSPARC-IIep Diagnostic Style 1 1.3 microSPARC-IIep Diagnostic Modes 2

2. Diagnostic Environment 5 2.1 Test Environment 5 2.2 Memory Environment 5 2.2.1 Tests Using the Assembly to Verilog tool 6 2.3 PCI Environment 9

3. Integer Unit Tests 13

4. Floating-point Unit Tests 47

5. Memory Management Unit Tests 77

6. Instruction and Data Cache Tests 105

7. Memory Interface Unit Tests 113 7.1 FlashPROM Controller 8-bit Tests 116 7.2 FlashPROM Controller 32-bit Tests 117

Contents iii 8. PCI Controller Unit Tests 119

9. Random Diagnostic Tests 133

Index 135

iv microSPARC-IIep Validation Catalog • July 1999 Preface

The book, microSPARC-IIep Validation Catalog, is one of a four-manual documentation set for the microSPARC-II technology. The other three manuals are: • Multiprocessor SPARC Architecture Simulator (MPSAS) User’s Guide, describes how to use the MPSAS and its associated programs. • Multiprocessor SPARC Architecture Simulator (MPSAS) Programmer’s Guide explains the facilities for creating or modifying MPSAS modules or otherwise extending MPSAS. • microSPARC-IIep Megacell Reference explains how to build microSPARC-IIep megacells.

Organization of This Book

This book is intended for programmers who develop and debug programs to be run the microSPARC-IIep. It is arranged as follows:

Chapter 1, "Introduction," introduces the microSPARC-IIep validation catalog.

Chapter 2, "Diagnostic Environment," describes the diagnostic environment used for microSPARC-IIep verification.

Chapter 3, "Integer Unit Test," identifies the integer unit validation test suites.

Chapter 4, "Floating-point Unit Tests," covers the microSPARC-IIEp floating- point unit diagnostic tests.

v Chapter 5, "Memory Management Unit Tests," describes the diagnostic tests for the memory management unit.

Chapter 6, "Instruction and Data Cache Tests," describes the instruction and data cache validation test suites.

Chapter 7, "Memory Interface Unit Tests," covers the memory interface unit diagnoztics.

Chapter 8, "PCI Controller Unit Tests," covers the PCI controller unit tests.

Chapter 9, "Random Diagnostic Tests," describes the diagnostic test randomly generated using the thrash process.

Prerequisite Knowledge

It is assumed that you are familiar with programming in the C language in the UNIX® environment and that you have a basic familiarity with computer architecture, in particular the SPARC architecture. For further information, see the list of documents in the following section.

Related Books and References

The following documents contain material that further explains or clarifies information presented in this guide.

The SPARC V8 Architecture Manual

SunOS Reference Manual: Section 1, User Commands

The C Programming Language by Brian W. Kernighan and Dennis M. Ritchie, Prentice Hall; ISBN: 0131103628

vi microSPARC-IIep Validation Catalog • July 1999 Typographic Conventions

The following table describes the typographic conventions used in this book.

Table P-1Typographic Conventions

Typeface or Symbol Meaning Example

AaBbCc123 The names of commands, instructions, files, Edit your .login file. and directories; on-screen computer output; Use ls -a to list all files. email addresses; URLs machine_name% You have mail. AaBbCc123 What you type, contrasted with on-screen machine_name% su computer output Password: AaBbCc123 Command-line placeholder: To delete a file, type rm filename. replace with a real name or value AaBbCc123 Book titles, section titles in cross-references, Read Chapter 6 in User’s Guide. new words or terms, or emphasized words These are called class options. You must be root to do this.

Sun Documents

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For a list of documents and how to order them, see the catalog section of the SunExpress™ Internet site at http://www.sun.com/sunexpress.

Sun Documentation Online

The docs.sun.com Web site enables you to access Sun technical documentation online. You can browse the docs.sun.com archive or search for a specific book title or subject. The URL is http://docs.sun.com/.

Disclaimer

The information in this manual is subject to change and will be revised from time to time. For up-to-date information, contact your Sun representative.

Preface vii viii microSPARC-IIep Validation Catalog • July 1999 CHAPTER 1

Introduction

The microSPARC-IIep is a highly integrated, low-cost, low-power implementation of the SPARC V8 RISC architecture. High performance is achieved by the high level of integration including on-chip instruction and data caches, and close coupling of the CPU with main memory. A full custom implementation allows for a target frequency of 70 MHz and 150 MHz, providing sustained performance of 42 and 84 Specmarks, respectively. The design is highly testable with the use of the full JTAG scan support. The microSPARC-IIep supports up to 256 Mbytes of DRAM and four 32-bit 33 MHz PCI slots.

1.1 microSPARC-IIep Blocks

This catalog contains descriptions of the diagnostics used in the architectural verification of microSPARC-IIep. Explanations are provided for the individual test cases.The diagnostics are divided into the following sections: ■ Integer Unit ■ Floating-Point Unit ■ Memory Management Unit ■ Instruction Cache and Data Cache ■ Memory Interface Unit ■ PCI Controller ■ Random Tests

1.2 microSPARC-IIep Diagnostic Style

The microSPARC-IIep diagnostics can be classified into two categories:

1 ■ Non-asm2ver style: contains no notion of Reference MMU and thereby always runs with the MMU disabled. ■ asm2ver style: contains a notion of Reference MMU. The MMU is enabled and the process allows for mapping of virtual pages.

Many of the diagnostics are self-checking and do not require Microprocessor SPARC Architecture Simulator (MPSAS) support (option -n sas on run script). MPSAS performs rudimentary modeling of the PCI (just a memory), so most tests of the PCI are self-checking for that reason.

1.3 microSPARC-IIep Diagnostic Modes

The microSPARC-IIep diagnostics make use of a concept called “mode.” A mode is a way of enabling or disabling some of the major functional blocks of microSPARC- IIep. The following modes are used in the microSPARC-IIep: ■ c_pa_reset: cacheable physical address (cpa) prevents virtual to physical address translation. ■ tlb_reset: translation look-aside buffer (tlb) register mode with one TLB entry. Causes thrashing of the TLB for extra traffic on the internal memory bus. ■ tlb32_reset: translation look-aside buffer (tlb) register mode configured to operate with all 32 entries. The TLB replacement counter is enabled and the entries are replaced using a pseudorandom algorithm. ■ nc: no cache (nc) mode with reset environment. In this mode, the microSPARC- IIep is configured so that the Instruction Cache and Data Cache are both disabled. All memory references miss the cache. This mode resets the Instruction Cache Enable and Data Cache Enable bits in the Processor Control Register. ■ nic: no instruction cache (nic) mode with reset environment. In this mode, the microSPARC-IIep is configured so that the Instruction Cache is disabled. All instruction accesses to the cache cause a miss. This mode resets the Instruction Cache Enable bit in the Processor Control Register. ■ ndc: no data cache (ndc) mode with reset environment. In this mode, the microSPARC-IIep is configured so that the Data Cache is disabled. All data accesses to the cache cause a miss. This mode resets the Data Cache Enable bit in the Processor Control Register. ■ fastrfr: refresh (rfr) mode with reset environment. In this mode, the microSPARC-IIep is configured so that the external DRAM refresh rate is the fastest. The microSPARC-IIep generates a refresh cycle every 128 clocks. This mode resets the Refresh Control bits [1:0] in the Processor Control Register.

2 microSPARC-IIep Validation Catalog • July 1999 ■ s: standby (s) assert/deassert randomly the power-down mode pin. A Verilog task asserts the power-down mode pin. The deassert of the mode pin can happen by deasserting the pin itself, or by asserting a fixed interrupt (based on the power management specification). Memory protocol monitor and PCI bus protocol monitor are used to verify the quiescent state. ■ nbf: no branch folding (nbf) causes the microSPARC-IIep not to fold branches. ■ pmc0: page 0 mode control. ■ pmc1: page 1 mode control. ■ pmc2: page 2 mode control. ■ ptp2: creates virtually tagged level-2 page table pointers.

Chapter 1 Introduction 3 4 microSPARC-IIep Validation Catalog • July 1999 CHAPTER 2

Diagnostic Environment

This chapter describes the diagnostic environment used for microSPARC-IIep verification.

2.1 Test Environment

The microSPARC-IIep test environment consists of a two models: ■ Multiprocessor SPARC Architecture Simulator (MPSAS) model ■ Verilog RTL (or gate-level) model as simulated by VCS

There are two ways of running MPSAS: ■ I-I: instruction-to-instruction comparison, that is, MPSAS run with Verilog VCS. Comparisons are done after every instruction. ■ Standalone: MPSAS runs through diagnostic to the end, before Verilog is run, and final state dumps are generated. Verilog VCS simulation then starts, and upon completion, generates final state dumps. The two sets of dumps are then compared. MPSAS can also be run standalone without running VCS.

Three options are available: ■ run -n sas: run with neither I-I nor standalone (for self-checking diagnostics) ■ run -S: run both I-I and standalone ■ run: (unspecified option) run only standalone

5 2.2 Memory Environment

There are two perspectives to consider for the microSPARC-IIep address map: ■ Hard-wired physical address spaces ■ Virtual spaces setup by the asm2ver environment

The physical address spaces defined for microSPARC-IIep address bits 30:28 are listed in the microSPARC-IIep User’s Manual. It defines eight possible address spaces, four of which are currently used:

PA[30:28]=000 DRAM Memory (256M) PA[30:28]=001 Control Space (256M) PA[30:28]=010 FlashPROM Space (256M) PA[30:28]=011 PCI Space (256M)

2.2.1 Tests Using the Assembly to Verilog Tool

Tests that use the Assembly to Verilog tool (asm2ver) are prepended with reset.s and traps.s from asm2ver tests ~diag/include/asm2ver. These code segments use #define statements to configure different modes, such as supervisor/user, alignment trap enable, etc. The #define definitions can be put at the beginning of the test as follows: #define INIT_PSR SUPER

The preceding example instructs the reset.s code to set supervisor mode in the PSR without having to know the specific register or bit field. The reset.s and traps.s also build a default set of trap handlers and page tables. The code builds page tables for the code between the label user_text_start and user_text_end. A similar set of tables is built for the data segment between labels user_data_start and user_data_end. #define IOTLB_ENABLE

In the preceding example, the asm2ver test initializes and enables the iotlb. This causes translations for PCI DMA to and from main memory. This is normally used as follows: #define ENABLE_PCI

The preceding example sets up and enables the control registers for master and slave PCI traffic.

The IOTLB_ENABLE switch sets all 16 entries as follows:

6 microSPARC-IIep Validation Catalog • July 1999 .word 0x080010f4, 0x00000001 ! 0xf4100008, 0x01000000 .word 0x081010f4, 0x00800001 ! 0xf4101008, 0x01008000 .word 0x080020f4, 0x00000002 ! 0xf4200008, 0x02000000 .word 0x081020f4, 0x00800002 ! 0xf4201008, 0x02008000 .word 0x080030f4, 0x00000003 ! 0xf4300008, 0x03000000 .word 0x081030f4, 0x00800003 ! 0xf4301008, 0x03008000 .word 0x080040f4, 0x00000004 ! 0xf4400008, 0x04000000 .word 0x081040f4, 0x00800004 ! 0xf4401008, 0x04008000 .word 0x080050f4, 0x00000005 ! 0xf4500008, 0x05000000 .word 0x081050f4, 0x00800005 ! 0xf4501008, 0x05008000 .word 0x080060f4, 0x00000006 ! 0xf4600008, 0x06000000 .word 0x081060f4, 0x00800006 ! 0xf4601008, 0x06008000 .word 0x080070f4, 0x00000007 ! 0xf4700008, 0x07000000 .word 0x081070f4, 0x00800007 ! 0xf4701008, 0x07008000 .word 0x080080f4, 0x00000008 ! 0xf4800008, 0x08000000 .word 0x081080f4, 0x00800008 ! 0xf4801008, 0x08008000

The first word is the CAM position, second is the RAM portion. The words are byte- twisted to account for the translation that takes place going through PCIC in the default mode. The comments show the little endian equivalents.

The default memory maps for the asm2ver tests are listed in TABLE 2-1 and TABLE 2-2.

TABLE 2-1 Virtual Memory Map

0-11FF traps

1590 xxxxxxxx

2000 user text (code)

4000 results area I

C000 results area II

14000 trap handlers (reset handler, trap data table, stack space)

15000 user data

TABLE 2-2 Physical Memory Map

0000 trap vector table

5000 trap handler data

100000 user text area

200000 user data area

300000 results area

Chapter 2 Diagnostic Environment 7 To create a custom map, the function ASSIGN_MMU_PAGE is provided as follows:

ASSIGN_MMU_MAP ( PAGE_START_LABEL = user_text_start, PAGE_END_LABEL = user_text_end. PHYSICAL_PAGE_NUMBER = 0x30005, PAGE_ACCESS_RIGHTS = ACCESS_RW, PAGE_CUNTEXT_NUMBER = 55, PAGE_SIZE = PAGE_4K, PAGE_CACHEABLE, PAGE_ENTRY_RESERVED = 0. PAGE_ENTRY_PTP = 0, PAGE_DATA_EXCLUDE

FIGURE 2-1 Custom Mapping of the ASSIGN_MMU_PAGE Function

TABLE 2-3 identifies the definitions of each field of the ASSIGN_MMU_PAGE function.

TABLE 2-3 ASSIGN_MMU_PAGE Function Field Definitions

Field Description

PAGE_START_LABEL and Designates the beginning and end virtual address of a portion of code/data PAGE_END_LABEL that is to be located somewhere in physical memory. It could point to mnemonic labels within the test program or refer to absolute addresses.

PAGE_ACCESS_RIGHTS Assigns one of eight possible access rights to a set of pages between PAGE_START_LABEL and PAGE_END_LABEL. These access rights are described in the MMU specification. The mnemonics for these rights are: ACCESS_R, _RW, _RX, _RWX, _X, _S_RW, _S_RX, and _S_RWX for MMU codes 0-7, respectively.

PAGE_CONTEXT_NUMBER Denotes the page context number the set of pages belongs to. The maximum context number allowed is 256.

PAGE_SIZE Defines the size of the page the portion of code/data is assigned to. Four different page sizes are allowed and denoted by PAGE_4K, PAGE_256K, PAGE_16M, and PAGE_ROOT (4G). Multiple pages, of the required size, may be allotted automatically depending on the page size and the amount of information to be loaded into the pages. If the difference between the user_text_start and user_text_end labels in FIGURE 2-1 is 12 Kbytes and the PAGE_SIZE is defined to be PAGE_4K, three such pages will be used.

PAGE_CACHEABLE When present, denotes whether the page is considered cacheable or not. If it is not included, noncacheable is assumed.

PHYSICAL_PAGE_NUMBER Encodes the starting physical address for the pages being defined. This number is appended with three hexadecimal 0's to form the physical address.

8 microSPARC-IIep Validation Catalog • July 1999 TABLE 2-3 ASSIGN_MMU_PAGE Function Field Definitions (Continued)

Field Description

PAGE_ENTRY_VALID Allows some control over the valid field as it appears in the PTEs and PTPs of the MMU. The following macros are available:

LEVEL_ALLVALID Sets all entries valid

LEVEL3_INVALID Causes the third-level entry to be marked invalid

LEVEL2_INVALID Causes the second-level entry in the page table to be marked invalid

LEVEL1_INVALID Causes the first-level entry in the page table to be marked invalid

LEVEL0_INVALID Causes the zeroth-level entry in the page table to be marked invalid

2.3 PCI Environment

The verification setup for microSPARC-IIep consists of four RaviCad PCI masters, one RaviCad slave, and one LMC slave attached to the microSPARC-IIep PCI bus. PCI PIO traffic is performed by writing to the space three physical address range. This space is split into a hard-wired space and spaces that are potentially translated before they are sent to the PCI bus, as shown in TABLE 2-4.

TABLE 2-4 PCI Physical Address Space for PIO

Physical Address Mapping

0x30000000 - 0x3000FFFF Hard-wired IO space to PCI bus.

0x30001000 - 0x31000000 Contains configuration registers and untranslated memory.

Any space three addresses above this last range are subject to translation by the smbar0, smbar1, and pibar registers. Refer to microSPARC-IIep User’s Manual for details. These registers allow for two different memory spaces and one IO space to be translated before going to the PCI bus. Any address in this range, not caught by the range of one of these registers, goes through untranslated as a memory cycle.

For all space three cases, the uppermost nibble, bits 31:28, do not get passed on to the PCI bus. For the fixed map cases, the nibble is stripped. For the translated cases, the upper bits presented on the PCI bus are determined by the register mappings.

Chapter 2 Diagnostic Environment 9 Therefore, there is no simple mapping of the PIO address space above 0x30FFFFFF. It is set by the translation registers. The crueltt_falc.s and traps.s initialization code provide for default programming of these registers, as well as the DMA translation. To provide a consistent default test environment, the PCI slave models have been set to respond to the following PCI physical address ranges. FIGURE 2-2 illustrates the ranges. lmc mem range 0 00100000-001FFFFF//LMC mem pages accessed by fixed map lmc mem range 1 21000000-21002000//2 LMC mem pages accessed by (pmbar0=2) translation lmc mem range 2 (still available) lmc io range 0 00000000-00002000//2 LMC IO pages accesses by fixed map lmc io range 1 13004000-13008000//4 LMC IO pages accessed by (pibar=1) lmc io range 2 (still available) ravi mem range 00800000-12004000 *//Large range in fixed mem+pages translated by (pmbar1=1) ravi io range 00004000-13002000//Pages in fixed IO+2 pages contiguous with LMC IO (pibar=1)

FIGURE 2-2 PCI Physical Address Ranges

These ranges provide target addresses that can be used with both the fixed map, requiring no register setup, and the default settings of the translation registers.

Files pcic.h and pcic.s are in the PCI/include area. The pcic.h file has some #defines for PCIC registers. If you use traps.s or crueltt_falc.s in your test, you can use these instead of hardwired values.

TABLE 2-5 shows the six PCI base registers and six PCI size registers the pcic.s file initializes.

TABLE 2-5 PCI Base and PCI Size Registers

PCI Base PCI Size Registers

PCIBASE0 Set to map PCI DMA starting at 0xF0000000

PCISIZE0 The space above covers a 256-Mbyte range

PCIBASE1 Set for 0xE0000000

PCISIZE1 Set for 256 bytes

PCIBASE2 Set for 0xE0000100

PCISIZE2 Set for 256 bytes

PCIBASE3 Set for 0xE0000200

PCISIZE3 Set for 256 bytes

PCIBASE4 Set for 0xE0000300

PCISIZE4 Set for 256 bytes

10 microSPARC-IIep Validation Catalog • July 1999 TABLE 2-5 PCI Base and PCI Size Registers (Continued)

PCI Base PCI Size Registers

PCIBASE5 Set for 0xE0000400

PCISIZE5 Set for 256 bytes

One of the register sets maps master DMA space similarly to the way it was set up for the PCI DMA master tests, such as burst_wr. The remaining registers are parked into unique 256-byte spaces starting at 0xE0000000.

The SMBAR registers for afx to PCI space have new addresses. They have #defines in pcic.h as well. They default to the values listed in TABLE 2-6.

TABLE 2-6 SMBAR Registers Default Values

SMBAR0 0x01 … Bits 27:23 of virtual address

MSIZE0 0x0F … Compare all four bits

PMBAR0 0x20 Bits 28:23 on PCI bus

SMBAR1 0x02

MSIZE1 0x0F

PMBAR1 0x10

Chapter 2 Diagnostic Environment 11 12 microSPARC-IIep Validation Catalog • July 1999 CHAPTER 3

Integer Unit Tests

This chapter identifies the integer unit validation test suites.

addrbyp

Data bypass is required when the instruction immediately following a load instruction (LD, LDUB, LDSB, LDUH, LDSH, and the alternate space variants) uses as an operand the destination register of the load.Bypass path 3 is used to pass a result from an R stage to the D stage in the pipeline. This diagnostic checks that the source 1 and source 2 inputs of the address adder are fed properly by the bypass paths from LD and LDD type instructions.

allInsts

A basic test to verify execution of each instruction. The program contains a number of nops to test instructions without any dependencies and interlocks. This test verifies illegal opcodes. This test, along with FallInst_v.s diagnostic, covers all the instructions. This is a self-checking diagnostic. The following instructions are verified: add, addcc, addx, addxcc, and, andcc, andn, andncc, annul, ba, bicc not taken, bicc taken, call, iflush, jmpl, ld, ldd, lddf, ldf, ldfsr, ldsb, ldsh, ldst, ldub, lduh, mulscc, or, orcc, orn, orncc, rdpsr, rdwim, rdy, restore, save, sra, std, swap, sethi, sll, srl, st, stb, stdfq, stf, stfsr, sth, sub, subcc, subx, subxcc, taddcc, taddcctv, ticc, tsubcc, tsubcctv, xnor, xor, xorcc, wrpsr, wrwim, wry.

This test uses its own trap handler.

13 alu_tvs

This diagnostic puts predetermined sequences of patterns through the ALU. The tests consist of blocks of ADDcc, ADDXcc, SUBcc, ORNcc, ORcc, ANDNcc, ANDcc, XNORcc, and XORcc instructions. Each instruction takes as operands two words read from the data segment to produce a result and setting of the icc. If the flag CHECK_RES is set at compilation time, the result and correct icc image are also read and checked against the results. The result of the operation is then stored, to make it visible, on the output pins of the IU. The original test patterns as received from BIT had the various instruction patterns interspersed. For this diagnostic, each instruction type (for example, all ANDcc) has been grouped to run together in a loop. To guarantee the correct condition codes are used for each subblock (for example, a group of sequential ADDXccs before they were merged), additional instructions are added to correctly set the ccs.

anotherRett

A basic test to verify various rett conditions. The following cases are covered: ■ ET = 1, S = 0, misaligned address, window underflow should get illegal instruction trap because ET = 1 ■ ET = 0, S = 0, misaligned address, window underflow should get privilege instruction trap because S = 0 ■ ET = 0, S = 1, misaligned address, window underflow should get window underflow trap ■ ET = 0, S = 1, misaligned address should get misaligned address trap ■ ET=1,ticc 26 trap handler does ticc 27 to make sure TT does not change on second ticc.

This test causes a watch-dog reset and an endless loop in Verilog simulation.

atomic_h

A basic test to verify atomic operation under different conditions. The atomic instructions (swap and ldstub) will hit in the cache, miss in the cache, and a non- cached access is attempted. Six cases are covered.

bicccorner_h

A test to verify the corner conditions with bicc instructions. The test verifies the following cases:

The annulled instruction in the delay slot is udivcc. ALl 16 branch instructions are followed by a udivcc instruction. The udivcc instruction should be annulled in each case.

14 microSPARC-IIep Validation Catalog • July 1999 Causes an Instruction Cache miss for the delay slot instruction. The missing instruction is a udivcc.

Checks for udivcc for overflow condition. br_displ.s

This diagnostic does plenty of negative displacements in bicc/call instructions. Displacements vary from 1 to 8. brCombo

An exhaustive test to verify all the branch condition code combinations. The following tests are covered: ■ Branch which annul single cycle alu instructions ■ Branch which annul loads ■ Branch which annul stores ■ Branch which annul ldstub (atomic operation) ■ Branch which annul floating-point loads ■ Branch which annul branches ■ Branch which annul jmp ■ Branch which annul save ■ Branch which annul restore ■ Branch which annul ticc ■ Branch which annul rett ■ Taken branches with various instructions (addcc, ld, jmp, ldd, st, std, rett)in the delay slot and branch target is also a branch ■ Branch followed by a branch combination. The target of first branch is also a branch. The first branch is taken. ■ Not taken branch with various delay (faddd, ld, ldd, st, std, ticc, taddcctv) and target instructions. branch_seq1

This diagnostic tests the branch sequence where a control transfer instruction (with its delay slot) has another control transfer instruction at or within seven instructions of the target. (The instructions before the second control transfer are nops in this diagnostic.)

The first control transfer is one of four possibilities: call, jump link, branch (taken, no annul), branch (taken, annul).

Chapter 3 Integer Unit Tests 15 The second control transfer is one of six: call, jump link, branch (taken, no annul), branch (taken, annul), branch (not taken, no annul), branch (not taken, annul).

Also, the first and the second control transfer can be on even or odd addresses (independent of each other). Each set of combinations is further expanded to give the target transfer at one of the first eight locations at the target.

The body of tests is in branch_seq.tb and is generated from branch_seq.im by the script branch_seq.make. The total number of test sets is: (2 * 4) * (2 * 6) * (8) = 768 with the first odd/even second odd/even and eight target locations.

Due to the large size of this diagnostic, it has been broken into three parts that run independently. The other two diagnostics are called branch_seq2 and branch_seq3.

branch_seq2

The first control transfer is one of four possibilities: call, jump link, branch (taken, no annul), branch (taken, annul).

The second control transfer is one of six: call, jump link, branch (taken, no annul), branch (taken, annul), branch (not taken, no annul), branch (not taken, annul).

The body of tests is in branch_seq.tb and is generated from branch_seq.im using the script branch_seq.make. The total number of test sets is: (2 * 4) * (2 * 6) * (8) = 768. First odd/even second odd/even eight target locations.

Because of the large size of this diagnostic, it has been broken into three parts that run independently. The other two diagnostics are called branch_seq1 and branch_seq3.

16 microSPARC-IIep Validation Catalog • July 1999 branch_seq3

The first control transfer is one of four possibilities: call, jump link, branch (taken, no annul), branch (taken, annul).

The second control transfer is one of six: call, jump link, branch (taken, no annul), branch (taken, annul), branch (not taken, no annul), branch (not taken, annul).

Also, the first and the second control transfer can be on even or odd addresses (independent of each other). Each set of combinations are further expanded to give the target transfer at one of the first eight locations at the target.

Because of the large size of this diagnostic, it has been broken into three parts that run independently. The other two diagnostics are called branch_seq1 and branch_seq2. branche

A basic test to verify the 16 combinations of the taken and not taken branches. bypass3

Data bypass is required when the instruction immediately following a load instruction (LD, LDUB, LDSB, LDUH, LDSH, and the alternate space variants) uses as an operand the destination register of the load.Bypass path 3 is used to pass a result from an R stage to the D stage in the pipeline. This diagnostic checks that the source 1 and source 2 inputs of the adder are fed properly by the bypass paths from alu type instructions.

This test is similar to the mem_memCombo test.

Chapter 3 Integer Unit Tests 17 bypass3_win

Data bypass is required when the instruction immediately following a load instruction (LD, LDUB, LDSB, LDUH, LDSH, and the alternate space variants) uses, as an operand, the destination register of the load.Bypass path 3 to pass a result from the R stage to the D stage in the pipeline. This diagnostic checks that the source 1 and source 2 inputs of the adder are fed properly by the bypass paths from alu type instructions.

This test is similar to the bypass3 test. This test does not have the percent go no bypass test case.

callret

This is a short test to verify the call and return operations.

callrit

This is a basic test to verify register interlock after a call instruction. For example, if the instruction in the delay slot of a call instruction uses register %o7, there is an interlock so that the new value (written by the call instruction) is used. The instructions used in the delay slot are jmp, ld, ldd, ldstub, multiple call, restore, save, st, std, taddcctv, and ticc.

cti_couplest1

This program tests all the CTI combinations. ■ Register r10 (window = 2) is used to log errors. ■ Register r11 (window = 2) is used to log the various cases covered. ■ A non-zero bit in r10 indicates an error. ■ A non-zero in r11 indicate the cases covered by the test.

TABLE 3-1 identifies the bit assignment for r10/r11.

18 microSPARC-IIep Validation Catalog • July 1999 TABLE 3-1 Error Bit Assignment for CTI Combinations

01:00 case 1a

03:02 case 1b

05:04 case 1c

07:06 case 1d

09:08 case 2a

11:10 case 2b

13:12 case 3a

15:14 case 3b

17:16 case 4a

19:18 case 4b

21:20 case 7a

23:22 case 7b

25:24 case 8a

27:26 case 8b

Upon successful completion of the test, r10 (out2, location 42 dec. in RF) will have all 0’s, and r11 (out3, location 43 dec. in RF) will have all 1’s.

TABLE 3-2 CTI Combination Test Cases

Case No. Cti # 1 Cti # 2

1a cti taken cti taken

1b cti (a) taken cti taken

1c cti taken cti (a) taken

1d cti (a) taken cti (a) taken

2a cti taken BA (a)

2b cti (a) taken BA (a)

3a cti taken cti untaken

Chapter 3 Integer Unit Tests 19 TABLE 3-2 CTI Combination Test Cases (Continued)

Case No. Cti # 1 Cti # 2

3b cti (a) taken cti untaken

4a cti taken cti (a) untaken

4b cti (a) taken cti (a) untaken

7a BA (a) cti taken

7b BA (a) cti (a) taken

8a BA (a) cti untaken

8b BA (a) cti (a) untaken

cwp

This diagnostic tests the various instructions and sequences that affect and depend upon the CWP. These include the save and restore instructions and the subroutine linkage sequence.

divTest

A short test to check sdivcc boundary case. It performs a number of divisions and checks the results against a precalculated result. It also tests the conditions code bits; it also checks for overflow conditions. The test branches to bad trap location in case of failure.

divTest1

A short test to check sdivcc and udivcc operations. It performs a number of divisions and checks the results against a precalculated result. It also tests the conditions code bits; it also checks for overflow conditions. The test branches to bad trap location in case of failure.

divTest2

A short test to check sdivcc and udivcc boundary case. It performs a number of divisions and checks the results against a precalculated result. It also tests the conditions code bits. It checks for division by zero (trap) and result of zero conditions. The test branches to bad trap location in case of failure.

20 microSPARC-IIep Validation Catalog • July 1999 divTest3

A basic test to check sdivcc boundary case. It performs a number of divisions and checks the results against a precalculated result. It also tests the conditions code bits; it checks for overflow conditions. The test branches to bad trap location in case of failure. divTest4

A short test to check sdiv operations. It performs a number of divisions and checks the results against a precalculated result. It also tests the conditions code bits. The test branches to bad trap location in case of failure. div_test

An exhaustive test to verify udiv, udivcc, sdiv, and sdivcc operations. The test causes a divide by zero trap, overflow conditions, and performs various divides for randomly generated operands. dmove

A short test to verify basic load/store operations with interlocks. The following cases are covered: ■ Load followed by a dependent store ■ Load double followed by a dependent store even register ■ Load double followed by a dependent store odd register ■ Load even register followed by a dependent store double ■ Load odd register followed by a dependent store double ■ Load double register followed by a dependent store double ■ Generic store followed by store double dslot_ilock2

This diagnostic tests the cases where an interlock occurs in the delay slot of a branch. The interlock is set up by a taken CTI. The FPC is notified of the new PC via the DOUT bus, but it must interlock because an FPU operation wants to be sent at the same time. The new PC is sent first, causing the IU to interlock. This diagnostic (dslot_ilock2) considers half the cases: The first CTI is a taken branch (annulled and not annulled cases), the second CTI is a FBicc (taken, untaken, and the annulled versions). See dslot_ilock3 for the other cases.

Chapter 3 Integer Unit Tests 21 dslot_ilock3

This diagnostic tests the cases where an interlock occurs in the delay slot of a branch. The interlock is set up by a taken CTI. The FPC is notified of the new PC via the DOUT bus, but it must interlock because an FPU operation wants to be sent at the same time. The new PC is sent first, causing the IU to interlock. This diagnostic (dslot_ilock3) considers half the cases: The first CTI is a taken branch (annulled and not annulled cases), the second CTI is an FBicc (taken, untaken, and the annulled versions). See dslot_ilock2 for the other cases.

forwsethi

A single operand corner case to verify forwarding (bypassing) into sethi. It doesn’t affect anything else.

ia_da_mmu_miss_h

A quick test to verify the interaction between Integer Unit and Memory Management Unit for instruction access error trap and data access error trap. This test also toggles the software table walk mode bit.

idiv_ovf

A quick test to verify the divide overflow cases. The test covers the udivcc and sdivcc instructions.

idiv_zero

A quick test to verify the divide by zero cases. The test covers the sdiv, sdivcc, udiv, and udivcc instructions.

ifetch.s

A shorter diagnostic to reproduce bugs found by Kaos. Bug related to iflush instruction followed by a folded branch caused the PC and instruction to miscompare.

iflush1.s

Tests iflush 5 instruction window with a full queue.

22 microSPARC-IIep Validation Catalog • July 1999 The algorithm: loads a line in the cache. This line contains an iflush instruction. Modify the sixth instruction after iflush to jump to the next test. Branch back to the line in cache. Execute iflush instn. The sixth instruction should be the modified instruction to jump to the next test. The following cases are covered: ■ iflush at odd address ■ iflush at even address ■ iflush at even address with a preceding multicycle instruction ■ iflush at odd address with a preceding multicycle instruction ■ iflush at odd address, nop followed by a folded branch ■ iflush at even address, nop followed by a folded branch ■ iflush at even address, nop followed by a folded branch and iflush preceded by a multicycle instruction ■ iflush at odd address, nop followed by a folded branch and iflush preceded by a multicycle instruction iflush2.s

Tests iflush instruction window with an empty queue. The algorithm is the same as iflush1.s. iflush instruction is executed with an empty queue by having iflush the target of a branch. The following cases are covered: ■ iflush at even address ■ iflush at odd address ■ iflush at even address with a preceding multicycle instruction ■ iflush at odd address with a preceding multicycle instruction iflush3.s

Tests iflush instruction window with iflush in the delay slot of a folded branch. The algorithm is same as iflush1.s. iflush instruction is executed in delay slot of folded branch. Eight possible branch cases are considered. iflush4.s

Tests iflush 5 instruction window with iflush preceding a folded branch. The algorithm is same as iflush1.s. iflush instruction is executed preceding a folded branch. Eight possible branch cases are considered.

Chapter 3 Integer Unit Tests 23 iflush5.s

Tests iflush 5 instuction window with iflush being the target of a folded branch. The algorithm is same as iflush1.s. iflush instruction is executed as the target of a folded taken branch. Four possible branch cases are considered and iflush at even and odd address.

iflush6.s

Tests iflush 5 instruction window with iflush being the target of an untaken folded branch. The algorithm is same as iflush1.s. iflush instruction is executed as the target of an untaken folded branch. Four possible branch cases are considered and iflush at even and odd address.

iflush7.s

Tests iflush 5 instruction window with an empty queue, followed by a folded branch and iflush at even and odd address. The algorithm is same as iflush1.s. The following cases are covered: ■ Empty queue -> iflush -> nop -> folded branch (iflush at even address) ■ Empty queue -> iflush -> nop -> folded branch (iflush at odd address)

iflush8.s

Tests iflush 5 instruction window with iflush and jmp instructions. The algorithm is same as iflush1.s. The following cases are covered: ■ iflush before and after a jmp ■ iflush -> nop -> jmp ■ iflush target of a jmp (even and odd address)

ill_opcode

This diagnostic creates instruction words that contain illegal opcodes (OP3). Not all illegal opcodes are covered. See the macro file ill_opc_macro.s for documentation for a list of the codes that are covered. Each illegal instruction traps to the handler illegal_opcode and increment a counter (illop_ct). At the end of execution, this illop_ct contains the number of illegal instructions encountered (NUM_ERRS). This value is checked at the end. This diagnostic also tests the now illegal LDF2, STF3, LDC3, and STC2. It does not check LDF3, STF2, LDC2, or STC3.

24 microSPARC-IIep Validation Catalog • July 1999 illegal_branches

This diagnostic tests combinations involving illegal combinations of branches. CTI couples will fail if the first bicc is not taken. The following cases are covered: ■ Annulled branch not taken ■ Floating-point annulled branch not taken

This diagnostic fails if run with branch folding. It is run without branch folding in regression. imul_742_810

A quick test to verify the multiply corner case bugs 742 and 810. The test verifies a multiply instruction followed by a mulscc instruction. The test also verifies the following bypass sequence: load instruction -dest_reg1 ■ Any instruction ■ Add or subtract instruction with dest_reg1 as one of the sources ■ Multiply instruction imul_idiv

A short test to verify multiply and divide operations using register operands. The test performs umulcc, smulcc, umul, sdivcc, udivcc. Eight operations are performed. imul_idiv_imm

A short test to verify multiply and divide operations using immediate operands. The test performs umulcc, smulcc, umul, sdivcc, udivcc. Six operations are performed. imul_simple

A short test to verify multiply operation using register operands. The test does one umulcc, smulcc, and umul operation. interlock

This diagnostic tests IU register interlocks that occur following certain instructions.

Chapter 3 Integer Unit Tests 25 If the instruction in the delay slot of a call instruction uses register %07. There is an interlock so that the new value written by the call instruction is used.

Write and Read Y register with a three-instruction delay interlock.

Write and Read PSR register with a three-instruction delay interlock. The implementation and version number are masked off.

Write and Read WIM register with a three-instruction delay interlock.

A simple interlock for load single word from memory.

intlddstd

A simple test case to verify register interlocks during load and store double word operands. Interlock is between a couple of load instructions. It also checks for load followed by store operation.(Read followed by Write to memory).

intldst

A simple test case to verify Load Store Unsigned Byte operation. All the ldstub operations causes an data access exception. The destination register in the test should be clearly restored upon data access exception to work.

intload

A simple test case to verify various load instructions: the load word, load unsigned halfword, load signed halfword, load unsigned byte, load signed byte for all address alignments. The load writes into all the registers of one window. There are no stores to verify that the loads into the register file are done correctly. To improve observability, use intload2.

intload2

A simple test case to verify various load instructions followed by store of all registers of interest: the load word, load unsigned halfword, load signed halfword, load unsigned byte, load signed byte for all address alignments. The loads writes into all the registers of one window. The individual registers are then stored back to memory to allow improved observability on the pins of microSPARC-I.

26 microSPARC-IIep Validation Catalog • July 1999 intma

A quick and simple test to verify load and store operation. A basic diagnostic which should be used during bring-up. No self-checking for the results written to register file or memory. To improve observability, use intma_h. intma_h

A quick and simple test to verify load and store operation with self-checking. A basic diagnostic which should be used during bring-up. Self-checking is provided for the results written to the register file and memory. intma_tbr

A quick and simple test to verify load and store operation. A basic diagnostic that should be used during bring-up. No self-checking for the results written to register file and memory. Only difference between this diagnostic and intma is that this writes a non-zero value into the upper bits of the tbr register. iu_traps_h

A toggle coverage test to toggle all the bits of the wim register. The test also generates a single data access exception trap. jmp

A short test to verify the jump and call sequence. The test does the jmp followed by a jmp followed by a call followed by a jmp. jmpCombo

An exhaustive test to verify the combinations of jump with various other instructions. The following cases are covered: ■ jmp followed by a bicc instruction ■ jmp followed by a call instruction ■ jmp followed by a load instruction ■ jmp followed by a ldstub instruction ■ jmp followed by a load double instruction ■ jmp followed by a store instruction ■ jmp followed by a store double instruction ■ jmp followed by a branch followed by a call

Chapter 3 Integer Unit Tests 27 ■ jmp followed by a jmp followed by a call ■ jmp followed by a read y register ■ jmp followed by a read psr register ■ jmp followed by a read tbr register ■ jmp followed by a read wim register

jmplRett_v

This diagnostic sets up an rett to return to a supervisor page in user mode (by setting PS=0) to a trap. The fetch of the rett target gets an instruction access exception.

jmplRett_v_h

A specific test case that sets up a rett to return to a supervisor page in user mode (by setting PS=0 to a trap). The fetch of the rett target gets an instruction access exception. This test also checks for an instruction cache miss between jmpl and rett.

jmplRettvu_h

A specific test case that sets up a rett to return to a user page from a supervisor mode (by setting PS=1 prior to a trap). The fetch of the rett target will not get an instruction access exception.

lotsatog

A toggle test to improve the toggle coverage. The test will do a series of load signed byte, load unsigned byte, load signed halfword, load unsigned halfword, addcc, and series of additions.

mem_brCombo

An exhaustive test to verify the memory load/store operations followed by a bicc instruction. The following cases are covered: ■ Store word followed by bicc ■ Store word followed by bicc,a not taken ■ Store word followed by taken ■ Store word followed by bicc,a taken ■ Store word followed by a branch always ■ Store word followed by a branch always, annulled

28 microSPARC-IIep Validation Catalog • July 1999 ■ Load word followed by bicc not taken ■ Load word followed by bicc,a not taken ■ Load word followed by taken ■ Load word followed by bicc,a taken ■ Load word followed by a branch always. ■ Load word followed by a branch always, annulled ■ ldstub followed by bicc not taken ■ ldstub followed by bicc,a not taken ■ ldstub followed by taken ■ ldstub followed by bicc,a taken ■ ldstub followed by a branch always ■ ldstub followed by a branch always, annulled mem_jmpRett

An exhaustive test that verifies various memory reference instructions followed by jmp, rett, fpop instruction sequence. The following cases are covered: ■ Load word followed by a jmp, rett ■ Store word followed by a jmp, rett ■ Load double word followed by a jmp, rett ■ Store double word followed by a jmp, rett ■ ldstub followed by a jmp, rett ■ load word followed by load floating-point word, followed by interlocking fpop

This test uses its own trap handler. multicycleCombo

An uninterrupted sequence of instructions —ld st ldstub ldd std jmp, which is designed so that each of the following instructions is followed by any other sometime during the sequence: ■ Load word. ■ Load unsigned halfword. ■ Store word (register interlock with previous load). ■ Store halfword (register interlock with previous load unsigned halfword). ■ Load store unsigned byte. ■ Load store unsigned byte. ■ Load double word. ■ Load double word. ■ Store double word (register interlock with first load double word). ■ Store double word (register interlock with second load double word).

Chapter 3 Integer Unit Tests 29 ■ jmpl. ■ ldub, ldstub, ldsh, ldd, ldsb, std (register interlock with previous ldd), ld, jmpl, stb. ■ lduh, st, ldd, std (register interlock with previous ldd), std (register interlock with previous ldd), stb, jmpl, ldstub. ■ st, save, st, ldstub, std, ldstub, jmpl, ldd. ■ ldstub, ldd, jmpl, std (register interlock with previous ldd), ldd.

muldivcor_high

A corner case test for multiply, divide, address generation operations and interlock with %g0 register. The following is the test sequence: ■ Generate a very large address and return back. ■ Do umulcc with the same source and destination register. ■ Perform back-to-back unsigned multiply and unsigned divide with same destination register. One of the source registers is the same as the destination register. ■ Perform back-to-back signed multiply and signed divide with same destination register. One of the source registers is the same as the destination register. ■ Interlock test for load double and store double with %g0. Only the %g1 register should be updated.

This test is a superset of muldivcorner_h.

muldivcorner_h

A corner case test for multiply, divide operations and interlock with %g0 register. The following is the test sequence: ■ Do umulcc with the same source and destination register. ■ Perform back-to-back unsigned multiply and unsigned divide with same destination register. One of the source registers is the same as the destination register. ■ Perform back-to-back signed multiply and signed divide with same destination register. One of the source registers is the same as the destination register. ■ Interlock test for load double and store double with %g0. Only the %g1 register should be updated.

This test is a subset of muldivcor_high.

30 microSPARC-IIep Validation Catalog • July 1999 mulscc_corner_h

A directed corner case test used to verify the bug found by one of the random Kaos diagnostics. This test verifies the multiply operation by using mulscc instructions. A umulcc is followed by mulscc instruction. nabalux_v

This test verifies the rule that SuperSPARC-I cannot use condition codes calculated in E0 as input to extended precision arithmetic in the same group. This rule inserts a break between the condition code computation and its use in extended arithmetic (addx, addxcc, subx, subxcc). nabcRF

An exhaustive test to verify all the software-visible 120-integer unit registers. The test sequence is as follows: ■ Verify all the global registers. ■ Verify all the ins registers. ■ Verify all the local registers. ■ Repeat the ins and local test for other windows. ■ Both 0 and 1 patterns are toggled.

RF_test2 is another exhaustive test for register file. nabcreg_v

A diagnostic that does back-to-back read of state register instructions (read y, read wim, read tbr). To prevent the registers from being read while they are being modified, the SuperSPARC-I processor forces an extra cycle between RDPSR instructions and a previous arithmetic operation that may have changed the condition code. It would be more interesting for SuperSPARC-I based on the grouping rules and issue restrictions. This was a quick way to get diagnostics with interlocking, back-to-back mulscc instructions. nabmulscc_v

A diagnostic that does back-to-back mulscc operations. It would be more interesting for SuperSPARC-I based on the grouping rules and issue restrictions. This was a quick way to get diagnostics with interlocking, back-to-back mulscc instructions.

Chapter 3 Integer Unit Tests 31 nabrule14_v

A diagnostic that does forwarding of cascaded ALU results for memory address calculation in SuperSPARC-I. It would be more interesting for SuperSPARC-I based on the grouping rules and issue restrictions.

nabrule2_v

A diagnostic that verifies the operation of various address ports of the register file. A rule which would prevent a group from using too many register file ports. It would be more interesting for SuperSPARC-I based on the grouping rules and issue restrictions. This was a quick way to get some additional weird diagnostics for microSPARC-I. FIGURE 3-1 illustrates the test sequence.

There are 2 MEMORY-ADDR-PORTS(MP) and 2 OPERAND- PORTS(OP). MP are accessed 1 phase earlier. Store uses OP. Load uses MP. If OP1 is used, even if Immediate is used, OP2 is considered used as well. Remember that LD/ST cannot be grouped with another LD/ST because of 2 memrefs (rule 6). However, a JMPL uses OP, so this is for test4 in this case. test1 - 3-instr group. Verify tasks work. test2 - LD,LD,LD. The 3rd LD cannot be in the same group. Has used up the 2 MPs. test3 - LD,LD,ST. Can they be in the same group since LD uses MP and ST uses OP?

FIGURE 3-1 nabrule2_v Test Sequence

nabrule4_v

A diagnostic used to verify the operation of various alu ports. The memory address and target PC calculations do not use these ALU ports. It would be more interesting for SuperSPARC-I based on the grouping rules and issue restrictions.

nabrule9_v

32 microSPARC-IIep Validation Catalog • July 1999 nabsetcc2_v

A diagnostic that breaks the current instruction group before the second setcc instruction unless the second instruction is a mulscc (SuperSPARC-I allows only one condition code source, resulting in simplified exception handling). SuperSPARC- I executes mulscc either as a single instruction group, or it executes two mulscc’s as a group. It would be more interesting for SuperSPARC-I based on the grouping rules and issue restrictions. nabticcA_v

A basic test to verify two of the ticc conditions. This test verifies the trap always and trap never operation. Only 1 of the 16 possible combinations is tested. The five remaining cases cannot be verified by means of the arithmetic instructions. They are verified with the wrpsr instruction.

This test is a subset of the nabticc_v test. nabticcD_v

A basic test to verify two of the ticc conditions. This test verifies the trap on greater or equal and trap on less operation. Only 11 of the 16 possible combinations are tested. The five remaining cases cannot be verified by means of the arithmetic instructions. They are verified with the wrpsr instruction.

This test is a subset of the nabticc_v test. nabticc_v

An exhaustive test to verify all the ticc cases. Sixteen conditions are possible. For each of the 16 conditions there are 16 states of the condition codes (although not required). Eleven states of the condition code are verified by means of arithmetic instructions. The remaining 5 states of condition codes are verified by the wrpsr instruction.

There are two subsets of this test called nabticcA_v and nabticcD_v. They verify two cases each. no_bypass

A basic test used to verify where bypassing should not occur. The following cases are covered by this test: ■ No bypassing on %g0

Chapter 3 Integer Unit Tests 33 ■ No bypassing from annulled delay slots ■ No bypassing from branch (taken and untaken) instructions where the bits in the branches opcode corresponding to a Type 3 rd field indicate a register that is subsequently used ■ No bypassing from call instruction where the bits in the call opcode corresponding to a Type 3 rd field indicate a register that is subsequently used ■ No bypassing from sethi instruction where the bits in the call opcode corresponding to a Type 3 rd field indicate a register that is subsequently used ■ No bypassing between a store and alu where the read of the store is a read of a source of the ALU ■ No bypassing between a store double and alu where the read of the store is a read of source of the ALU

no_del_rett

A basic test to verify the case where the delay slot of a jmpl is a rett and the rett in missing from the instruction buffers. Two cases are tested: ■ When the jmpl and the rett transfer control to contiguous instructions. ■ When the instructions are not contiguous.

Since rett does a window restore, a stack area is established and set up in the registers. Do a save prior to each rett to make sure that there is no window underflow trap. Also, rett requires that ET (enable trap) be 0 and it will set it to 1. Therefore, set ET to 0 prior to each rett; otherwise, an illegal instruction trap occurs. S (supervisor bit) should always be 1.

page_interlock_h

A corner case test to verify the following situation.

A load is followed by an interlocking (the destination register of load is one of the source registers) add. The two instructions are on two different pages. The load is the last instruction on a user page, and the add is the first instruction on the next supervisor page. The add instruction will cause an instruction access exception.

psr1

A basic test that verifies all instructions that change the current window pointer. The instructions are wrpsr, save, restore, ticc, and rett. The test sequence is as follows: ■ Using wrpsr, check for current cwp – window five. ■ Using wrpsr, check for current cwp – window four. ■ Using wrpsr, check for current cwp – window three.

34 microSPARC-IIep Validation Catalog • July 1999 ■ Using wrpsr, check for current cwp – window two. ■ Using save instruction, check for cwp. ■ Using restore instruction, check for cwp. ■ Using trap always instruction, check for cwp. ■ Using rett instruction, check for cwp. ■ A sequence of call, save, restore instructions.

This test uses its own trap handler. rdspreg

A basic test used to verify the operation of the programmer visible state registers. The following cases are covered: ■ Write y register, followed by read y register ■ Write psr register, followed by read psr register ■ Write wim register, followed by read wim register ■ Write tbr register, followed by read tbr register ■ Write y register ■ Read y register, followed by interlocking load instruction ■ Read y register, followed by interlocking store instruction ■ Read y register, followed by interlocking load store unsigned byte instruction ■ Read y register, followed by interlocking jmpl instruction ■ Read y register, followed by interlocking load double instruction ■ Read y register, followed by interlocking store double instruction ■ Read y register, followed by floating point instruction ■ Read y register, followed by interlocking save instruction ■ Read y register, followed by interlocking restore instruction ■ Read y register, followed by interlocking trap always instruction ■ Read y register, followed by interlocking tagged add, modify icc, and trap on overflow instruction ■ Read y register, followed by interlocking tagged subtract, modify icc, and trap on overflow instruction ■ Read y register, followed by interlocking load followed by interlocking jmpl instruction readspec

A quick test to verify write to programmer-visible state registers followed by read of the register. The test sequence is as follows: ■ Write psr ■ Write wim ■ Write tbr

Chapter 3 Integer Unit Tests 35 ■ Write y ■ Read psr ■ Read y ■ Read wim ■ Read tbr

The test also includes some add and andn instructions.

rett2

A basic test to verify combinations of jump followed by rett in various situations. The following cases are covered: ■ All of the traps and the trap prioritizing that can occur on RETT:

■ Illegal instruction caused by ET=1andS=1 ■ Privileged instruction caused by S = 0 and ET = 1 ■ Privileged instruction (converted to reset) caused by S = 0 and ET = 0 ■ Window underflow (converted to reset) ■ Misaligned address (converted to reset) ■ Multicycle and other interesting targets for JMP/RETT

■ ld/st ■ ldd/std ■ ldst/ld ■ not taken branch ■ wrpsr ■ save ■ restore

This test uses its own trap handler. This test causes a watch-dog reset. This test will cause an endless loop in Verilog simulation.

rett_sps

A basic test to verify jmpl/rett will fetch instructions with the correct permission (user or supervisor). The following cases are covered: ■ Jump hits in the cache and rett misses. ■ Target of jmp hits but the target of rett misses ■ jmp and rett target misses

36 microSPARC-IIep Validation Catalog • July 1999 sdiv_byp_bug

A directed test to verify the divide bypass bug for the carry overflow bit. When a sdivcc instruction is followed by a subx/addx, the subx/addx instruction thinks the carry bit is 1, even though the sdiv/udiv instruction always sets the C bit to 0. This is an operand corner case for generation of C condition code.

The operands and sequence were discovered by a random Kaos program. The original failure occurred at 99k+ q cycles, and a directed test was written to verify the fix. shift_test

A basic test to verify the functionality of the shift unit. It does sll, srl, and sra.It checks that the result has been shifted the proper amount by examining the final register contents. Cases of small (0 or 1), large (31 or 32) and normal (type 7, 11, 21) shift amounts are done. Since the shifter only examines the low 5 bits of the shift amount, large numbers with higher bits set should only cause a shift amount equal to the number contained in the low 5 bits. The test sequence is as follows: ■ sll by small amount (0 or 1) ■ sll by big amount (32 or 31) ■ sll by normal amount (7, 11, 21) ■ srl by small amount (0 or 1) ■ srl by big amount (32 or 31) ■ srl by normal amount (7, 11, 21) ■ sra for positive number by small amount (0 or 1) ■ sra for positive number by big amount (32 or 31) ■ srl for positive number by normal amount (7, 11, 21) ■ sra for negative number by small amount (0 or 1) ■ sra for negative number by big amount (32 or 31) ■ srl for negative number by normal amount (7, 11, 21) st_divcombo

A basic test to verify the divide combination with loads and stores. The test checks the following sequences: ■ Load followed by sdiv ■ Load followed by interlocking sdiv ■ sdiv followed by load ■ Store followed by sdiv ■ sdiv followed by interlocking store

Chapter 3 Integer Unit Tests 37 test_Bicc

An exhaustive test to verify the Branch on Integer Condition Code instructions. For the 12 possible combinations of condition codes, test all of the 16 Bicc instructions.

t-s-g-i

A basic test to verify the special group (state register instructions). The test verifies the following cases: ■ Write tbr followed by read tbr ■ Write psr followed by read psr ■ Write wim followed by read wim ■ Write y followed by read y

taddcc_h

A corner case test to verify that if a taddcctv causes a tag overflow, a tag overflow trap is generated and the condition codes remain unchanged.

brfold*.s

Test different instruction categories (non-load/-store) in the delay slot of a folded branch. Following instructions are verified: add, addcc, bicc, call, mulscc, nop, rdy, restore, save, sdivcc, sethi, sll, smulcc, sub, subcc, ticc, udiv, umul, wry, xnorcc, xor

brfold1.s

A conditional taken branch.

brfold2.s

A conditional taken branch (annul on).

brfold3.s

A conditional untaken branch.

38 microSPARC-IIep Validation Catalog • July 1999 brfold4.s

A conditional untaken branch (annul on). brfold5.s

An unconditional taken branch. brfold6.s

An unconditional untaken branch. brfold7.s

An unconditional taken branch (annul on). brfold8.s

An unconditional untaken branch (annul on). brfldst*.s

Tests load and store operations in the delay slot of a folded branch. The following instructions are verified. st, ld, std, ldd, stb, ldub, sth, lduh, ldsb, ldsh, sta, lda, stda, ldda, stba, lduba, stha, lduha, ldsba, ldsha, ldstub, swap, ldstuba, swapa, stf, ldf, stdf, lddf, stfsr, ldfsr, stdfq, iflush, sta flush operations. brfldst1.s

A conditional taken branch. brfldst2.s

A conditional taken branch (annul on).

Chapter 3 Integer Unit Tests 39 brfldst3.s

A conditional untaken branch.

brfldst4.s

A conditional untaken branch (annul on).

brfldst5.s

An unconditional taken branch.

brfldst6.s

An unconditional untaken branch.

brfldst7.s

An unconditional taken branch (annul on).

brfldst8.s

An unconditional untaken branch (annul on).

brftag.s

Test tagged addition and subtraction instructions in the delay slot of a folded branch.

brftraps.s

Verifies traps generated in the delay slot of a folded branch. It uses its own trap handler. Not all trap types are tested in this diagnostic. The purpose is to verify the program counter of the IU.

40 microSPARC-IIep Validation Catalog • July 1999 brfatraps.s

A directed corner case test that verifies the bug found by one of the random Kaos diagnostics. This diagnostic verifies traps detected in the delay slot of a conditional untaken (annul on) folded branch. The diagnostic uses its own trap handler. The following traps are covered: ■ div-by-0 ■ instr-access-exception ■ data-access-exception ■ Privileged instruction ■ Illegal instruction ■ fp-disabled ■ cp-disabled ■ win-overflow ■ win-underflow ■ mem-addr-not-align ■ fp-exception ■ tag-overflow ■ Trap instruction br_traps.s

This diagnostic verifies the program counter in the IU when traps are detected before and after a branch instruction. Since traps occur before a branch instruction, that particular branch instruction is not folded. br_ilock.s

This diagnostic verifies interlock detection during unfolded bicc/call instruction. An unfolded bicc/call instruction is achieved by having this instruction in the delay slot of a folded branch. A bicc/call interlock is achieved by causing rs1 or rs2 field of the bicc/call to match the destination register of a previous load operation. This normally should not cause interlock, but since interlock is detected faster by not looking into the bicc/call opcode, this case of interlock is allowed. ldst.s

Verifies that loads and stores work correctly including bypasses. The following cases are covered: ld/ldd, ldd/ld, st/std, std/st, ld/st, ldd/st, ld/std, ldd/stdld/nop/st, ldd/nop/st, ld/nop/std, ldd/nop/std, ld/bicc/st, ldd/bicc/st, ld/bicc/std, ldd/bicc/std