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Microsparc-Iiep™ Validation Catalog

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Microsparc-Iiep™ Validation Catalog microSPARC-IIep™ Validation Catalog Sun Microsystems, Inc. 901 San Antonio Road Palo Alto, CA 94303 USA 650 960-1300 Part No.: 851-2430 Revision: 01 July 1999 Copyright © 1999 Sun Microsystems, Inc. All rights reserved. The contents of this documentation is subject to the current version of the Sun Community Source License, microSPARC-II ("the License"). You may not use this documentation except in compliance with the License. You may obtain a copy of the License by searching for "Sun Community Source License" on the World Wide Web at http://www.sun.com. See the License for the rights, obligations, and limitations governing use of the contents of this documentation. Sun Microsystems, Inc. has intellectual property rights relating to the technology embodied in this documentation. In particular, and without limitation, these intellectual property rights may include one or more U.S. patents, foreign patents, or pending applications. Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, Solaris, Java and all Java-based trademarks and logos are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. microSPARC is a trademark or registered trademark of SPARC International, Inc. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. an architecture developed by Sun Microsystems, Inc. THIS PUBLICATION IS PROVIDED "AS IS" AND ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD TO BE LEGALLY INVALID. THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOGRAPHICAL ERRORS. CHANGES ARE PERIODICALLY ADDED TO THE INFORMATION HEREIN; THESE CHANGES WILL BE INCORPORATED IN NEW EDITIONS OF THE PUBLICATION. SUN MICROSYSTEMS, INC. MAY MAKE IMPROVEMENTS AND/OR CHANGES IN THE PRODUCT(S) AND /OR THE PROGRAM(S) DESCRIBED IN THIS PUBLICATION AT ANY TIME. Please Recycle Contents 1. Introduction 1 1.1 microSPARC-IIep Blocks 1 1.2 microSPARC-IIep Diagnostic Style 1 1.3 microSPARC-IIep Diagnostic Modes 2 2. Diagnostic Environment 5 2.1 Test Environment 5 2.2 Memory Environment 5 2.2.1 Tests Using the Assembly to Verilog tool 6 2.3 PCI Environment 9 3. Integer Unit Tests 13 4. Floating-point Unit Tests 47 5. Memory Management Unit Tests 77 6. Instruction and Data Cache Tests 105 7. Memory Interface Unit Tests 113 7.1 FlashPROM Controller 8-bit Tests 116 7.2 FlashPROM Controller 32-bit Tests 117 Contents iii 8. PCI Controller Unit Tests 119 9. Random Diagnostic Tests 133 Index 135 iv microSPARC-IIep Validation Catalog • July 1999 Preface The book, microSPARC-IIep Validation Catalog, is one of a four-manual documentation set for the microSPARC-II technology. The other three manuals are: • Multiprocessor SPARC Architecture Simulator (MPSAS) User’s Guide, describes how to use the MPSAS and its associated programs. • Multiprocessor SPARC Architecture Simulator (MPSAS) Programmer’s Guide explains the facilities for creating or modifying MPSAS modules or otherwise extending MPSAS. • microSPARC-IIep Megacell Reference explains how to build microSPARC-IIep megacells. Organization of This Book This book is intended for programmers who develop and debug programs to be run the microSPARC-IIep. It is arranged as follows: Chapter 1, "Introduction," introduces the microSPARC-IIep validation catalog. Chapter 2, "Diagnostic Environment," describes the diagnostic environment used for microSPARC-IIep verification. Chapter 3, "Integer Unit Test," identifies the integer unit validation test suites. Chapter 4, "Floating-point Unit Tests," covers the microSPARC-IIEp floating- point unit diagnostic tests. v Chapter 5, "Memory Management Unit Tests," describes the diagnostic tests for the memory management unit. Chapter 6, "Instruction and Data Cache Tests," describes the instruction and data cache validation test suites. Chapter 7, "Memory Interface Unit Tests," covers the memory interface unit diagnoztics. Chapter 8, "PCI Controller Unit Tests," covers the PCI controller unit tests. Chapter 9, "Random Diagnostic Tests," describes the diagnostic test randomly generated using the thrash process. Prerequisite Knowledge It is assumed that you are familiar with programming in the C language in the UNIX® environment and that you have a basic familiarity with computer architecture, in particular the SPARC architecture. For further information, see the list of documents in the following section. Related Books and References The following documents contain material that further explains or clarifies information presented in this guide. The SPARC V8 Architecture Manual SunOS Reference Manual: Section 1, User Commands The C Programming Language by Brian W. Kernighan and Dennis M. Ritchie, Prentice Hall; ISBN: 0131103628 vi microSPARC-IIep Validation Catalog • July 1999 Typographic Conventions The following table describes the typographic conventions used in this book. Table P-1Typographic Conventions Typeface or Symbol Meaning Example AaBbCc123 The names of commands, instructions, files, Edit your .login file. and directories; on-screen computer output; Use ls -a to list all files. email addresses; URLs machine_name% You have mail. AaBbCc123 What you type, contrasted with on-screen machine_name% su computer output Password: AaBbCc123 Command-line placeholder: To delete a file, type rm filename. replace with a real name or value AaBbCc123 Book titles, section titles in cross-references, Read Chapter 6 in User’s Guide. new words or terms, or emphasized words These are called class options. You must be root to do this. Sun Documents The SunDocsSM program provides more than 250 manuals from Sun Microsystems, Inc. If you live in the United States, Canada, Europe, or Japan, you can purchase documentation sets or individual manuals by using this program. For a list of documents and how to order them, see the catalog section of the SunExpress™ Internet site at http://www.sun.com/sunexpress. Sun Documentation Online The docs.sun.com Web site enables you to access Sun technical documentation online. You can browse the docs.sun.com archive or search for a specific book title or subject. The URL is http://docs.sun.com/. Disclaimer The information in this manual is subject to change and will be revised from time to time. For up-to-date information, contact your Sun representative. Preface vii viii microSPARC-IIep Validation Catalog • July 1999 CHAPTER 1 Introduction The microSPARC-IIep is a highly integrated, low-cost, low-power implementation of the SPARC V8 RISC architecture. High performance is achieved by the high level of integration including on-chip instruction and data caches, and close coupling of the CPU with main memory. A full custom implementation allows for a target frequency of 70 MHz and 150 MHz, providing sustained performance of 42 and 84 Specmarks, respectively. The design is highly testable with the use of the full JTAG scan support. The microSPARC-IIep supports up to 256 Mbytes of DRAM and four 32-bit 33 MHz PCI slots. 1.1 microSPARC-IIep Blocks This catalog contains descriptions of the diagnostics used in the architectural verification of microSPARC-IIep. Explanations are provided for the individual test cases.The diagnostics are divided into the following sections: ■ Integer Unit ■ Floating-Point Unit ■ Memory Management Unit ■ Instruction Cache and Data Cache ■ Memory Interface Unit ■ PCI Controller ■ Random Tests 1.2 microSPARC-IIep Diagnostic Style The microSPARC-IIep diagnostics can be classified into two categories: 1 ■ Non-asm2ver style: contains no notion of Reference MMU and thereby always runs with the MMU disabled. ■ asm2ver style: contains a notion of Reference MMU. The MMU is enabled and the process allows for mapping of virtual pages. Many of the diagnostics are self-checking and do not require Microprocessor SPARC Architecture Simulator (MPSAS) support (option -n sas on run script). MPSAS performs rudimentary modeling of the PCI (just a memory), so most tests of the PCI are self-checking for that reason. 1.3 microSPARC-IIep Diagnostic Modes The microSPARC-IIep diagnostics make use of a concept called “mode.” A mode is a way of enabling or disabling some of the major functional blocks of microSPARC- IIep. The following modes are used in the microSPARC-IIep: ■ c_pa_reset: cacheable physical address (cpa) prevents virtual to physical address translation. ■ tlb_reset: translation look-aside buffer (tlb) register mode with one TLB entry. Causes thrashing of the TLB for extra traffic on the internal memory bus. ■ tlb32_reset: translation look-aside buffer (tlb) register mode configured to operate with all 32 entries. The TLB replacement counter is enabled and the entries are replaced using a pseudorandom algorithm. ■ nc: no cache (nc) mode with reset environment. In this mode, the microSPARC- IIep is configured so that the Instruction Cache and Data Cache are both disabled. All memory references miss the cache. This mode resets the Instruction Cache Enable and Data Cache Enable bits in the Processor Control Register. ■ nic: no instruction cache (nic) mode with reset environment. In this mode, the microSPARC-IIep is configured so that the Instruction Cache is disabled. All instruction accesses to the cache cause a miss. This mode resets the Instruction Cache Enable bit in the Processor Control Register. ■ ndc: no data cache (ndc) mode with reset environment. In this mode, the microSPARC-IIep is configured so that the Data Cache is disabled. All data accesses to the cache cause a miss. This mode resets the Data Cache Enable bit in the Processor Control Register. ■ fastrfr: refresh (rfr) mode with reset environment. In this mode, the microSPARC-IIep is configured so that the external DRAM refresh rate is the fastest. The microSPARC-IIep generates a refresh cycle every 128 clocks. This mode resets the Refresh Control bits [1:0] in the Processor Control Register. 2 microSPARC-IIep Validation Catalog • July 1999 ■ s: standby (s) assert/deassert randomly the power-down mode pin.
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