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Microsparc™-Iiep User's Manual

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Microsparc™-Iiep User's Manual microSPARC™-IIep User’s Manual April 1997 - microSPARC-IIep User’s Manual April 1997 Sun Microelectronics 2550 Garcia Avenue Mountain View, CA U.S.A. 94043 1-800-681-8845 www.sun.com/sparc Part Number: 802-7100-01 Copyright © 1997 Sun Microelectronics All Rights Reserved. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED “AS IS” WITHOUT ANY EXPRESS REPRESENTATIONS OR WARRANTIES. IN ADDITION, SUN MICROELECTRONICS DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WARRANTIES, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON- INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. This document contains proprietary information of Sun Microelectronics or under license from third parties. No part of this document may be reproduced in any form or by any means or transferred to any third party without the prior written consent of Sun Microelectronics Sun, Sun Microsystems, and the Sun logo are trademarks or registered trademarks of Sun Microelectronics in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microelectronics The information contained in this document is not designed or intended for use in on-line control of aircraft, air traffic, aircraft navigation or aircraft communications; or in the design, construction, operation or maintenance of any nuclear facility. Sun disclaims any express or implied warranty of fitness for such uses. Printed in the United States of America. Contents 1. microSPARC-IIep Overview . 1 1.1 Introduction. 1 1.2 microSPARC-IIep Memory Map . 3 1.3 Endian Support . 4 1.3.1 Processor-to-System Memory Endian Conversion. 4 1.3.2 Processor-to-PCI Endian Conversion. 6 1.3.3 Settings for Endian Conversion . 7 1.3.3.1 Big Endian Environment . 7 1.3.3.2 Little Endian Environment . 8 1.4 Block Diagram. 8 2. CPU Performance. 11 2.1 Benchmark Test Results . 11 2.1.1 Benchmark Test Setup . 12 2.1.2 SPECint92 Test Results . 12 2.1.3 SPECfp92 Test Results . 13 2.1.4 Dhrystone Test Results . 13 2.2 Compiler Optimization Guidelines . 13 2.2.1 Branches . 13 2.2.2 Guidelines for Branch Folding . 14 2.2.3 Multicycle Instructions . 16 2.2.4 Pipeline Interlocks . 17 microSPARC-IIep User’s Manual — April 1997 i 2.2.5 Other Guidelines . 17 2.2.6 Floating-Point Instructions . 17 2.2.6.1 FP Interlocks . 18 2.2.6.2 Functional Units . 18 2.2.6.3 FP Queue Details . 18 2.2.7 Loads and Stores . 21 2.2.8 General Techniques . 22 2.3 Using the Two Page-Hit Registers . 22 3. Integer Unit. 25 3.1 Overview . 25 3.2 Instruction Pipeline . 27 3.3 Memory Operations . 28 3.3.1 Loads . 28 3.3.2 Stores . 30 3.3.3 Atomic Operations . 30 3.4 ALU/Shift Operations . 31 3.5 Integer Multiply . 32 3.6 Integer Divide . 32 3.7 Control-Transfer Instructions . 33 3.7.1 Branches . 33 3.7.2 JMPL . 34 3.7.3 RETT . 35 3.7.4 CALL . 35 3.8 Instruction Cache Interface . 35 3.9 Data Cache Interface. 36 3.10 Interlocks . 36 3.10.1 Load Interlock. 36 3.10.2 Floating Point Interlocks . 36 3.10.3 Miscellaneous Interlocks . 37 3.11 Traps and Interrupts. 37 3.11.1 Traps. 37 3.11.2 Interrupts. 38 3.11.3 Reset Trap . 39 ii microSPARC-IIep User’s Manual — April 1997 3.11.4 Error Mode . 40 3.12 Floating-Point Interface . 40 3.13 Compliance With SPARC Version 8 . 41 4. Floating-Point Unit . 43 4.1 Overview . 44 4.2 Deviations from SPARC version 8 . 49 4.3 Implementation Specific Features. 50 4.3.1 fp_execute State . 51 4.3.2 fp_exception_pending State . 51 4.3.3 fp_exception State . 52 4.3.4 STDFQ Instruction . 52 4.4 Software Considerations . 52 4.5 FP Performance Factors . 54 5. Memory Management Unit . 57 5.1 Overview . 58 5.2 MMU Programming Interface. 60 5.3 Reference MMU Registers (ASI=0x04) . 60 5.3.1 Processor Control Register (VA[12:8]=0x00). 61 5.3.2 Context Table Pointer Register (VA[12:8]=0x01). 63 5.3.3 Context Register (VA[12:8]=0x02) . 64 5.3.4 Synchronous Fault Status Register (VA[12:8]=0x03, VA[12:8]=0x13) . 64 5.3.5 Synchronous Fault Address Register (VA[12:8]=0x04, VA[12:8]=0x14) . 69 5.3.6 TLB Replacement Control Register (VA[12:8]=0x10). 70 5.4 TLB Table Walk . 71 5.5 Translation Lookaside Buffer (TLB) . 73 5.5.1 TLB Replacement . 74 5.5.2 TLB Entry . ..
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