Microprocessors We Saw in 1996

Integrated Circuit Engineering Corporation

MICRMICROPROPROCESSORSOCESSORS

Deservedly still the technology leader category we believe (although the Siemens’ 64Mb DRAM may make this too close to call).

Again this year this product category provided not only the most complex metal interconnect technology (Motorola), but also the shortest gates (Motorola)!

So, Motorola appears to definitely be “in the game” and gets our vote for “most improved” technology this year.

Intel’s Pentium Pro and IBM PC601+ seem to be “mature” technologies at this point.

The UltraSparc from SUN included here has a somewhat unfair disadvantage, it is about a year older technology, (since we seem to be unable to obtain any late model devices). Hewlett Packard also remains shrouded in mystery (shyness?).

Now, if all these manufacturers could only catch DEC Alpha’s speed!

5-1 Integrated Circuit Engineering Corporation m m m m µ µ µ µ ) 2 + + 2 m* m m m/1.8 m/0.9 m/0.9 m/0.9 m m µ µ µ m µ µ µ µ µ µ µ SUN Ultra Sparc 64 Bit RISC 9528 17.7 x 17.8mm (315mm NA NA 2.0 0.8 0.8 0.8 0.7 0.7 0.45 0.45 0.45 64 m m m m m µ µ µ ❷ µ µ ) 2 + + 2 m/0.8 m/0.8 m/0.7 m m* m m m/1.4 m/0.9 m/NA m µ µ µ µ µ µ µ m µ µ µ µ µ IBM 6X86 32 Bit CISC 1996 13.3 x 14.6mm (194mm 1.7 0.75 0.65 0.6 0.55 0.7 0.65 0.7 0.35 0.35 0.35 44 m m m m µ µ µ µ ) 2 + + 2 m/0.4 m m/2.0 m/0.55 m/0.55 m m* m m µ µ m µ µ µ µ µ µ µ µ INTEL Pentium Pro 64 Bit CISC 1996 14 x 14mm (196mm NA NA 2.0 0.6 0.6 0.55 0.5 0.55 0.3 0.3 0.3 49 able 5-1 T m m m m µ µ µ µ ) 2 + + 2 m m m/2.6 m/2.6 m/0.8 m/0.8 m m m µ µ m µ µ µ µ µ µ µ µ DEC Alpha 21164 64 Bit RISC 1996 16.8 x 18.6mm (313mm NA NA 3.4 2.2 1.2 1.2 0.5 0.6 0.35 0.4 0.45 43 See text ❷ ❶ m m m µ m m m µ µ µ µ µ ) Active area 2 + + ❶ 2 m/0.75 m m m* m m m/2.0 m/0.7 m/0.65 m/0.75 m/0.5 µ µ µ µ µ µ m µ µ µ µ µ µ MOTOROLA MPC 604e 64 Bit RISC 1996 x 12.9mm 11.7 (148mm 3.0 1.0 1.1 1.0 0.8 0.55 0.55 0.55 0.25 0.25 0.25 36 Plugs Plugs + HORIZONTAL DIMENSIONS (DESIGN RULES) HORIZONTAL † † (Met. to Si) Physical gate length † (Met. to Met) CPUs Polycide Die size Min. M6 width/space Min. M5 width/space Min. M4 width/space Min. M3 width/space Min. M2 width/space Min. M1 width/space Min. via Min contact Min. Poly Min. gate-(N) Min. gate-(P) Cache Cell * Integrated Circuit Engineering Corporation m* m m m m m m m µ µ µ µ µ µ µ µ m m (P) µ µ ❶ SUN Ultra Sparc 64 Bit RISC 9528 2.0 NA NA 1.3 0.8 0.8 0.8 0.6 0.25 0.55 2 ? 6 ❸ ❷ m m m m m* m m m m µ µ µ µ µ µ µ µ µ m m (P) µ µ ❶ IBM 6X86 32 Bit CISC 1996 1.0 NA 0.9 0.85 0.8 0.65 0.65 0.75 0.15 0.4 1 ? 2 S N O I ❷ m m m* S m m m m m µ µ µ µ µ µ µ µ m m (P) µ µ ❶ N INTEL Pentium Pro 64 Bit CISC 1996 0.7 NA NA 1.9 0.85 0.8 0.6 0.45 0.35 0.4 1 ? 2 E M I D able 5-2

T L ❷ m m m m m m m* m m (P) A µ µ µ µ µ µ µ µ µ ❶ ❶ 0.7 NA NA 1.6 1.6 0.9 0.9 1.2 0.3 0.4 ? ? 2.5 DEC Alpha 21164 64 Bit RISC 1996 C I T R See text ❸ E V ❷ m m m m m m m m m m* m (P) µ µ µ µ µ µ µ µ µ µ µ m µ ❶ MOTOROLA MPC 604e 64 Bit RISC 1996 1.0 1.8 0.7 0.7 0.65 0.7 0.8 0.7 0.2 0.55 1 ? 2.5 Shallow trench

❷ Could not delineate

❶ CPUs Polycide

Final passivation Metal 6 Metal 5 Metal 4 Metal 3 Metal 2 Metal 1 Pre-metal dielectric Poly Recessed oxide N-well P-well Epi *

Integrated Circuit Engineering Corporation † + + Nitride on glass NA NA Titanium-Nitride Aluminum Titanium-Nitride Same as Metal 4 Same as Metal 4 Same as Metal 4 Tungsten Tungsten glass w SOG glass titanium* SUN Ultra Sparc 64 Bit RISC 9528 † ❶ + + Nitride on glass Titanium-Nitride Aluminum Titanium Same as Metal 6 Same as Metal 6 Same as Metal 6 Same as Metal 6 Tungsten Tungsten Tungsten glass glass/nitride titanium* IBM 6X86 32 Bit CISC 1996 † + + Nitride NA NA Titanium-Nitride Aluminum Titanium Same as Metal 4 Same as Metal 4 Same as Metal 4 Tungsten Tungsten glass glass titanium* INTEL Pentium Pro 64 Bit CISC 1996 Table 5-3 Table + + † DEC Alpha 21164 64 Bit RISC 1996 glass NA NA Titanium-Nitride Aluminum Titanium-Nitride Same as Metal 4 Same as Metal 4 Same as Metal 4 Tungsten Tungsten glass w SOG glass Layered cobalt* DIE MATERIALS † + + Nitride on glass Aluminum Titanium-Nitride Aluminum Titanium-Nitride Titanium Same as Metal 5 Same as Metal 5 Same as Metal 5 Tungsten Tungsten Tungsten glass glass/nitride titanium* MOTOROLA MPC 604e 64 Bit RISC 1996 metal

† See text

❶ salicide / * (metal to silicon) CPUs (metal to metal) Plugs + Contact Intermetal dielectric Pre-metal dielectric Polycide Final passivation Metal 6 Metal 5 Metal 4 Metal 3 Metal 2 Metal 1 Via Motorola Power PC604e Integrated Circuit Engineering Corporation

TECHNOLOGY DESCRIPTION

MOTOROLA MPC604e 64-BIT RISC MICROPROCESSOR

Introduction Ref. report SCA 9607-486

The part was packaged in a 256-pin (255 actual) ceramic ball grid array package. A date code was not identifiable but the devices were undoubtedly fabbed in 1996. The device has on-chip 32Kbyte instruction and data cache memory arrays, a 64-bit external data bus, 32-bit address bus, and runs at 166MHz.

See tables for specific dimensions and materials identification and see figures for examples of physical structures.

Important/Unique Features

– The most advanced microprocessor technology seen in 1996!

– Very aggressive feature size (0.25 micron gates).

– Six metal process (five aluminum, one tungsten).

– High degree of planarization (CMP).

– Shallow trench isolation.

– “C4” flip-chip design with solder bumps.

Quality

Quality of the process implementation was very good and we found no areas of concern.

In the area of layer patterning, etch definition and control were both good.

Alignment and registration were also good.

5-2 Motorola Power PC604e Integrated Circuit Engineering Corporation

Technology

The device was manufactured by a shallow trench oxide isolation twin (multiple)-well CMOS process in a P-epi on a P substrate. It is the first example we’ve seen of an IBM style process fabbed by Motorola. Final passivation consisted of a layer of nitride over a layer of silicon dioxide.

This device incorporated six levels of metal. Metals 2 - 6 were defined by dry-etch techniques (no damascene) and consisted of aluminum with titanium-nitride caps and barriers on thin titanium adhesion layers, except for metal 6 which had no cap or barrier. Metal 1 consisted of tungsten and was defined using a damascene process. It was used for local interconnect.

Metal 6 used standard vias to connect to metal 5. Tungsten plugs (some elongated) were used for vertical interconnects between metals 2 - 5, and were stacked where needed.

Planarization of the interlevel dielectric 5 (between M5 and M6) consisted of a layer of deposited glass (possibly TEOS) which was subjected to an etchback, then followed by a thin layer of deposited glass (no SOG). Interlevel dielectrics 2 - 4 each consisted of a layer of deposited glass followed by a thick layer of glass that was planarized by CMP, and another layer of glass that was planarized by the CMP process that leveled the tungsten plugs. Interlevel dielectric 1 consisted of a thick layer of glass which was also planarized by the tungsten plug leveling CMP. Planarization of the “pre-metal” dielectric (which in this process surrounds metal 1) was done using a thick layer of silicon-dioxide (subjected to CMP) followed by a thin layer of silicon- dioxide. Again here also the thin layer was planarized as part of the tungsten planarizing CMP. A thin nitride “sealing layer” was present under the “pre-metal” covering all active areas. No evidence of any spin-on-glass (SOG) was found anywhere.

A single layer of titanium-silicided polysilicon (polycide) was used for all gates on the die.

Sidewall spacers were of nitride, providing both the spacing for the LDD requirements as well as separation between gate edges and the metallized (salicide process) source/drain diffusions. The same material (titanium) was used at sources/drains as for siliciding the polysilicon.

Buried contacts were not used, the metal 1 tungsten being used for connecting poly to diffusions.

No evidence of unusual gate oxides was found, but shallow trench oxide isolation was employed and well implemented.

5-3 Motorola Power PC604e Integrated Circuit Engineering Corporation

Redundancy fuses made with metal 5 were present, but no blown links were found. Passivation and oxide cutouts were present over the fuses.

Cache memory cells consisted of a six transistor CMOS SRAM cell design. Metal 3 formed the bit lines (via metals 1 and 2). Metal 2 formed “piggyback” word lines and distributed Vcc and GND (via metal 1). This SRAM had a 36 microns2 cell size, the smallest seen on any microprocessor this year.

Overall minimum feature size measured anywhere on this die was the 0.25 micron polycide (gates). This represents the smallest feature size found on any microprocessor product in 1996!

Packaging/Assembly

As mentioned, the part was packaged in a 256-pin (255 actual) ceramic ball grid array package.

No decoupling capacitors were present outside or inside the package. The die was mounted using a flip-chip design (“C4”) incorporating solder bumps. A thin protective coating (under- fill) was present between the ceramic substrate and the die surface. A spun-on patterned, polyimide die coat covered the active die surface, but was not present over the test array along the edge of the die. Bond pads employed a barrier/interface metal (CuSn) for good solder adhesion. Solder ball pads on the die were 130 microns wide with 115 micron spacing.

The die had a large array of test devices attached. Die size including this array was 166 mm2.

This part (package and process) incorporates the most advanced “state-of-the-art” features found on any microprocessors we saw in 1996.

5-4 Motorola Power PC604e Integrated Circuit Engineering Corporation

Whole die photograph of the Motorola Power PC604e. Mag. 14x. Motorola Power PC604e Integrated Circuit Engineering Corporation

METAL 6

METAL 5 METAL 3

METAL 4 METAL 3 PLUG

METAL 2 PLUG

METAL 4 PLUG METAL 2

METAL 1

N+ S/D

Silicon etch view illustrating general structure. Mag. 6000x.

NITRIDE Ti-SILICIDE NITRIDE SIDEWALL SPACER

POLY Ti-SALICIDE

SEM section view of SRAM N-channel storage gate. Glass etch, Mag. 52,000x. Motorola Power PC604e Integrated Circuit Engineering Corporation

METAL 5 FUSE LINK

ILD 4 METAL 5 PLUG

METAL 4

SEM section view of a metal 5 fuse. Mag. 15,000x.

METAL 2 PLUGS

METAL 1 Mag. 8000x METAL 1

DIFFUSION

Mag. 6000x

TRENCH OXIDE

SEM views of metal 1 and poly. 60°. DEC Alpha AXP21164 Integrated Circuit Engineering Corporation

TECHNOLOGY DESCRIPTION

DIGITAL EQUIPMENT CORPORATION ALPHA AXP 21164 64-BIT RISC MICROPROCESSOR

Introduction Ref. report SCA 9604-455

Five loose dice were received for this analysis. Four of these were supplied by DEC. Date codes were thus not available, however, the parts were definitely manufactured in early 1996. This processor is a high-performance implementation of Digital’s Alpha AXP architecture. It incorporates 8Kbyte instruction and data Caches and a 96Kbyte second level (L2) Cache. As far as we know it was the highest speed microprocessor available in 1996, operating at 300MHz.

See tables for specific dimensions and materials identification and see figures for examples of physical structures.

Important/Unique Features

– Cobalt used for silicides.

– Titanium-nitride local interconnect used in the Cache SRAM arrays.

– Shallow trench isolation.

– Use of the M4 TiN barrier for redundancy fuses (current blown).

– Non-CMP planarization.

Quality

Quality of the process implementation was very good and we found no areas of concern.

In the area of layer patterning, etch definition and control were both good.

Alignment and registration were also good.

5-5 DEC Alpha AXP21164 Integrated Circuit Engineering Corporation

Technology

These devices were manufactured by a twin (multiple)-well CMOS process in a P-epi on a P substrate.

Final passivation consisted of a single layer of silicon-dioxide.

They incorporated four levels of metal plus one layer of local interconnect, one layer of cobalt- polycide, and cobalt-silicided source/drain diffusions (salicide process). All four metal layers were defined by dry-etch techniques (no damascene) and consisted of aluminum with titanium- nitride caps and barriers. A thin titanium-nitride layer was used in the Cache cell arrays as poly-to-diffusion (local) interconnect, and to strap diffusions. This type of local interconnect is unique to DEC.

Another unique feature on these devices was the use of the titanium-nitride used for the M4 barrier to form redundancy fuses. A window cut-out over the fuse areas removed the passivation, the cap metal and the Aluminum 4. It appeared the fuses were intended to be activated by current blowing rather than laser.

Tungsten plugs were used for all vertical interconnects. Plugs were not stacked and implementation was good. All plugs used titanium-nitride liners both below and above (i.e., two separate depositions). The liner above the plugs was in fact the barrier metal under the next level of aluminum interconnect.

Planarization of the interlevel dielectrics was by alternating layers of silicon-dioxide (TEOS?), with spin-on-glass (SOG) which was etched back to form complex but well planarized surfaces for M4, M3, and M2. Planarization under M1 was by three layers of silicon dioxide (TEOS?) and etchback (no reflow) with equally good results.

A single layer of cobalt-silicided polysilicon (polycide) was used for all gates on the die. The use of cobalt is unique to DEC as far as we know.

Sidewall spacers on the gates were of silicon-dioxide, providing both the spacing for the LDD requirements (apparently double-diffused) as well as separation between gate edges and the metallized source/drain diffusions (salicide process). The same material (cobalt) was used for silicide on sources/drains as for siliciding the polysilicon. Sidewall spacers had been etched back so only a minimal amount of the spacer was still present.

¥ Sidewall spacers had been back etched, so only a minimal amount of the spacer was still present. The purpose of this was not fully understood. 5-6 DEC Alpha AXP21164 Integrated Circuit Engineering Corporation

Standard buried contacts were not used. Instead, the thin titanium-nitride (TiN) local interconnect layer was used in the cell array to connect polycide to diffusion. To improve speed (a key feature of this part type), this TiN is also used to further strap the (salicided) source/drain diffusions in the Cache arrays.

No evidence of unusual gate oxides or other dielectrics was found but shallow trench oxide isolation was employed (and well implemented) instead of the local oxide (LOCOS) used on the earlier version of this party type.

All on-chip Cache memory cells (8Kbyte + 8Kbyte + 96Kbyte) used a six transistor CMOS SRAM design thus requiring multiple wells in the arrays but making a second poly unnecessary. Metal 2 formed the bit lines using metal 1 links. Metal 1 distributed GND and Vcc and as mentioned a thin layer of titanium-nitride provided local interconnect and diffusion strap- ping. Metals 3 and 4 were not used directly in these arrays. No other unusual features were present. This design resulted in a 43 micron2 cell size, quite small for these design rules.

Overall minimum feature size measured anywhere on these dice was the 0.35 micron polycide and the 0.4 micron gates.

Packaging/Assembly

As mentioned, the devices analyzed were unpackaged (loose dice), but provisions for assembly consisted of wirebond pads only (no solder ball bonds). A thin, even thickness, patterned polyimide die coat was present.

Wirebond pads on the die were on a 110 micron pitch using 100 micron wide pads (90 micron windows) with 10 micron spaces. Bond pads utilized all four metal layers interconnected over the entire area using tungsten plugs.

5-7 DEC Alpha AXP21164 Integrated Circuit Engineering Corporation

L1 D CACHE

L2 CACHE L2 CACHE

L1 CACHE

Whole die photograph of the DEC Alpha AXP21164 Microprocessor. Mag. 10x. DEC Alpha AXP21164 Integrated Circuit Engineering Corporation

PASSIVATION

METAL 4 M4 PLUG

METAL 3 Mag. 6500x

METAL 1 METAL 2 POLYCIDE GATES M1 PLUG N+ S/D

Mag. 12,000x

M1 PLUGS POLYCIDE

DIFFUSION

CUT-OUT

intact, Mag. 6000x, 50° TiN (M4 BARRIER)

SEM section views of general devices structures and titanium-nitride fuse. DEC Alpha AXP21164 Integrated Circuit Engineering Corporation

POLYCIDE WORD LINE

delayered, M1 PLUGS Mag. 8000x, 60°

TiN INTERCONNECT

delayered, Mag. 25,000x POLYCIDE

M1 PLUG

TiN STRAP P+

METAL 1

TiN POLYCIDE GATE perpendicular to bit lines, M2 Mag. 27,000x PLUG

TRENCH OXIDE

N+ S/D

Perspective and section SEM views of the Cache SRAM array. Intel Pentium Pro Integrated Circuit Engineering Corporation

TECHNOLOGY DESCRIPTION

INTEL PENTIUM PRO 64-BIT CISC MICROPROCESSOR

Introduction Ref. report SCA 9603-453

The part was packaged in a 387-pin, multi-chip, ceramic-lid, Pin Grid Array (PGA). A date code was not identifiable, but the die was probably fabbed in 1996 (early). The package cavity contained both the P6 processor die and the Level 2 Cache SRAM die. A large heatsink and attached fan were used for heat dissipation. This device runs at 200MHz.

See tables for specific dimensions and materials identification and see figures for examples of physical structures.

Important/Unique Features

– Multi-chip PGA with twin-cavity.

– BiCMOS process.

– Unique tungsten plugs with “stubs” buried into the aluminum below.

– CMP planarization and shallow trench isolation.

– Aggressive feature sizes (0.3 micron gates and 0.95 micron metal 1 pitch).

Quality

Quality of the process implementation was very good and we found no areas of concern.

In the area of layer patterning, etch definition, and control (depth) were both good.

5-8 Intel Pentium Pro Integrated Circuit Engineering Corporation

Alignment and registration were also good.

Technology

These devices were manufactured by a twin (multiple)-well BiCMOS process in a P-epi on a P substrate. The fact that it was a BiCMOS process came as a surprise since it was expected that Intel would switch to straight CMOS for the P6 family. Final passivation consisted of a single layer of nitride.

Four levels of metal defined by dry-etch techniques (no damascene) were used. They consisted of aluminum with titanium-nitride caps and thin titanium barrier/adhesion layers.

Tungsten plugs (not stacked) were used for all vertical interconnects. Plugs under metals 2 - 4 employed tungsten “stubs” at the bottom of the tungsten plugs. These unique features consist of stubs of tungsten plug metallization that penetrate into the underlying aluminum. They were lined with a titanium-nitride layer. Presumably, this plug structure indicates a problem at Intel in obtaining good, reliable plug-to-metal interface connections. We say this because the structures appear to require enlarging the metal surround area under all plugs resulting in larger “contacted” metal pitch. However, metal on top of the plugs can be, and is in many places, coincidental with plug diameter. Intel’s capability in patterning offsets this pitch problem by providing non-contacted pitch that was the most aggressive seen in 1996 (0.95 micron)!

Planarization of the interlevel dielectrics was by depositing a very thin glass, followed by two thick layers of glass. The uppermost layer of glass was subjected to CMP planarization which left a very planar surface. Planarization under the M1 was formed using a thick layer of silicon-dioxide followed by a thin layer of glass. This layer also appeared to have been planarized by CMP. No spin-on-glass was used anywhere.

A single layer of titanium-silicided polysilicon (polycide) were used for all gates of MOS devices and as N+ diffusion sources for the emitters of the bipolar devices.

Sidewall spacers were of nitride, providing both the spacing for the LDD requirements as well as separation between gate edges and the metallized (salicide process) source/drain diffusions.

5-9 Intel Pentium Pro Integrated Circuit Engineering Corporation

The same material (titanium) was used at sources/drains and for siliciding the polysilicon.

Buried contacts were not used (except at bipolar transistor emitters). A local interconnect was also not present.

No evidence of unusual gate oxides or other dielectrics was found, but shallow trench oxide isolation was employed and well implemented.

No redundancy fuse elements were found on this device.

As mentioned, a separate 256K L2 Cache RAM die was present in the package, however; the CPU die did have on-chip data and instruction cache memory arrays (8K each). These employ an unusual six transistor design. Metal 2 formed the word lines and distributed GND (via metal 1). The word lines also made diode connections to the P-wells at every cell. Metal 1 distributed Vcc, formed the bit lines and provided cell interconnect. Resulting cell size was 49 microns2.

Overall minimum feature size measured was the 0.3 micron polycide (gates).

Packaging/Assembly

As mentioned, the part was packaged in a 387-pin, multi-chip, ceramic-lid Pin Grid Array (PGA). No decoupling capacitors were present outside or inside the package. Die attach was by a gold-silicon eutectic. Wirebonding employed aluminum wire and ultrasonic wedge bond- ing to two-tiered package lands. Wirebond pads on the die were on an 85 micron pitch using 80 micron wide pads (65 micron windows) with only 5 micron spaces. This is the closest pitch and spacing found on any microprocessor product.

5-10 Intel Pentium Pro Integrated Circuit Engineering Corporation

PROCESSOR LEVEL 2 CACHE

delidded, Mag. 1.2x

PASSIVATION

PLUG 4 METAL 4

METAL 3 METAL 2

METAL 1

POLYCIDE PLUG 1

N+ S/D

Mag. 8000x Package photograph and general structure views of the Pentium Pro. Intel Pentium Pro Integrated Circuit Engineering Corporation

Photograph of the Pentium Pro die. Mag. 13x. Intel Pentium Pro Integrated Circuit Engineering Corporation

METAL 3

INTERLEVEL DIELECTRIC 2 W PLUG

METAL 2 “STUB”

glass etch, Mag. 27,000x

Mag. 8000x, 60° Section and perspective SEM views of unique via plugs and polycide gates. Intel Pentium Pro Integrated Circuit Engineering Corporation

WORD

BIT

metal 1, Mag. 10,000x, 0° BIT

WORD

VCC

GND GND

VCC

6 4 VCC

polycide, Mag. 10,000x, 0° WORD BIT 1 2 5 3 BIT GND

WORD GND

POLYCIDE

NITRIDE SIDEWALL SPACER Mag. 52,000x

N+ S/D GATE OXIDE

Topological SEM and section views of an on-die Cache cell and typical gate. IBM/Cyrix 6x86 Integrated Circuit Engineering Corporation

TECHNOLOGY DESCRIPTION

IBM 6x86 32-BIT CISC MICROPROCESSOR

Introduction Ref. report SCA 9612-473

Nine loose dice were received for this analysis from IBM. Although no date code was available, it is certain that they were manufactured in 1996. These were Cyrix designed microprocessors fabbed by IBM. No speed data was supplied. These dice contain a 16Kbyte prima- ry Cache memory.

See tables for specific dimensions and materials identification and see figures for examples

of physical structures.

Important/Unique Features

– Standard IBM process with 0.35 micron gates.

– Tungsten via/contact plugs of the “borderless contact” type.

Quality

Quality of the process implementation was very good except for one metal alignment problem (see below). No other items of concern were found.

In the area of layer patterning, etch definition and control (depth) were both good.

Alignment and registration were also good except between metal 3 and the tungsten plugs below it, where misalignment reduced contact area to approximately 25 percent in some cases. It is doubtful this will affect reliability.

Technology

These devices were manufactured by a twin (multiple)-well CMOS process in a P-epi on a P substrate.

Final passivation consisted of a layer of nitride over a layer of glass. 5-11 IBM/Cyrix 6x86 Integrated Circuit Engineering Corporation

These devices incorporated six levels of metal defined by dry-etch techniques (no damascene). Metals 2 - 6 consisted of aluminum with titanium-nitride caps. Metal 6 also employed a titanium adhesion layer. Unlike other circuits we’ve seen made by this process, metal 1 (tungsten) was not used as a local interconnect but was only used as a link between all regular metal 2 plugs and silicon. The top of this layer is defined by the first chemical-mechanical-planarization (CMP) procedure. We were surprised to see this process used in this case since it does add another metal deposition and CMP procedure. IBM has a process that eliminates this first tungsten (M1) layer for use where local interconnect is not needed.

Tungsten plugs were used for all vertical interconnect. Plugs were “stacked” wherever needed. A titanium-nitride (TiN) layer was used to line the via and contact cuts for the plugs. No TiN was visible between the top of the plugs and the aluminum metallization.

The intermetal dielectrics (except IMD 1) consisted of a thin deposited glass (TEOS?), followed by a thick layer of glass and another thin layer of glass. The first layer appeared to have been covered with a sacrificial layer to allow back etching to break the corners at metal edges. The second layer appeared to have been planarized by CMP. The third (thin) layer was then deposited and planarized when the tops of the plugs were planarized. The dielectric under metal 2 consisted of two thick layers of glass. The first was planarized by CMP with the tops of metal 1 and the second along with the CMP process that leveled to tops of the M2 plugs.

A single layer of titanium-silicided polysilicon (polycide) was used for all gates on the die.

Sidewall spacers on the gates were of nitride, and provided both the spacing for the LDD requirements as well as separation between gate edges and the metallized source/drain diffusions (salicide process). The same material (titanium) was used to silicide sources/drains as for siliciding the polysilicon. This silicide layer was covered by the normal thin nitride sealing layer employed by IBM.

No standard buried contacts were utilized and the metal 1 tungsten was also not used to make “local” interconnects. Instead connections between poly and diffusions used a metal 1 contact plug on each surface, an M2 plug on both M1 contacts, and metal 2 aluminum interconnect.

No evidence of unusual gate oxides was found, but shallow trench oxide isolation was employed and well implemented. IBM has used this process for several years.

Redundancy fuse elements were not found on this device.

5-12 IBM/Cyrix 6x86 Integrated Circuit Engineering Corporation

The on chip Cache memory cells (16Kbyte) used a six transistor CMOS SRAM design thus requiring multiple wells in the arrays but making a second poly unnecessary. Metal 4 distributed GND and Vcc and also provided “piggyback” word lines. Bit lines used metal 3 and metal 2 for cell interconnect. This resulted in a quite respectable 44 microns2 cell size.

Overall minimum feature size measured anywhere on these dice was the 0.35 micron polycide (gates).

Packaging/Assembly

As mentioned, the devices analyzed were unpackaged (loose dice) but they incorporated standard wirebond pads (not C4 solder ball pads). A thin patterned polyimide die coat was present.

Wirebond pads on the die were on a 110 micron pitch using 100 micron wide pads (90 micron windows) with 10 micron spaces.

5-13 IBM 6x86 Integrated Circuit Engineering Corporation

Whole die photograph of the IBM 6x86 Microprocessor. Mag. 14x. IBM 6x86 Integrated Circuit Engineering Corporation

METAL 5 METAL 6

PASSIVATION 2

M4 PLUG METAL 3

METAL 4 M3 PLUG glass etch, METAL 2 Mag. 6000x M2 PLUG

METAL 1 POLY GATE

METAL 4

M4 PLUG

METAL 3

M3PLUG M2 PLUG Mag. 9000x METAL 2

METAL 1 N-WELL

TRENCH OXIDE

M4 PLUG

METAL 3 M4 PLUG Mag. 30,000x, 55°

Section and perspective SEM views of general structure and plugs. IBM 6x86 Integrated Circuit Engineering Corporation

METAL 3

METAL 4 metal patterning, M4 PLUG Mag. 11,000x MISALIGNMENT

M6 PLUG

borderless via, CAP Mag. 25,000x, 55° METAL 5

M5 PLUG

DIFFUSION

M2 PLUG

POLY GATES Mag. 8000x, 50°

METAL 1

Topological and perspective SEM views of metal and poly coverage. Sun Microsystems Ultra Sparc Integrated Circuit Engineering Corporation

TECHNOLOGY DESCRIPTION

SUN MICROSYSTEMS ULTRA SPARC-1 64-BIT RISC MICROPROCESSOR

Introduction Ref. report SCA 9604-456

The part was packaged in a fiberglass ball grid array package, date coded 9528. These devices use Sun’s “UltraSparc” operating system and run at 143MHz. They have on-die instruction and data Cache memory arrays.

See tables for specific dimensions and materials identification and see figures for examples of physical structures.

Important/Unique Features

– Four level metal, twin-well, P-epi, CMOS process.

– Spin-on-glass (SOG) for interlevel planarization (no CMP).

– Slightly older technology therefore less aggressive feature sizes (0.45 micron gates).

Quality

Quality of the process implementation was good, except at Metal 4 where aluminum thinning up to 100 percent occurred at via edges (barrier maintained continuity).

In the area of layer patterning, etch definition and control (depth) were both good.

Alignment and registration were also good.

Technology

The device was manufactured by a twin (multiple)-well CMOS process using standard recessed oxide (LOCOS) isolation in a P-epi on a P substrate.

Final passivation consisted of a layer of nitride over a layer of silicon dioxide.

5-14 Sun Microsystems Ultra Sparc Integrated Circuit Engineering Corporation

This device incorporated four levels of metal defined by standard dry-etch techniques (no damascene). Each consisted of aluminum with titanium-nitride caps and barriers. A thin titanium adhesion layer was present under metal 1.

Tungsten plugs (not stacked) were used for vertical interconnects between metals 1 - 3. Metal 4 used standard vias to connect to metal 3. The plugs were both lined and covered by titanium- nitride liners.

All dielectric layers (ILD1 - ILD3) consisted of a uniform layer of glass, followed by a spin-on- glass (SOG) for planarization, and another layer of glass. Only the SOG appeared to have been subjected to an etchback. Planarization under the M1 was performed using a thick layer of glass (possibly subjected to etchback for planarization) followed by a uniform layer of glass.

A single layer of titanium-silicided polysilicon (polycide) was used for all gates on the die.

Gate sidewall spacers were of nitride, providing both the spacing for the LDD requirements as well as separation between gate edges and the metallized (salicide process) source/drain diffusions. The same material (titanium) was used at source/drains as for siliciding the polysilicon.

Buried contacts were not used and no “local” interconnect layer was present.

No evidence of unusual gate oxides or other dielectrics was found. Standard LOCOS isolation was employed and well implemented. A step was present in the LOCOS at edges of wells.

Polycide redundancy fuses were present. Some laser-blown fuses were found. Passivation 1 and interlevel oxide cutouts were present over the fuses. Passivation and pre-metal dielectric covered the fuses.

The Cache memory cells used a six transistor CMOS SRAM cell design. Metal 2 formed the bit lines and distributed GND (via metal 1 links). Metal 1 distributed Vcc, formed “piggyback” word lines, and provided cell interconnect. This SRAM design had the largest cell size, 63.7 microns2 of any of the processors analyzed.

Overall minimum feature size measured anywhere on this die was the 0.45 micron polycide (gates), the largest of this group.

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Packaging/Assembly

As mentioned, the part was packaged in a fiberglass ball grid array package, date coded 9528.

Four decoupling capacitors were present on the corners of the package. The die was mounted to the underside of the heatsink (cavity down) with silver-epoxy die attach. The cavity was filled with a black encapsulant. Wirebond pads on the die had a pitch of 100 microns with a 5 micron spacing. Pads were 95 microns wide with an 85 micron window.

A thin, patterned polyimide die coat was present.

5-16 Sun Microsystems Ultra Sparc Integrated Circuit Engineering Corporation

INSTRUCTION CACHE

DATA CACHE

Whole die photograph of the Sun Microsystems Ultra Sparc Microprocessor. Mag. 10x. Sun Microsystems Ultra Sparc Integrated Circuit Engineering Corporation

METAL 4

METAL 3

METAL 2

METAL 1

Mag. 8450x, 60°

PASSIVATION 2

PASSIVATION 1

METAL 4

METAL 3

METAL 2

METAL 1

POLYCIDE

Mag. 9300x Perspective and section SEM views illustrating general device structures. Sun Microsystems Ultra Sparc Integrated Circuit Engineering Corporation

SOG

METAL 1 Mag. 17,600x POLYCIDE GATE M1 PLUG

N+ S/D N+ S/D

NITRIDE SIDEWALL SPACER

POLYCIDE GATE Mag. 52,000x

N+ S/D

GATE OXIDE

POLYCIDE

Mag. 6000x

SEM section and perspective views of transistor structures.