DOCSLIB.ORG

Microprocessors We Saw in 1996

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Microprocessors We Saw in 1996 Integrated Circuit Engineering Corporation MICRMICROPROPROCESSORSOCESSORS Deservedly still the technology leader category we believe (although the Siemens’ 64Mb DRAM may make this too close to call). Again this year this product category provided not only the most complex metal interconnect technology (Motorola), but also the shortest gates (Motorola)! So, Motorola appears to definitely be “in the game” and gets our vote for “most improved” technology this year. Intel’s Pentium Pro and IBM PC601+ seem to be “mature” technologies at this point. The UltraSparc from SUN included here has a somewhat unfair disadvantage, it is about a year older technology, (since we seem to be unable to obtain any late model devices). Hewlett Packard also remains shrouded in mystery (shyness?). Now, if all these manufacturers could only catch DEC Alpha’s speed! 5-1 HORIZONTAL DIMENSIONS (DESIGN RULES) MOTOROLA DEC INTEL IBM SUN CPUs MPC 604e Alpha 21164 Pentium Pro 6X86 Ultra Sparc 64 Bit RISC 64 Bit RISC 64 Bit CISC 32 Bit CISC 64 Bit RISC 1996 1996 1996 1996 9528 ❶ Die size 11.7 x 12.9mm 16.8 x 18.6mm 14 x 14mm 13.3 x 14.6mm 17.7 x 17.8mm (148mm2) (313mm2) (196mm2) (194mm2) (315mm2) Min. M6 width/space 3.0µm/2.0µm NA NA 1.7µm/1.4µm NA Min. M5 width/space 1.0µm/0.7µm NA NA 0.75µm/0.8µm NA Min. M4 width/space 1.1µm/0.65µm 3.4µm/2.6µm 2.0µm/2.0µm 0.65µm/0.8µm 2.0µm/1.8µm Min. M3 width/space 1.0µm/0.75µm 2.2µm/2.6µm 0.6µm/0.55µm 0.6µm/0.9µm 0.8µm/0.9µm Min. M2 width/space 0.8µm/0.5µm 1.2µm/0.8µm 0.6µm/0.55µm 0.55µm/0.7µm 0.8µm/0.9µm ❷ Min. M1 width/space 0.55µm/0.75µm 1.2µm/0.8µm 0.55µm/0.4µm 0.7µm/NA 0.8µm/0.9µm + + + + + Min. via (Met. to Met) 0.55µm 0.5µm 0.5µm 0.65µm 0.7µm µ + µ + µ + µ + µ + Min contact (Met. to Si) 0.55 m 0.6 m 0.55 m 0.7 m 0.7 m Integrated CircuitEngineeringCorporation Min. Poly 0.25µm* 0.35µm 0.3µm* 0.35µm* 0.45µm* Min. gate-(N)† 0.25µm 0.4µm 0.3µm 0.35µm 0.45µm Min. gate-(P)† 0.25µm 0.45µm 0.3µm 0.35µm 0.45µm Cache Cell 36µm2 43µm2 49µm2 44µm2 64µm2 ❶ ❷ * Polycide † Physical gate length + Plugs Active area See text Table 5-1 VERTICAL DIMENSIONS MOTOROLA DEC INTEL IBM SUN CPUs MPC 604e Alpha 21164 Pentium Pro 6X86 Ultra Sparc 64 Bit RISC 64 Bit RISC 64 Bit CISC 32 Bit CISC 64 Bit RISC 1996 1996 1996 1996 9528 Final passivation 1.0µm 0.7µm 0.7µm 1.0µm 2.0µm Metal 6 1.8µm NA NA NA NA Metal 5 0.7µm NA NA 0.9µm NA Metal 4 0.7µm 1.6µm 1.9µm 0.85µm 1.3µm Metal 3 0.65µm 1.6µm 0.85µm 0.8µm 0.8µm Metal 2 0.7µm 0.9µm 0.8µm 0.65µm 0.8µm Metal 1 0.8µm 0.9µm 0.6µm 0.65µm 0.8µm Pre-metal dielectric 0.7µm 1.2µm 0.45µm 0.75µm❸ 0.6µm Poly 0.2µm* 0.3µm* 0.35µm* 0.15µm* 0.25µm* Integrated CircuitEngineeringCorporation Recessed oxide 0.55µm❷ 0.4µm❷ 0.4µm❷ 0.4µm❷ 0.55µm N-well 1µm ?❶ 1µm 1µm 2µm P-well ?❶ ?❶ ?❶ ?❶ ?❶ Epi 2.5µm (P) 2.5µm (P) 2µm (P) 2µm (P) 6µm (P) ❶ ❷ ❸ * Polycide Could not delineate Shallow trench See text Table 5-2 DIE MATERIALS MOTOROLA DEC INTEL IBM SUN CPUs MPC 604e Alpha 21164 Pentium Pro 6X86 Ultra Sparc 64 Bit RISC 64 Bit RISC 64 Bit CISC 32 Bit CISC 64 Bit RISC 1996 1996 1996 1996 9528 Final passivation Nitride on glass glass Nitride Nitride on glass Nitride on glass Metal 6 Aluminum NA NA Titanium-Nitride NA Aluminum Titanium Metal 5 Titanium-Nitride NA NA Same as Metal 6 NA Aluminum Titanium-Nitride Titanium Metal 4 Same as Metal 5 Titanium-Nitride Titanium-Nitride Same as Metal 6 Titanium-Nitride Aluminum Aluminum Aluminum Titanium-Nitride Titanium Titanium-Nitride Metal 3 Same as Metal 5 Same as Metal 4 Same as Metal 4 Same as Metal 6 Same as Metal 4 Metal 2 Same as Metal 5 Same as Metal 4 Same as Metal 4 Same as Metal 6 Same as Metal 4 Integrated CircuitEngineeringCorporation Metal 1 Tungsten Same as Metal 4 Same as Metal 4 Tungsten❶ Same as Metal 4 Via (metal to metal) Tungsten+ Tungsten+ Tungsten+ Tungsten+ Tungsten+ Contact (metal to silicon) Tungsten+ Tungsten+ Tungsten+ Tungsten+ Tungsten+ Intermetal dielectric glass glass w SOG glass glass glass w SOG Pre-metal dielectric glass/nitride Layered glass glass glass/nitride glass Polycide*/salicide† metal titanium*† cobalt*† titanium*† titanium*† titanium*† + Plugs ❶ See text Table 5-3 Motorola Power PC604e Integrated Circuit Engineering Corporation TECHNOLOGY DESCRIPTION MOTOROLA MPC604e 64-BIT RISC MICROPROCESSOR Introduction Ref. report SCA 9607-486 The part was packaged in a 256-pin (255 actual) ceramic ball grid array package. A date code was not identifiable but the devices were undoubtedly fabbed in 1996. The device has on-chip 32Kbyte instruction and data cache memory arrays, a 64-bit external data bus, 32-bit address bus, and runs at 166MHz. See tables for specific dimensions and materials identification and see figures for examples of physical structures. Important/Unique Features – The most advanced microprocessor technology seen in 1996! – Very aggressive feature size (0.25 micron gates). – Six metal process (five aluminum, one tungsten). – High degree of planarization (CMP). – Shallow trench isolation. – “C4” flip-chip design with solder bumps. Quality Quality of the process implementation was very good and we found no areas of concern. In the area of layer patterning, etch definition and control were both good. Alignment and registration were also good. 5-2 Motorola Power PC604e Integrated Circuit Engineering Corporation Technology The device was manufactured by a shallow trench oxide isolation twin (multiple)-well CMOS process in a P-epi on a P substrate. It is the first example we’ve seen of an IBM style process fabbed by Motorola. Final passivation consisted of a layer of nitride over a layer of silicon dioxide. This device incorporated six levels of metal. Metals 2 - 6 were defined by dry-etch techniques (no damascene) and consisted of aluminum with titanium-nitride caps and barriers on thin tita- nium adhesion layers, except for metal 6 which had no cap or barrier. Metal 1 consisted of tungsten and was defined using a damascene process. It was used for local interconnect. Metal 6 used standard vias to connect to metal 5. Tungsten plugs (some elongated) were used for vertical interconnects between metals 2 - 5, and were stacked where needed. Planarization of the interlevel dielectric 5 (between M5 and M6) consisted of a layer of deposit- ed glass (possibly TEOS) which was subjected to an etchback, then followed by a thin layer of deposited glass (no SOG). Interlevel dielectrics 2 - 4 each consisted of a layer of deposited glass followed by a thick layer of glass that was planarized by CMP, and another layer of glass that was planarized by the CMP process that leveled the tungsten plugs. Interlevel dielectric 1 consisted of a thick layer of glass which was also planarized by the tungsten plug leveling CMP. Planarization of the “pre-metal” dielectric (which in this process surrounds metal 1) was done using a thick layer of silicon-dioxide (subjected to CMP) followed by a thin layer of silicon- dioxide. Again here also the thin layer was planarized as part of the tungsten planarizing CMP. A thin nitride “sealing layer” was present under the “pre-metal” covering all active areas. No evidence of any spin-on-glass (SOG) was found anywhere. A single layer of titanium-silicided polysilicon (polycide) was used for all gates on the die. Sidewall spacers were of nitride, providing both the spacing for the LDD requirements as well as separation between gate edges and the metallized (salicide process) source/drain diffusions. The same material (titanium) was used at sources/drains as for siliciding the polysilicon. Buried contacts were not used, the metal 1 tungsten being used for connecting poly to diffusions. No evidence of unusual gate oxides was found, but shallow trench oxide isolation was employed and well implemented. 5-3 Motorola Power PC604e Integrated Circuit Engineering Corporation Redundancy fuses made with metal 5 were present, but no blown links were found. Passivation and oxide cutouts were present over the fuses. Cache memory cells consisted of a six transistor CMOS SRAM cell design. Metal 3 formed the bit lines (via metals 1 and 2). Metal 2 formed “piggyback” word lines and distributed Vcc and GND (via metal 1). This SRAM had a 36 microns2 cell size, the smallest seen on any micro- processor this year. Overall minimum feature size measured anywhere on this die was the 0.25 micron polycide (gates). This represents the smallest feature size found on any microprocessor product in 1996! Packaging/Assembly As mentioned, the part was packaged in a 256-pin (255 actual) ceramic ball grid array package. No decoupling capacitors were present outside or inside the package. The die was mounted using a flip-chip design (“C4”) incorporating solder bumps. A thin protective coating (under- fill) was present between the ceramic substrate and the die surface. A spun-on patterned, poly- imide die coat covered the active die surface, but was not present over the test array along the edge of the die.
Load more

Recommended publications
  • SPARC/IOBP-CPU-56 Installation Guide
    SPARC/IOBP-CPU-56 Installation Guide P/N 220226 Revision AB September 2003 Copyright The information in this publication is subject to change without notice. Force Computers, GmbH reserves the right to make changes without notice to this, or any of its products, to improve reliability, performance, or design. Force Computers, GmbH shall not be liable for technical or editorial errors or omissions contained herein, nor for indirect, special, incidental, or consequential damages resulting from the furnishing, performance, or use of this material. This information is provided "as is" and Force Computers, GmbH expressly disclaims any and all warranties, express, implied, statutory, or otherwise, including without limitation, any express, statutory, or implied warranty of merchantability, fitness for a particular purpose, or non−infringement. This publication contains information protected by copyright. This publication shall not be reproduced, transmitted, or stored in a retrieval system, nor its contents used for any purpose, without the prior written consent of Force Computers, GmbH. Force Computers, GmbH assumes no responsibility for the use of any circuitry other than circuitry that is part of a product of Force Computers, GmbH. Force Computers, GmbH does not convey to the purchaser of the product described herein any license under the patent rights of Force Computers, GmbH nor the rights of others. CopyrightE 2003 by Force Computers, GmbH. All rights reserved. The Force logo is a trademark of Force Computers, GmbH. IEEER is a registered trademark of the Institute for Electrical and Electronics Engineers, Inc. PICMGR, CompactPCIR, and the CompactPCI logo are registered trademarks and the PICMG logo is a trademark of the PCI Industrial Computer Manufacturer’s Group.
    [Show full text]
  • Historical Perspective and Further Reading 162.E1
    2.21 Historical Perspective and Further Reading 162.e1 2.21 Historical Perspective and Further Reading Th is section surveys the history of in struction set architectures over time, and we give a short history of programming languages and compilers. ISAs include accumulator architectures, general-purpose register architectures, stack architectures, and a brief history of ARMv7 and the x86. We also review the controversial subjects of high-level-language computer architectures and reduced instruction set computer architectures. Th e history of programming languages includes Fortran, Lisp, Algol, C, Cobol, Pascal, Simula, Smalltalk, C+ + , and Java, and the history of compilers includes the key milestones and the pioneers who achieved them. Accumulator Architectures Hardware was precious in the earliest stored-program computers. Consequently, computer pioneers could not aff ord the number of registers found in today’s architectures. In fact, these architectures had a single register for arithmetic instructions. Since all operations would accumulate in one register, it was called the accumulator , and this style of instruction set is given the same name. For example, accumulator Archaic EDSAC in 1949 had a single accumulator. term for register. On-line Th e three-operand format of RISC-V suggests that a single register is at least two use of it as a synonym for registers shy of our needs. Having the accumulator as both a source operand and “register” is a fairly reliable indication that the user the destination of the operation fi lls part of the shortfall, but it still leaves us one has been around quite a operand short. Th at fi nal operand is found in memory.
    [Show full text]
  • LSU EE 4720 Homework 1 Solution Due: 3 March 2006
    LSU EE 4720 Homework 1 Solution Due: 3 March 2006 Several Web links appear below and at least one is long, to avoid the tedium of typing them view the assignment in Adobe reader and click. Problem 1: Consider these add instructions in three common ISAs. (Use the ISA manuals linked to the references page, http://www.ece.lsu.edu/ee4720/reference.html.) # MIPS64 addu r1, r2, r3 # SPARC V9 add g2, g3, g1 # PA RISC 2 add r1, r2, r3 (a) Show the encoding (binary form) for each instruction. Show the value of as many bits as possible. Codings shown below. For PA-RISC the ea, ec, and ed ¯elds are labeled e1, e2, and e3, respectively in the instruction descriptions. There is no label for the eb ¯eld in the instruction description of the add and yes it would make sense to use e0 instead of e1 but they didn't for whatever reason. opcode rs rt rd sa func MIPS64: 0 2 3 1 0 0x21 31 26 25 21 20 16 15 11 10 6 5 0 op rd op3 rs1 i asi rs2 SPARC V9: 2 1 0 2 0 0 3 31 30 29 25 24 19 18 14 13 13 12 5 4 0 OPCD r2 r1 c f ea eb ec ed d t PA-RISC 2: 2 3 2 0 0 01 1 0 00 0 1 0 5 6 10 11 15 16 18 19 19 20 21 22 22 23 23 24 25 26 26 27 31 (b) Identify the ¯eld or ¯elds in the SPARC add instruction which are the closest equivalent to MIPS' func ¯eld.
    [Show full text]
  • Ross Technology RT6224K User Manual 1 (Pdf)
    Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Ross Technology RT6224K-200/512S at our website: Click HERE 830-0016-03 Rev A 11/15/96 PRELIMINARY Colorado 4 RT6224K hyperSPARC CPU Module Features D Based on ROSS’ fifth-generation D SPARC compliant — Zero-wait-state, 512-Kbyte or hyperSPARC processor — SPARC Instruction Set Architec- 1-Mbyte 2nd-level cache — RT620D Central Processing Unit ture (ISA) Version 8 compliant — Demand-paged virtual memory (CPU) — Conforms to SPARC Reference management — RT626 Cache Controller, Memory MMU Architecture D Module design Management, and Tag Unit — Conforms to SPARC Level 2 MBus — MBus-standard form factor: 3.30” (CMTU) Module Specification (Revision 1.2) (8.34 cm) x 5.78” (14.67 cm) — Four (512-Kbyte) or eight D Dual-clock architecture — Provides CPU upgrade path at (1-Mbyte) RT628 Cache Data Units module level (CDUs) Ċ CPU scaleable up to
    [Show full text]
  • SPARC Assembly Language Reference Manual
    SPARC Assembly Language Reference Manual 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. A Sun Microsystems, Inc. Business 1995 Sun Microsystems, Inc. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system, licensed from UNIX Systems Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun’s Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, SunSoft, the SunSoft logo, Solaris, SunOS, OpenWindows, DeskSet, ONC, ONC+, and NFS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. OPEN LOOK is a registered trademark of Novell, Inc.
    [Show full text]
  • Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN)
    Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN). [Chapters 1, 2] • Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] Week 2 • MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] • Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4] Week 3 • CPU Organization: Datapath & Control Unit Design. [Chapter 5] Week 4 – MIPS Single Cycle Datapath & Control Unit Design. – MIPS Multicycle Datapath and Finite State Machine Control Unit Design. Week 5 • Microprogrammed Control Unit Design. [Chapter 5] – Microprogramming Project Week 6 • Midterm Review and Midterm Exam Week 7 • CPU Pipelining. [Chapter 6] • The Memory Hierarchy: Cache Design & Performance. [Chapter 7] Week 8 • The Memory Hierarchy: Main & Virtual Memory. [Chapter 7] Week 9 • Input/Output Organization & System Performance Evaluation. [Chapter 8] Week 10 • Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Week 11 • Final Exam. EECC550 - Shaaban #1 Lec # 1 Winter 2005 11-29-2005 Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals • Computing Element Choices: – Computing Element Programmability – Spatial vs. Temporal Computing – Main Processor Types/Applications • General Purpose Processor Generations • The Von Neumann Computer Model • CPU Organization (Design) • Recent Trends in Computer Design/performance • Hierarchy
    [Show full text]
  • Solaris Powerpc Edition: Installing Solaris Software—May 1996 What Is a Profile
    SolarisPowerPC Edition: Installing Solaris Software 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. A Sun Microsystems, Inc. Business Copyright 1996 Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system, licensed from Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. UNIX is a registered trademark in the United States and other countries and is exclusively licensed by X/Open Company Ltd. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun’s suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. Sun, Sun Microsystems, the Sun logo, Solaris, Solstice, SunOS, OpenWindows, ONC, NFS, DeskSet are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc.
    [Show full text]
  • V850 Series Development Environment Pamphlet
    To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples.
    [Show full text]
  • Unit 2: Instruction Set Architectures
    Computer Architecture Unit 2: Instruction Set Architectures Slides'developed'by'Milo'Mar0n'&'Amir'Roth'at'the'University'of'Pennsylvania'' with'sources'that'included'University'of'Wisconsin'slides' by'Mark'Hill,'Guri'Sohi,'Jim'Smith,'and'David'Wood' Computer Architecture | Prof. Milo Martin | Instruction Sets 1 Instruction Set Architecture (ISA) Application • What is an ISA? OS • A functional contract Compiler Firmware • All ISAs similar in high-level ways • But many design choices in details CPU I/O • Two “philosophies”: CISC/RISC Memory • Difference is blurring Digital Circuits • Good ISA… Gates & Transistors • Enables high-performance • At least doesn’t get in the way • Compatibility is a powerful force • Tricks: binary translation, µISAs Computer Architecture | Prof. Milo Martin | Instruction Sets 2 Readings • Suggested reading: • “The Evolution of RISC Technology at IBM” by John Cocke and V. Markstein Computer Architecture | Prof. Milo Martin | Instruction Sets 3 Execution Model Computer Architecture | Prof. Milo Martin | Instruction Sets 4 Program Compilation int array[100], sum;! void array_sum() {! for (int i=0; i<100;i++) {! sum += array[i];! }! }! • Program written in a “high-level” programming language • C, C++, Java, C# • Hierarchical, structured control: loops, functions, conditionals • Hierarchical, structured data: scalars, arrays, pointers, structures • Compiler: translates program to assembly • Parsing and straight-forward translation • Compiler also optimizes • Compiler itself another application … who compiled compiler? Computer Architecture | Prof. Milo Martin | Instruction Sets 5 Assembly & Machine Language • Assembly language • Human-readable representation • Machine language • Machine-readable representation • 1s and 0s (often displayed in “hex”) • Assembler • Translates assembly to machine Example is in “LC4” a toy instruction set architecture, or ISA Computer Architecture | Prof.
    [Show full text]
  • Phaser 600 Color Printer User Manual
    WELCOME! This is the home page of the Phaser 600 Color Printer User Manual. See Tips on using this guide, or go immediately to the Contents. Phaser® 600 Wide-Format Color Printer Tips on using this guide ■ Use the navigation buttons in Acrobat Reader to move through the document: 1 23 4 5 6 1 and 4 are the First Page and Last Page buttons. These buttons move to the first or last page of a document. 2 and 3 are the Previous Page and Next Page buttons. These buttons move the document backward or forward one page at a time. 5 and 6 are the Go Back and Go Forward buttons. These buttons let you retrace your steps through a document, moving to each page or view in the order visited. ■ For best results, use the Adobe Acrobat Reader version 2.1 to read this guide. Version 2.1 of the Acrobat Reader is supplied on your printer’s CD-ROM. ■ Click on the page numbers in the Contents on the following pages to open the topics you want to read. ■ You can click on the page numbers following keywords in the Index to open topics of interest. ■ You can also use the Bookmarks provided by the Acrobat Reader to navigate through this guide. If the Bookmarks are not already displayed at the left of the window, select Bookmarks and Page from the View menu. ■ If you have difficultly reading any small type or seeing the details in any of the illustrations, you can use the Acrobat Reader’s Magnification feature.
    [Show full text]
  • RISC-V Geneology
    RISC-V Geneology Tony Chen David A. Patterson Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2016-6 http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-6.html January 24, 2016 Copyright © 2016, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Introduction RISC-V is an open instruction set designed along RISC principles developed originally at UC Berkeley1 and is now set to become an open industry standard under the governance of the RISC-V Foundation (www.riscv.org). Since the instruction set architecture (ISA) is unrestricted, organizations can share implementations as well as open source compilers and operating systems. Designed for use in custom systems on a chip, RISC-V consists of a base set of instructions called RV32I along with optional extensions for multiply and divide (RV32M), atomic operations (RV32A), single-precision floating point (RV32F), and double-precision floating point (RV32D). The base and these four extensions are collectively called RV32G. This report discusses the historical precedents of RV32G. We look at 18 prior instruction set architectures, chosen primarily from earlier UC Berkeley RISC architectures and major proprietary RISC instruction sets. Among the 122 instructions in RV32G: ● 6 instructions do not have precedents among the selected instruction sets, ● 98 instructions of the 116 with precedents appear in at least three different instruction sets.
    [Show full text]
  • Effectiveness of the MAX-2 Multimedia Extensions for PA-RISC 2.0 Processors
    Effectiveness of the MAX-2 Multimedia Extensions for PA-RISC 2.0 Processors Ruby Lee Hewlett-Packard Company HotChips IX Stanford, CA, August 24-26,1997 Outline Introduction PA-RISC MAX-2 features and examples Mix Permute Multiply with Shift&Add Conditionals with Saturation Arith (e.g., Absolute Values) Performance Comparison with / without MAX-2 General-Purpose Workloads will include Increasing Amounts of Media Processing MM a b a b 2 1 2 1 b c b c functionality 5 2 5 2 A B C D 1 2 22 2 2 33 3 4 55 59 A B C D 1 2 A B C D 22 1 2 22 2 2 2 2 33 33 3 4 55 59 3 4 55 59 Distributed Multimedia Real-time Information Access Communications Tool Tool Computation Tool time 1980 1990 2000 Multimedia Extensions for General-Purpose Processors MAX-1 for HP PA-RISC (product Jan '94) VIS for Sun Sparc (H2 '95) MAX-2 for HP PA-RISC (product Mar '96) MMX for Intel x86 (chips Jan '97) MDMX for SGI MIPS-V (tbd) MVI for DEC Alpha (tbd) Ideally, different media streams map onto both the integer and floating-point datapaths of microprocessors images GR: GR: 32x32 video 32x64 ALU SMU FP: graphics FP:16x64 Mem 32x64 audio FMAC PA-RISC 2.0 Processor Datapath Subword Parallelism in a General-Purpose Processor with Multimedia Extensions General Regs. y5 y6 y7 y8 x5 x6 x7 x8 x1 x2 x3 x4 y1 y2 y3 y4 Partitionable Partitionable 64-bit ALU 64-bit ALU 8 ops / cycle Subword Parallel MAX-2 Instructions in PA-RISC 2.0 Parallel Add (modulo or saturation) Parallel Subtract (modulo or saturation) Parallel Shift Right (1,2 or 3 bits) and Add Parallel Shift Left (1,2 or 3 bits) and Add Parallel Average Parallel Shift Right (n bits) Parallel Shift Left (n bits) Mix Permute MAX-2 Leverages Existing Processing Resources FP: INTEGER FLOAT GR: 16x64 General Regs.
    [Show full text]