DOCSLIB.ORG

Oracle SPARC Architecture 2011 • Draft D1.0.0

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Oracle SPARC Architecture 2011 • Draft D1.0.0 Oracle SPARC Architecture 2011 One Architecture ... Multiple Innovative Implementations Draft D1.0.0, 12 Jan 2016 Privilege Levels: Privileged and Nonprivileged Distribution: Public Part No: 950-5954-00 Revision: Draft D1.0.0, 12 Jan 2016 Oracle Corporation 4150 Network Circle Santa Clara, CA 95054 U.S.A. 650-960-1300 ii Oracle SPARC Architecture 2011 • Draft D1.0.0, 12 Jan 2016 Copyright © 2011, Oracle and/or its affiliates. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective owners. AMD, Opteron, the AMD logo, and the AMD Opteron logo are trademarks or registered trademarks of Advanced Micro Devices. Intel and Intel Xeon are trademarks or registered trademarks of Intel Corporation. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. UNIX is a registered trademark licensed through X/Open Company, Ltd.. Comments and "bug reports” regarding this document are welcome; they should be submitted to email address: [email protected] iv Oracle SPARC Architecture 2011 • Draft D1.0.0, 12 Jan 2016 Contents Preface. i 1 Document Overview . .1 1.1 Navigating Oracle SPARC Architecture 2011 . .1 1.2 Fonts and Notational Conventions . .2 1.2.1 Implementation Dependencies. 3 1.2.2 Notation for Numbers . 3 1.2.3 Informational Notes. 3 1.3 Reporting Errors in this Specification. .4 2 Definitions . 5 3 Architecture Overview. 13 3.1 The Oracle SPARC Architecture 2011 . .13 3.1.1 Features . 13 3.1.2 Attributes . 14 3.1.2.1 Design Goals. .15 3.1.2.2 Register Windows . .15 3.1.3 System Components . 15 3.1.3.1 Binary Compatibility . .15 3.1.3.2 Oracle SPARC Architecture 2011 MMU . .15 3.1.3.3 Privileged Software . .15 3.1.4 Architectural Definition . 16 3.1.5 Oracle SPARC Architecture 2011 Compliance with SPARC V9 Architecture. 16 3.1.6 Implementation Compliance with Oracle SPARC Architecture 2011 . 16 3.2 Processor Architecture . .16 3.2.1 Integer Unit (IU). 16 3.2.2 Floating-Point Unit (FPU). 17 3.3 Instructions . 17 3.3.1 Memory Access . 17 3.3.1.1 Memory Alignment Restrictions . .18 3.3.1.2 Addressing Conventions. .18 3.3.1.3 Addressing Range . .18 3.3.1.4 Load/Store Alternate . .18 3.3.1.5 Separate Instruction and Data Memories . .19 3.3.1.6 Input/Output (I/O). .19 3.3.1.7 Memory Synchronization . .19 3.3.2 Integer Arithmetic / Logical / Shift Instructions . 19 3.3.3 Control Transfer . 20 3.3.4 State Register Access . 20 3.3.4.1 Ancillary State Registers . .20 3.3.4.2 PR State Registers . .20 i 3.3.5 Floating-Point Operate . 21 3.3.6 Conditional Move . 21 3.3.7 Register Window Management . 21 3.3.8 SIMD. 21 3.4 Traps . 21 4 Data Formats. 23 4.1 Integer Data Formats . 24 4.1.1 Signed Integer Data Types . 24 4.1.1.1 Signed Integer Byte, Halfword, and Word. 25 4.1.1.2 Signed Integer Doubleword (64 bits) . 25 4.1.1.3 Signed Integer Extended-Word (64 bits) . 25 4.1.2 Unsigned Integer Data Types . 25 4.1.2.1 Unsigned Integer Byte, Halfword, and Word . 26 4.1.2.2 Unsigned Integer Doubleword (64 bits). 26 4.1.2.3 Unsigned Extended Integer (64 bits) . 26 4.1.3 Tagged Word (32 bits). 26 4.2 Floating-Point Data Formats. 27 4.2.1 Floating Point, Single Precision (32 bits) . 27 4.2.2 Floating Point, Double Precision (64 bits) . 27 4.2.3 Floating Point, Quad Precision (128 bits). 28 4.2.4 Floating-Point Data Alignment in Memory and Registers . 29 4.3 SIMD Data Formats . 29 4.3.1 Uint8 SIMD Data Format . 30 4.3.2 Int16 SIMD Data Formats. 30 4.3.3 Int32 SIMD Data Format . 30 5 Registers . 31 5.1 Reserved Register Fields . .32 5.2 General-Purpose R Registers . 32 5.2.1 Global R Registers. 33 5.2.2 Windowed R Registers . 34 5.2.3 Special R Registers . 37 5.3 Floating-Point Registers . ..
Load more

Recommended publications
  • SPARC/IOBP-CPU-56 Installation Guide
    SPARC/IOBP-CPU-56 Installation Guide P/N 220226 Revision AB September 2003 Copyright The information in this publication is subject to change without notice. Force Computers, GmbH reserves the right to make changes without notice to this, or any of its products, to improve reliability, performance, or design. Force Computers, GmbH shall not be liable for technical or editorial errors or omissions contained herein, nor for indirect, special, incidental, or consequential damages resulting from the furnishing, performance, or use of this material. This information is provided "as is" and Force Computers, GmbH expressly disclaims any and all warranties, express, implied, statutory, or otherwise, including without limitation, any express, statutory, or implied warranty of merchantability, fitness for a particular purpose, or non−infringement. This publication contains information protected by copyright. This publication shall not be reproduced, transmitted, or stored in a retrieval system, nor its contents used for any purpose, without the prior written consent of Force Computers, GmbH. Force Computers, GmbH assumes no responsibility for the use of any circuitry other than circuitry that is part of a product of Force Computers, GmbH. Force Computers, GmbH does not convey to the purchaser of the product described herein any license under the patent rights of Force Computers, GmbH nor the rights of others. CopyrightE 2003 by Force Computers, GmbH. All rights reserved. The Force logo is a trademark of Force Computers, GmbH. IEEER is a registered trademark of the Institute for Electrical and Electronics Engineers, Inc. PICMGR, CompactPCIR, and the CompactPCI logo are registered trademarks and the PICMG logo is a trademark of the PCI Industrial Computer Manufacturer’s Group.
    [Show full text]
  • LSU EE 4720 Homework 1 Solution Due: 3 March 2006
    LSU EE 4720 Homework 1 Solution Due: 3 March 2006 Several Web links appear below and at least one is long, to avoid the tedium of typing them view the assignment in Adobe reader and click. Problem 1: Consider these add instructions in three common ISAs. (Use the ISA manuals linked to the references page, http://www.ece.lsu.edu/ee4720/reference.html.) # MIPS64 addu r1, r2, r3 # SPARC V9 add g2, g3, g1 # PA RISC 2 add r1, r2, r3 (a) Show the encoding (binary form) for each instruction. Show the value of as many bits as possible. Codings shown below. For PA-RISC the ea, ec, and ed ¯elds are labeled e1, e2, and e3, respectively in the instruction descriptions. There is no label for the eb ¯eld in the instruction description of the add and yes it would make sense to use e0 instead of e1 but they didn't for whatever reason. opcode rs rt rd sa func MIPS64: 0 2 3 1 0 0x21 31 26 25 21 20 16 15 11 10 6 5 0 op rd op3 rs1 i asi rs2 SPARC V9: 2 1 0 2 0 0 3 31 30 29 25 24 19 18 14 13 13 12 5 4 0 OPCD r2 r1 c f ea eb ec ed d t PA-RISC 2: 2 3 2 0 0 01 1 0 00 0 1 0 5 6 10 11 15 16 18 19 19 20 21 22 22 23 23 24 25 26 26 27 31 (b) Identify the ¯eld or ¯elds in the SPARC add instruction which are the closest equivalent to MIPS' func ¯eld.
    [Show full text]
  • Ross Technology RT6224K User Manual 1 (Pdf)
    Full-service, independent repair center -~ ARTISAN® with experienced engineers and technicians on staff. TECHNOLOGY GROUP ~I We buy your excess, underutilized, and idle equipment along with credit for buybacks and trade-ins. Custom engineering Your definitive source so your equipment works exactly as you specify. for quality pre-owned • Critical and expedited services • Leasing / Rentals/ Demos equipment. • In stock/ Ready-to-ship • !TAR-certified secure asset solutions Expert team I Trust guarantee I 100% satisfaction Artisan Technology Group (217) 352-9330 | [email protected] | artisantg.com All trademarks, brand names, and brands appearing herein are the property o f their respective owners. Find the Ross Technology RT6224K-200/512S at our website: Click HERE 830-0016-03 Rev A 11/15/96 PRELIMINARY Colorado 4 RT6224K hyperSPARC CPU Module Features D Based on ROSS’ fifth-generation D SPARC compliant — Zero-wait-state, 512-Kbyte or hyperSPARC processor — SPARC Instruction Set Architec- 1-Mbyte 2nd-level cache — RT620D Central Processing Unit ture (ISA) Version 8 compliant — Demand-paged virtual memory (CPU) — Conforms to SPARC Reference management — RT626 Cache Controller, Memory MMU Architecture D Module design Management, and Tag Unit — Conforms to SPARC Level 2 MBus — MBus-standard form factor: 3.30” (CMTU) Module Specification (Revision 1.2) (8.34 cm) x 5.78” (14.67 cm) — Four (512-Kbyte) or eight D Dual-clock architecture — Provides CPU upgrade path at (1-Mbyte) RT628 Cache Data Units module level (CDUs) Ċ CPU scaleable up to
    [Show full text]
  • SPARC Assembly Language Reference Manual
    SPARC Assembly Language Reference Manual 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. A Sun Microsystems, Inc. Business 1995 Sun Microsystems, Inc. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system, licensed from UNIX Systems Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun’s Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, SunSoft, the SunSoft logo, Solaris, SunOS, OpenWindows, DeskSet, ONC, ONC+, and NFS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. OPEN LOOK is a registered trademark of Novell, Inc.
    [Show full text]
  • Solaris Powerpc Edition: Installing Solaris Software—May 1996 What Is a Profile
    SolarisPowerPC Edition: Installing Solaris Software 2550 Garcia Avenue Mountain View, CA 94043 U.S.A. A Sun Microsystems, Inc. Business Copyright 1996 Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system, licensed from Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. UNIX is a registered trademark in the United States and other countries and is exclusively licensed by X/Open Company Ltd. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun’s suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. Sun, Sun Microsystems, the Sun logo, Solaris, Solstice, SunOS, OpenWindows, ONC, NFS, DeskSet are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc.
    [Show full text]
  • V850 Series Development Environment Pamphlet
    To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples.
    [Show full text]
  • Unit 2: Instruction Set Architectures
    Computer Architecture Unit 2: Instruction Set Architectures Slides'developed'by'Milo'Mar0n'&'Amir'Roth'at'the'University'of'Pennsylvania'' with'sources'that'included'University'of'Wisconsin'slides' by'Mark'Hill,'Guri'Sohi,'Jim'Smith,'and'David'Wood' Computer Architecture | Prof. Milo Martin | Instruction Sets 1 Instruction Set Architecture (ISA) Application • What is an ISA? OS • A functional contract Compiler Firmware • All ISAs similar in high-level ways • But many design choices in details CPU I/O • Two “philosophies”: CISC/RISC Memory • Difference is blurring Digital Circuits • Good ISA… Gates & Transistors • Enables high-performance • At least doesn’t get in the way • Compatibility is a powerful force • Tricks: binary translation, µISAs Computer Architecture | Prof. Milo Martin | Instruction Sets 2 Readings • Suggested reading: • “The Evolution of RISC Technology at IBM” by John Cocke and V. Markstein Computer Architecture | Prof. Milo Martin | Instruction Sets 3 Execution Model Computer Architecture | Prof. Milo Martin | Instruction Sets 4 Program Compilation int array[100], sum;! void array_sum() {! for (int i=0; i<100;i++) {! sum += array[i];! }! }! • Program written in a “high-level” programming language • C, C++, Java, C# • Hierarchical, structured control: loops, functions, conditionals • Hierarchical, structured data: scalars, arrays, pointers, structures • Compiler: translates program to assembly • Parsing and straight-forward translation • Compiler also optimizes • Compiler itself another application … who compiled compiler? Computer Architecture | Prof. Milo Martin | Instruction Sets 5 Assembly & Machine Language • Assembly language • Human-readable representation • Machine language • Machine-readable representation • 1s and 0s (often displayed in “hex”) • Assembler • Translates assembly to machine Example is in “LC4” a toy instruction set architecture, or ISA Computer Architecture | Prof.
    [Show full text]
  • 12 MULTICHIP MODULES (Mcms)
    12 MULTICHIP MODULES (MCMs) HISTORICAL PERSPECTIVE Virtually every large computer manufacturer, telecommunications products manufacturer, high volume consumer electronics manufacturer and aerospace products manufacturer is working on or considering designs that include multichip modules. There has been a dramatic increase in activity over the last five years, with entire conferences being dedicated to multichip modules. MCMs have gone through three phases in their growth. Phase one was the widespread use in mainframe and super computer products. Some examples of MCMs used for these high-end applications are shown in Figure 12-1. The primary driving force was performance. These systems were predominately ECL based, with relatively low inte- gration levels. The MCM implementation allowed the Òre-integrationÓ of the LSI chips into VLSI modules, while keeping the wiring delays small. Source: DEC Source: IBM Source: Motorola/Siemens Source: ICE, “Roadmaps of Packaging Technology” 22555 Figure 12-1. Early MCMs in ECL Mainframe Computers in the Mid 1980Õs INTEGRATED CIRCUIT ENGINEERING CORPORATION 12-1 Multichip Modules (MCMs) Using a conventional single chip package and circuit board interconnect strategy, the package and interconnects took up over 50% of the timing budget. Decreases in the chip delays could not have much impact on system performance without a significant decrease in the interconnect delays as well. The use of MCMs reduced the interconnect delays significantly. This is shown in Figure 12-2 com- paring the delays in the IBM 3033 with a CPU using single chip packages and four circuit boards, and the IBM 3081, the first mainframe that used the Thermal Conduction Module (TCM).
    [Show full text]
  • Fujitsu AR'99(E)
    50p10/66p2 50p10/66p2 FUJITSU LIMITED FUJITSU LIMITED Annual Report Annual Report 1999 ©1999 6-1, Marunouchi 1-chome, Chiyoda-ku, Tokyo 100-8211, Japan Printed in Japan Telephone: +81-3-3213-4160 BA0013-1M Facsimile: +81-3-3216-9365 This annual report is Homepage URL: http://www.fujitsu.co.jp/index-e.html printed on recycled paper. C4 C1 50p10/66p2 50p10/66p2 Shareholders’ Data 49 CONTENTS Capital: ¥261,222 million Common Stock: Authorized: 5,000,000,000 shares 1 Consolidated Financial Highlights Issued: 1,884,139,404 2 To Our Shareholders Number of Shareholders: 156,110 Percentage of Number of shares total shares 6 Special Feature—Solutions Business Principal Shareholders held (thousands) outstanding 12 State of Readiness for Year 2000 Fuji Electric Co., Ltd. 237,963 12.6% Asahi Mutual Life Insurance Company 117,172 6.2% 13 Consolidated Net Sales and Operating Income The Dai-Ichi Kangyo Bank, Limited 76,817 4.1% by Segment The Sumitomo Trust and Banking Company, Limited (Trust services) 60,851 3.2% 14 Environmental and Social Activities The Chase Manhattan Bank NA London (Standing proxy: The Fuji Bank, Ltd.) 46,437 2.5% 18 Board of Directors and Auditors The Industrial Bank of Japan, Limited 42,202 2.2% 19 Five-Year Summary The Chuo Trust and Banking Company, Limited (Trust services) 38,284 2.0% 20 Management’s Discussion and Analysis of Operations The Mitsubishi Trust and Banking Corporation (Trust services) 38,024 2.0% 24 Consolidated Balance Sheets The Asahi Bank, Ltd. 29,221 1.6% 26 Consolidated Statements of Operations The Sakura Bank, Ltd.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Evaluation of Synthesizable CPU Cores
    Evaluation of synthesizable CPU cores DANIEL MATTSSON MARCUS CHRISTENSSON Maste r ' s Thesis Com p u t e r Science an d Eng i n ee r i n g Pro g r a m CHALMERS UNIVERSITY OF TECHNOLOGY Depart men t of Computer Engineering Gothe n bu r g 20 0 4 All rights reserved. This publication is protected by law in accordance with “Lagen om Upphovsrätt, 1960:729”. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior permission of the authors. Daniel Mattsson and Marcus Christensson, Gothenburg 2004. Evaluation of synthesizable CPU cores Abstract The three synthesizable processors: LEON2 from Gaisler Research, MicroBlaze from Xilinx, and OpenRISC 1200 from OpenCores are evaluated and discussed. Performance in terms of benchmark results and area resource usage is measured. Different aspects like usability and configurability are also reviewed. Three configurations for each of the processors are defined and evaluated: the comparable configuration, the performance optimized configuration and the area optimized configuration. For each of the configurations three benchmarks are executed: the Dhrystone 2.1 benchmark, the Stanford benchmark suite and a typical control application run as a benchmark. A detailed analysis of the three processors and their development tools is presented. The three benchmarks are described and motivated. Conclusions and results in terms of benchmark results, performance per clock cycle and performance per area unit are discussed and presented. Sammanfattning De tre syntetiserbara processorerna: LEON2 från Gaisler Research, MicroBlaze från Xilinx och OpenRISC 1200 från OpenCores utvärderas och diskuteras.
    [Show full text]
  • Jamaicavm Provides Hard Realtime Guarantees for Most Common Realtime Operating Systems Are Sup- All Primitive Java Operations
    ��������� Java-Technology for Critical Embedded Systems ��������� �������� ���������� ����������� ������� ���������� ������� ������� ���������� ����������� ���������� ������ ��������� Java-Tools for developers of critical software applications. Key Technologies Interoperability Hard realtime execution Ported to standard RTOSes The JamaicaVM provides hard realtime guarantees for Most common realtime operating systems are sup- all primitive Java operations. This enables all of Java’s ported by JamaicaVM, ports for VxWorks, QNX, Linux- features to be used for your hard realtime tasks. Fea- variants, RTEMS, etc. exist. The supported architectures tures essential to object-oriented software develop- include SH4, PPC, x86, ARM, XScale, ERC32, and many ment like dynamic allocation of objects, inheritance, more. To support your specific system, we can provide and dynamic binding become available to the real- you with the required porting service. time developer. ROMable code Realtime Garbage Collection Class files and the Jamaica Virtual Machine may be The JamaicaVM provides the only Java implementa- linked into a standalone binary for execution out of tion with an efficient hard realtime garbage collector. ROM. A filesystem in not necessary for running Java It operates in small increments of only a few machine code. instructions and guarantees to recycle all garbage memory, to avoid memory fragmentation, and to Library and JNI Native Code bound the execution time for allocations. Existing library code or low level performance critical code for hardware access can be embedded into Fast & Small your realtime application using the Java Native Inter- A highly optimizing static compiler ensures best runtime face. performance. A profiling tool gathers information for providing the best trade-off between runtime perfor- mance and code size. Jamaica Toolset Sophisticated automatic class file compaction, dead- � � � � � � � � � � code elimination and profile-guided partial compila- tion techniques reduce the code footprint to the bare ���������� minimum.
    [Show full text]