Oracle SPARC Architecture 2011 One Architecture ... Multiple Innovative Implementations Draft D1.0.0, 12 Jan 2016 Privilege Levels: Privileged and Nonprivileged Distribution: Public Part No: 950-5954-00 Revision: Draft D1.0.0, 12 Jan 2016 Oracle Corporation 4150 Network Circle Santa Clara, CA 95054 U.S.A. 650-960-1300 ii Oracle SPARC Architecture 2011 • Draft D1.0.0, 12 Jan 2016 Copyright © 2011, Oracle and/or its affiliates. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective owners. AMD, Opteron, the AMD logo, and the AMD Opteron logo are trademarks or registered trademarks of Advanced Micro Devices. Intel and Intel Xeon are trademarks or registered trademarks of Intel Corporation. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. UNIX is a registered trademark licensed through X/Open Company, Ltd.. Comments and "bug reports” regarding this document are welcome; they should be submitted to email address: [email protected] iv Oracle SPARC Architecture 2011 • Draft D1.0.0, 12 Jan 2016 Contents Preface. i 1 Document Overview . .1 1.1 Navigating Oracle SPARC Architecture 2011 . .1 1.2 Fonts and Notational Conventions . .2 1.2.1 Implementation Dependencies. 3 1.2.2 Notation for Numbers . 3 1.2.3 Informational Notes. 3 1.3 Reporting Errors in this Specification. .4 2 Definitions . 5 3 Architecture Overview. 13 3.1 The Oracle SPARC Architecture 2011 . .13 3.1.1 Features . 13 3.1.2 Attributes . 14 3.1.2.1 Design Goals. .15 3.1.2.2 Register Windows . .15 3.1.3 System Components . 15 3.1.3.1 Binary Compatibility . .15 3.1.3.2 Oracle SPARC Architecture 2011 MMU . .15 3.1.3.3 Privileged Software . .15 3.1.4 Architectural Definition . 16 3.1.5 Oracle SPARC Architecture 2011 Compliance with SPARC V9 Architecture. 16 3.1.6 Implementation Compliance with Oracle SPARC Architecture 2011 . 16 3.2 Processor Architecture . .16 3.2.1 Integer Unit (IU). 16 3.2.2 Floating-Point Unit (FPU). 17 3.3 Instructions . 17 3.3.1 Memory Access . 17 3.3.1.1 Memory Alignment Restrictions . .18 3.3.1.2 Addressing Conventions. .18 3.3.1.3 Addressing Range . .18 3.3.1.4 Load/Store Alternate . .18 3.3.1.5 Separate Instruction and Data Memories . .19 3.3.1.6 Input/Output (I/O). .19 3.3.1.7 Memory Synchronization . .19 3.3.2 Integer Arithmetic / Logical / Shift Instructions . 19 3.3.3 Control Transfer . 20 3.3.4 State Register Access . 20 3.3.4.1 Ancillary State Registers . .20 3.3.4.2 PR State Registers . .20 i 3.3.5 Floating-Point Operate . 21 3.3.6 Conditional Move . 21 3.3.7 Register Window Management . 21 3.3.8 SIMD. 21 3.4 Traps . 21 4 Data Formats. 23 4.1 Integer Data Formats . 24 4.1.1 Signed Integer Data Types . 24 4.1.1.1 Signed Integer Byte, Halfword, and Word. 25 4.1.1.2 Signed Integer Doubleword (64 bits) . 25 4.1.1.3 Signed Integer Extended-Word (64 bits) . 25 4.1.2 Unsigned Integer Data Types . 25 4.1.2.1 Unsigned Integer Byte, Halfword, and Word . 26 4.1.2.2 Unsigned Integer Doubleword (64 bits). 26 4.1.2.3 Unsigned Extended Integer (64 bits) . 26 4.1.3 Tagged Word (32 bits). 26 4.2 Floating-Point Data Formats. 27 4.2.1 Floating Point, Single Precision (32 bits) . 27 4.2.2 Floating Point, Double Precision (64 bits) . 27 4.2.3 Floating Point, Quad Precision (128 bits). 28 4.2.4 Floating-Point Data Alignment in Memory and Registers . 29 4.3 SIMD Data Formats . 29 4.3.1 Uint8 SIMD Data Format . 30 4.3.2 Int16 SIMD Data Formats. 30 4.3.3 Int32 SIMD Data Format . 30 5 Registers . 31 5.1 Reserved Register Fields . .32 5.2 General-Purpose R Registers . 32 5.2.1 Global R Registers. 33 5.2.2 Windowed R Registers . 34 5.2.3 Special R Registers . 37 5.3 Floating-Point Registers . ..